diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-01-30 20:48:02 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-09 13:44:56 -0500 |
commit | 2caea7576a42c5f6593c58229d51f74517e0c60c (patch) | |
tree | 26d652848baede8f822afa8009cae7faa29945ac /include | |
parent | 6c35cebdcb2d14741385cfe051577882a806cdb8 (diff) |
gpu: nvgpu: vgpu: add clear single SM error state
Add support for clearing single SM error state for CUDA debugger.
In addition to clearing local copy of SM error state,
vgpu_gr_clear_sm_error_state now sends a command to RM server
(TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE), to clear global ESR and
warp ESR.
Bug 1791111
Change-Id: I3a1f0644787fd900ec59a0e7974037d46a603487
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1296311
(cherry picked from commit fd07e03c3d086f396e4d65575c576a4dd68c920a)
Reviewed-on: http://git-master/r/1299060
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Tested-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 9ecc44a7..3e3bbf58 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -101,6 +101,7 @@ enum { | |||
101 | TEGRA_VGPU_CMD_GET_GPU_LOAD = 65, | 101 | TEGRA_VGPU_CMD_GET_GPU_LOAD = 65, |
102 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, | 102 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, |
103 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, | 103 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, |
104 | TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, | ||
104 | }; | 105 | }; |
105 | 106 | ||
106 | struct tegra_vgpu_connect_params { | 107 | struct tegra_vgpu_connect_params { |
@@ -462,6 +463,11 @@ struct tegra_vgpu_suspend_resume_contexts { | |||
462 | u16 chids[]; | 463 | u16 chids[]; |
463 | }; | 464 | }; |
464 | 465 | ||
466 | struct tegra_vgpu_clear_sm_error_state { | ||
467 | u64 handle; | ||
468 | u32 sm_id; | ||
469 | }; | ||
470 | |||
465 | struct tegra_vgpu_cmd_msg { | 471 | struct tegra_vgpu_cmd_msg { |
466 | u32 cmd; | 472 | u32 cmd; |
467 | int ret; | 473 | int ret; |
@@ -510,6 +516,7 @@ struct tegra_vgpu_cmd_msg { | |||
510 | struct tegra_vgpu_gpu_load_params gpu_load; | 516 | struct tegra_vgpu_gpu_load_params gpu_load; |
511 | struct tegra_vgpu_suspend_resume_contexts suspend_contexts; | 517 | struct tegra_vgpu_suspend_resume_contexts suspend_contexts; |
512 | struct tegra_vgpu_suspend_resume_contexts resume_contexts; | 518 | struct tegra_vgpu_suspend_resume_contexts resume_contexts; |
519 | struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; | ||
513 | char padding[192]; | 520 | char padding[192]; |
514 | } params; | 521 | } params; |
515 | }; | 522 | }; |