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author | Peter Daifuku <pdaifuku@nvidia.com> | 2016-06-09 19:09:52 -0400 |
---|---|---|
committer | Vladislav Buzov <vbuzov@nvidia.com> | 2016-07-06 18:26:22 -0400 |
commit | 1b04326f400489f25399167ef9f1c931a576656e (patch) | |
tree | 0dca7cf0982773647ca7bee54b2e190e02a97f97 /include | |
parent | da4d5130e81b68d9773c8d64c7a6d944acfac0c8 (diff) |
gpu: nvgpu: vgpu: dbg_set_powergate support
Add support for dbg_set_powergate when virtualized
Jira VFND-1905
Change-Id: I0d81c8863b3eda4ae4fee42e5a95d2fc9d78b174
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1162048
(cherry picked from commit 0dfc55f390a10e21ae13e14dd2f16e89a3bddfa7)
Reviewed-on: http://git-master/r/1167182
(cherry picked from commit 4e34a1844558d93da5ad208532ec28aeda228f95)
Reviewed-on: http://git-master/r/1174701
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 196b08ca..6e8f5d53 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -96,6 +96,7 @@ enum { | |||
96 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, | 96 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, |
97 | TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, | 97 | TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, |
98 | TEGRA_VGPU_CMD_READ_PTIMER = 59, | 98 | TEGRA_VGPU_CMD_READ_PTIMER = 59, |
99 | TEGRA_VGPU_CMD_SET_POWERGATE = 60, | ||
99 | }; | 100 | }; |
100 | 101 | ||
101 | struct tegra_vgpu_connect_params { | 102 | struct tegra_vgpu_connect_params { |
@@ -394,6 +395,10 @@ struct tegra_vgpu_read_ptimer_params { | |||
394 | u64 time; | 395 | u64 time; |
395 | }; | 396 | }; |
396 | 397 | ||
398 | struct tegra_vgpu_set_powergate_params { | ||
399 | u32 mode; | ||
400 | }; | ||
401 | |||
397 | struct tegra_vgpu_cmd_msg { | 402 | struct tegra_vgpu_cmd_msg { |
398 | u32 cmd; | 403 | u32 cmd; |
399 | int ret; | 404 | int ret; |
@@ -435,6 +440,7 @@ struct tegra_vgpu_cmd_msg { | |||
435 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | 440 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; |
436 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; | 441 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; |
437 | struct tegra_vgpu_read_ptimer_params read_ptimer; | 442 | struct tegra_vgpu_read_ptimer_params read_ptimer; |
443 | struct tegra_vgpu_set_powergate_params set_powergate; | ||
438 | char padding[192]; | 444 | char padding[192]; |
439 | } params; | 445 | } params; |
440 | }; | 446 | }; |