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authorSeema Khowala <seemaj@nvidia.com>2017-03-22 12:24:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-23 20:18:28 -0400
commit17df1921807a190d24dbd5b0e0f78192c2e3b772 (patch)
tree9f76ed1e5762e1e2cf57a374fb6cd39facf50af4 /include
parentdf94d474a8200fc61969e2fc35d1b2a8d7fa5b8c (diff)
gpu: nvgpu: gr faults: do not depend on fake mmu fault notifier
Currently NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT is being set in error notifier for non mmu fault too. For fake mmu faults i.e. trigger mmu fault cases, make sure proper notifiers are set and driver is not depending on sending mmu error fault notifier. This change is needed for t19x fifo recovery too. NVGPU_CHANNEL_GR_ERROR_SW_METHOD (12), NVGPU_CHANNEL_GR_EXCEPTION(13) and NVGPU_CHANNEL_FECS_ERR_UNIMP_FIRMWARE_METHOD (37) are new error notifiers. JIRA GPUT19X-7 Change-Id: Idee83e842c835bdba9eb18578aad0c372ea74c5d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/nvgpu.h17
1 files changed, 10 insertions, 7 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 75011998..ca9b49e6 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -1470,13 +1470,16 @@ struct nvgpu_notification {
1470 __u32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 */ 1470 __u32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 */
1471 } time_stamp; /* -0007 */ 1471 } time_stamp; /* -0007 */
1472 __u32 info32; /* info returned depends on method 0008-000b */ 1472 __u32 info32; /* info returned depends on method 0008-000b */
1473#define NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8 1473#define NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8
1474#define NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY 13 1474#define NVGPU_CHANNEL_GR_ERROR_SW_METHOD 12
1475#define NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT 24 1475#define NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY 13
1476#define NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY 25 1476#define NVGPU_CHANNEL_GR_EXCEPTION 13
1477#define NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31 1477#define NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT 24
1478#define NVGPU_CHANNEL_PBDMA_ERROR 32 1478#define NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY 25
1479#define NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR 43 1479#define NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31
1480#define NVGPU_CHANNEL_PBDMA_ERROR 32
1481#define NVGPU_CHANNEL_FECS_ERR_UNIMP_FIRMWARE_METHOD 37
1482#define NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR 43
1480#define NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH 80 1483#define NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH 80
1481 __u16 info16; /* info returned depends on method 000c-000d */ 1484 __u16 info16; /* info returned depends on method 000c-000d */
1482 __u16 status; /* user sets bit 15, NV sets status 000e-000f */ 1485 __u16 status; /* user sets bit 15, NV sets status 000e-000f */