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authorSeema Khowala <seemaj@nvidia.com>2017-09-26 18:08:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-08 07:07:12 -0500
commitec189e454d8fa3defdef1252e149577ce3b6e5b7 (patch)
tree5c5192b37ce6fd9adfe8950ff9defa4ad2d1d426 /include/uapi
parent58dd20f86b3b9faef89b24f2b4ec6b62a183fe9d (diff)
gpu: nvgpu: spew err for pbus interrupt
Spew err message for pri_squash, fecserr and pri_timeout pbus interrupts. If FECS_TGT is set in timeout_save_0, addr, write fields are not reliable. Also timeout_save_1 is unreliable. For both squash and timeout should have correct data most of the time. Even for FECS_TGT, a timeout for a read should indicate the correct transaction as Host only supports one read at a time. It's mostly just writes to FECS that have potentially incorrect information. Bug 200246808 Bug 200350539 Change-Id: I8a992d924ff6c740a8dacecaaaf4ef257756d01d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1568860 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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