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authorDeepak Nibade <dnibade@nvidia.com>2016-04-19 07:27:49 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-09 16:16:29 -0400
commitd868b654419cfa096f563c9281a2a5cc067c23db (patch)
treea11fc30ab435c6e2a4c54b97455d3f5c177ad507 /include/uapi
parentf14152c081d94710dbde843b8dcd9b3981afb831 (diff)
gpu: nvgpu: separate IOCTL to set preemption mode
Add separate IOCTL NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE to allow setting preemption modes from UMD Define preemption modes in nvgpu.h and use them everywhere Remove mode definitions from mm_gk20a.h Also, we support setting only one preemption mode in a channel But it is possible to have multiple preemption modes (one from graphics and one from compute) set simultaneously Hence, update struct gr_ctx_desc to include two separate preemption modes (graphics_preempt_mode and compute_preempt_mode) API NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE also supports setting two separate preemption modes i.e. one for graphics and one for compute Make necessary changes in code to support two preemption modes Bug 1646259 Change-Id: Ia1dea19e609ba8cc0de2f39ab6c0c4cd6b0a752c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1131805 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/linux/nvgpu.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index b8bd21f2..8ebe8d06 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -999,6 +999,16 @@ struct nvgpu_event_id_ctrl_args {
999 999
1000#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 1000#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1
1001 1001
1002struct nvgpu_preemption_mode_args {
1003/* only one should be enabled at a time */
1004#define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI BIT(0)
1005 __u32 graphics_preempt_mode; /* in */
1006
1007/* only one should be enabled at a time */
1008#define NVGPU_COMPUTE_PREEMPTION_MODE_WFI BIT(0)
1009#define NVGPU_COMPUTE_PREEMPTION_MODE_CTA BIT(1)
1010 __u32 compute_preempt_mode; /* in */
1011};
1002 1012
1003#define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ 1013#define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \
1004 _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) 1014 _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args)
@@ -1046,9 +1056,11 @@ struct nvgpu_event_id_ctrl_args {
1046 _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) 1056 _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args)
1047#define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \ 1057#define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \
1048 _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args) 1058 _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args)
1059#define NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE \
1060 _IOW(NVGPU_IOCTL_MAGIC, 122, struct nvgpu_preemption_mode_args)
1049 1061
1050#define NVGPU_IOCTL_CHANNEL_LAST \ 1062#define NVGPU_IOCTL_CHANNEL_LAST \
1051 _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_TIMESLICE) 1063 _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE)
1052#define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) 1064#define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args)
1053 1065
1054/* 1066/*