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author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-03-02 18:36:22 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:58:04 -0400 |
commit | 895675e1d5790e2361b22edb50d702f7dd9a8edd (patch) | |
tree | dbe3586cec5351fd2c2eb13d91c258e663d73b08 /include/uapi | |
parent | cf0085ec231246748b34081d2786c29cedcbd706 (diff) |
gpu: nvgpu: Removal of regops from CUDA driver
The current CUDA drivers have been using the regops to
directly accessing the GPU registers from user space through
the dbg node. This is a security hole and needs to be avoided.
The patch alternatively implements the similar functionality
in the kernel and provide an ioctl for it.
Bug 200083334
Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/711758
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/uapi')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 42 |
1 files changed, 41 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index b04ef2e3..3a7c7831 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -252,6 +252,36 @@ struct nvgpu_gpu_l2_fb_args { | |||
252 | __u32 reserved; | 252 | __u32 reserved; |
253 | } __packed; | 253 | } __packed; |
254 | 254 | ||
255 | struct nvgpu_gpu_inval_icache_args { | ||
256 | int channel_fd; | ||
257 | __u32 reserved; | ||
258 | } __packed; | ||
259 | |||
260 | struct nvgpu_gpu_mmu_debug_mode_args { | ||
261 | __u32 state; | ||
262 | __u32 reserved; | ||
263 | } __packed; | ||
264 | |||
265 | struct nvgpu_gpu_sm_debug_mode_args { | ||
266 | int channel_fd; | ||
267 | __u32 enable; | ||
268 | __u64 sms; | ||
269 | } __packed; | ||
270 | |||
271 | struct warpstate { | ||
272 | __u64 valid_warps; | ||
273 | __u64 trapped_warps; | ||
274 | __u64 paused_warps; | ||
275 | }; | ||
276 | |||
277 | struct nvgpu_gpu_wait_pause_args { | ||
278 | __u64 pwarpstate; | ||
279 | }; | ||
280 | |||
281 | struct nvgpu_gpu_tpc_exception_en_status_args { | ||
282 | __u64 tpc_exception_en_sm_mask; | ||
283 | }; | ||
284 | |||
255 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | 285 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ |
256 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | 286 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) |
257 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | 287 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ |
@@ -276,9 +306,19 @@ struct nvgpu_gpu_l2_fb_args { | |||
276 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args) | 306 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args) |
277 | #define NVGPU_GPU_IOCTL_FLUSH_L2 \ | 307 | #define NVGPU_GPU_IOCTL_FLUSH_L2 \ |
278 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_gpu_l2_fb_args) | 308 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_gpu_l2_fb_args) |
309 | #define NVGPU_GPU_IOCTL_INVAL_ICACHE \ | ||
310 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 13, struct nvgpu_gpu_inval_icache_args) | ||
311 | #define NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE \ | ||
312 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 14, struct nvgpu_gpu_mmu_debug_mode_args) | ||
313 | #define NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE \ | ||
314 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 15, struct nvgpu_gpu_sm_debug_mode_args) | ||
315 | #define NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE \ | ||
316 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 16, struct nvgpu_gpu_wait_pause_args) | ||
317 | #define NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS \ | ||
318 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 17, struct nvgpu_gpu_tpc_exception_en_status_args) | ||
279 | 319 | ||
280 | #define NVGPU_GPU_IOCTL_LAST \ | 320 | #define NVGPU_GPU_IOCTL_LAST \ |
281 | _IOC_NR(NVGPU_GPU_IOCTL_FLUSH_L2) | 321 | _IOC_NR(NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS) |
282 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | 322 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ |
283 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) | 323 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) |
284 | 324 | ||