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| author | Vijayakumar <vsubbu@nvidia.com> | 2016-05-17 07:28:03 -0400 |
|---|---|---|
| committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-24 15:59:24 -0400 |
| commit | 0d2b93ac3742422386853a2d9e562a673a6424a8 (patch) | |
| tree | f804fd7a45041b4607fc128bbc525a5567aa2312 /include/uapi | |
| parent | 3e431e26c5c3aba6da8a6555ec3d7b7df53f534a (diff) | |
gpu:nvgpu:gm20b: update elpg prod settings
bug 1764398
PGSequencer settings use index to writ to PSORDER register setting.
HW has implementation for 28 PSORDER (PSORDER0 - 27).
Every write will auto increment index and index will wrap around
after it reaches 27.
In PROD settings we are writing enable for 0 to 27 and
zero for 28 to 65. This overwrites enables written to 0 to 27.
Effectively those partitions are never power gated.
P4 SWCL# 20744424
Change-Id: I45826e98dd6a84e9c4fe119fbe7ca75acfd8a4ea
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1149055
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/uapi')
0 files changed, 0 insertions, 0 deletions