gpu: nvgpu: remove channel cycle stats ioctls

Cycle stats and cycle stats snapshot ioctls have been moved to
debug node. Removing channel ioctls.

Bug 2660206
Bug 220464613

Change-Id: I3aecdf4a8310eeb38de2de5ac076048891afe436
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030992
(cherry picked from commit f20424ea6a7c6fcf977630e3e95d9e78418f13b8)
Signed-off-by: Gagan Grover <ggrover@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2092020
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Daifuku <pdaifuku@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 25 deletions

diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 2c130d82..873e787f 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -114,9 +114,9 @@ struct nvgpu_gpu_zbc_query_table_args {
 #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS           (1ULL << 2)
 /* sync fence FDs are available in, e.g., submit_gpfifo */
 #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS          (1ULL << 3)
-/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */
+/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
 #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS             (1ULL << 4)
-/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */
+/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
 #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT    (1ULL << 6)
 /* User-space managed address spaces support */
 #define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS    (1ULL << 7)
@@ -1624,11 +1624,6 @@ struct nvgpu_wait_args {
         } condition; /* determined by type field */
 };
 
-/* cycle stats support */
-struct nvgpu_cycle_stats_args {
-        __u32 dmabuf_fd;
-} __packed;
-
 struct nvgpu_set_timeout_args {
         __u32 timeout;
 } __packed;
@@ -1677,20 +1672,6 @@ struct nvgpu_notification {
 #define NVGPU_CHANNEL_SUBMIT_TIMEOUT            1
 };
 
-/* cycle stats snapshot buffer support for mode E */
-struct nvgpu_cycle_stats_snapshot_args {
-        __u32 cmd;              /* in: command to handle     */
-        __u32 dmabuf_fd;        /* in: dma buffer handler    */
-        __u32 extra;            /* in/out: extra payload e.g.*/
-                                /*    counter/start perfmon  */
-        __u32 pad0[1];
-};
-
-/* valid commands to control cycle stats shared buffer */
-#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH   0
-#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH  1
-#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH  2
-
 /* configure watchdog per-channel */
 struct nvgpu_channel_wdt_args {
         __u32 wdt_status;
@@ -1789,8 +1770,6 @@ struct nvgpu_reschedule_runlist_args {
         _IOW(NVGPU_IOCTL_MAGIC,  100, struct nvgpu_alloc_gpfifo_args)
 #define NVGPU_IOCTL_CHANNEL_WAIT                \
         _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args)
-#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS \
-        _IOWR(NVGPU_IOCTL_MAGIC, 106, struct nvgpu_cycle_stats_args)
 #define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO       \
         _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args)
 #define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX       \
@@ -1811,8 +1790,6 @@ struct nvgpu_reschedule_runlist_args {
         _IO(NVGPU_IOCTL_MAGIC,  116)
 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \
         _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args)
-#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT        \
-        _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args)
 #define NVGPU_IOCTL_CHANNEL_WDT \
         _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args)
 #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \