diff options
author | Vinod G <vinodg@nvidia.com> | 2018-08-08 02:09:30 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-25 05:10:43 -0400 |
commit | bfe65407bde2b5d0776724301e215c6553c989f3 (patch) | |
tree | f68a01361052afe1c30a0c6dcd5d359b762e647a /include/uapi/linux | |
parent | 3bd47da0954d3486d9ccd3c396f84445918f82b4 (diff) |
gpu: nvgpu: Read sm error ioctl support for tsg
Add READ_SM_ERROR IOCTL support to TSG level.
Moved the struct to save the sm_error details
from gr to tsg as the sm_error support is context
based, not global.
Also corrected MISRA 21.1 error in header file.
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and
nvgpu_dbg_gpu_ioctl_read_single_sm_error_state
functions are modified to use the tsg struct
nvgpu_tsg_sm_error_state.
Bug 200412642
Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794856
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/uapi/linux')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 8d884872..b1dc4df4 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -861,38 +861,6 @@ struct nvgpu_gpu_set_deterministic_opts_args { | |||
861 | __u64 channels; /* in */ | 861 | __u64 channels; /* in */ |
862 | }; | 862 | }; |
863 | 863 | ||
864 | /* | ||
865 | * This struct helps to report the SM error state of a single SM. | ||
866 | * This acts upon the currently resident GR context. | ||
867 | * Global Error status register | ||
868 | * Warp Error status register | ||
869 | * Warp Error status register PC | ||
870 | * Global Error status register Report Mask | ||
871 | * Warp Error status register Report Mask | ||
872 | */ | ||
873 | struct nvgpu_gpu_sm_error_state_record { | ||
874 | __u32 global_esr; | ||
875 | __u32 warp_esr; | ||
876 | __u64 warp_esr_pc; | ||
877 | __u32 global_esr_report_mask; | ||
878 | __u32 warp_esr_report_mask; | ||
879 | }; | ||
880 | |||
881 | /* | ||
882 | * This struct helps to read the SM error state. | ||
883 | */ | ||
884 | struct nvgpu_gpu_read_single_sm_error_state_args { | ||
885 | /* Valid SM ID */ | ||
886 | __u32 sm_id; | ||
887 | __u32 reserved; | ||
888 | /* | ||
889 | * This is pointer to the struct nvgpu_gpu_sm_error_state_record | ||
890 | */ | ||
891 | __u64 record_mem; | ||
892 | /* size of the record size to read */ | ||
893 | __u64 record_size; | ||
894 | }; | ||
895 | |||
896 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | 864 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ |
897 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | 865 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) |
898 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | 866 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ |
@@ -976,11 +944,8 @@ struct nvgpu_gpu_read_single_sm_error_state_args { | |||
976 | #define NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS \ | 944 | #define NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS \ |
977 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 40, \ | 945 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 40, \ |
978 | struct nvgpu_gpu_set_deterministic_opts_args) | 946 | struct nvgpu_gpu_set_deterministic_opts_args) |
979 | #define NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE \ | ||
980 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 41, \ | ||
981 | struct nvgpu_gpu_read_single_sm_error_state_args) | ||
982 | #define NVGPU_GPU_IOCTL_LAST \ | 947 | #define NVGPU_GPU_IOCTL_LAST \ |
983 | _IOC_NR(NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE) | 948 | _IOC_NR(NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS) |
984 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | 949 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ |
985 | sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args) | 950 | sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args) |
986 | 951 | ||
@@ -1063,6 +1028,38 @@ struct nvgpu_tsg_bind_channel_ex_args { | |||
1063 | __u8 reserved[11]; | 1028 | __u8 reserved[11]; |
1064 | }; | 1029 | }; |
1065 | 1030 | ||
1031 | /* | ||
1032 | * This struct helps to report the SM error state of a single SM. | ||
1033 | * This acts upon the currently resident TSG context. | ||
1034 | * Global Error status register | ||
1035 | * Warp Error status register | ||
1036 | * Warp Error status register PC | ||
1037 | * Global Error status register Report Mask | ||
1038 | * Warp Error status register Report Mask | ||
1039 | */ | ||
1040 | struct nvgpu_tsg_sm_error_state_record { | ||
1041 | __u32 global_esr; | ||
1042 | __u32 warp_esr; | ||
1043 | __u64 warp_esr_pc; | ||
1044 | __u32 global_esr_report_mask; | ||
1045 | __u32 warp_esr_report_mask; | ||
1046 | }; | ||
1047 | |||
1048 | /* | ||
1049 | * This struct helps to read the SM error state. | ||
1050 | */ | ||
1051 | struct nvgpu_tsg_read_single_sm_error_state_args { | ||
1052 | /* Valid SM ID */ | ||
1053 | __u32 sm_id; | ||
1054 | __u32 reserved; | ||
1055 | /* | ||
1056 | * This is pointer to the struct nvgpu_gpu_sm_error_state_record | ||
1057 | */ | ||
1058 | __u64 record_mem; | ||
1059 | /* size of the record size to read */ | ||
1060 | __u64 record_size; | ||
1061 | }; | ||
1062 | |||
1066 | #define NVGPU_TSG_IOCTL_BIND_CHANNEL \ | 1063 | #define NVGPU_TSG_IOCTL_BIND_CHANNEL \ |
1067 | _IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int) | 1064 | _IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int) |
1068 | #define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \ | 1065 | #define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \ |
@@ -1083,10 +1080,13 @@ struct nvgpu_tsg_bind_channel_ex_args { | |||
1083 | _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) | 1080 | _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) |
1084 | #define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \ | 1081 | #define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \ |
1085 | _IOWR(NVGPU_TSG_IOCTL_MAGIC, 11, struct nvgpu_tsg_bind_channel_ex_args) | 1082 | _IOWR(NVGPU_TSG_IOCTL_MAGIC, 11, struct nvgpu_tsg_bind_channel_ex_args) |
1083 | #define NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE \ | ||
1084 | _IOR(NVGPU_TSG_IOCTL_MAGIC, 12, \ | ||
1085 | struct nvgpu_tsg_read_single_sm_error_state_args) | ||
1086 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ | 1086 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ |
1087 | sizeof(struct nvgpu_tsg_bind_channel_ex_args) | 1087 | sizeof(struct nvgpu_tsg_bind_channel_ex_args) |
1088 | #define NVGPU_TSG_IOCTL_LAST \ | 1088 | #define NVGPU_TSG_IOCTL_LAST \ |
1089 | _IOC_NR(NVGPU_TSG_IOCTL_BIND_CHANNEL_EX) | 1089 | _IOC_NR(NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE) |
1090 | 1090 | ||
1091 | /* | 1091 | /* |
1092 | * /dev/nvhost-dbg-gpu device | 1092 | * /dev/nvhost-dbg-gpu device |