diff options
author | Vinod G <vinodg@nvidia.com> | 2018-05-24 17:00:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-08 07:27:28 -0400 |
commit | a09b9cd587d27a3ef6479a17631c3497d447e7a9 (patch) | |
tree | df543902311f6c0e87458041e13b9f569fc92318 /include/uapi/linux | |
parent | 32bcf21f5712fcd872b26ec70ad8987f7db4478f (diff) |
gpu: nvgpu: Add IOCTL for SM_EXCEPTION_TYPE_MASK
Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is
added to dbg session.
Currently support SM_EXCEPTION_TYPE_MASK_FATAL type
If this type is set then the code will skip RC recovery,
instead trigger CILP preemption.
bug 200412641
JIRA NVGPU-702
Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729792
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/uapi/linux')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 446f5bd3..0733a7b2 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -1411,8 +1411,27 @@ struct nvgpu_dbg_gpu_profiler_reserve_args { | |||
1411 | #define NVGPU_DBG_GPU_IOCTL_PROFILER_RESERVE \ | 1411 | #define NVGPU_DBG_GPU_IOCTL_PROFILER_RESERVE \ |
1412 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 22, struct nvgpu_dbg_gpu_profiler_reserve_args) | 1412 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 22, struct nvgpu_dbg_gpu_profiler_reserve_args) |
1413 | 1413 | ||
1414 | /* | ||
1415 | * This struct helps to set the exception mask. If mask is not set | ||
1416 | * or set to NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_NONE | ||
1417 | * then kernel code will follow recovery path on sm exception. | ||
1418 | * If mask is set to NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL, then | ||
1419 | * kernel code will skip recovery path on sm exception. | ||
1420 | */ | ||
1421 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args { | ||
1422 | #define NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) | ||
1423 | #define NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0U) | ||
1424 | /* exception type mask value */ | ||
1425 | __u32 exception_type_mask; | ||
1426 | __u32 reserved; | ||
1427 | }; | ||
1428 | |||
1429 | #define NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK \ | ||
1430 | _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 23, \ | ||
1431 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args) | ||
1432 | |||
1414 | #define NVGPU_DBG_GPU_IOCTL_LAST \ | 1433 | #define NVGPU_DBG_GPU_IOCTL_LAST \ |
1415 | _IOC_NR(NVGPU_DBG_GPU_IOCTL_PROFILER_RESERVE) | 1434 | _IOC_NR(NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK) |
1416 | 1435 | ||
1417 | #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ | 1436 | #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ |
1418 | sizeof(struct nvgpu_dbg_gpu_access_fb_memory_args) | 1437 | sizeof(struct nvgpu_dbg_gpu_access_fb_memory_args) |