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| author | Deepak Nibade <dnibade@nvidia.com> | 2014-10-01 11:53:49 -0400 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:10 -0400 |
| commit | f8f6b298848ed05ad83ce107ff8a4fff0b37dd2d (patch) | |
| tree | 554d121fbbc47745556cd6a99c6b5d6258951b80 /include/uapi/linux/nvgpu.h | |
| parent | 6275bbb33bb0f72cc03c7e68d8186b36c96ee854 (diff) | |
gpu: nvgpu: support config of TPC FUSE dynamically
Follow steps below to config active TPC number:
echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle
echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask
echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle
where,
0x1 : disable TPC1
0x2 : disable TPC0
0x3 : both TPCs active
Also, add API set_gpc_tpc_mask to update the TPCs and call this
API after update to sysfs "tpc_fs_mask"
Once fuses are updated for new TPC settings, we need to
reconfigure GR and golden_image. Hence disable gr->sw_ready
and golden_image_initialized flags.
Also, initialize gr->tpc_count = 0 each time in
gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count
Bug 1513685
Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/552606
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Diffstat (limited to 'include/uapi/linux/nvgpu.h')
0 files changed, 0 insertions, 0 deletions