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author | Thomas Fleury <tfleury@nvidia.com> | 2019-02-28 18:01:09 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-07-27 17:55:13 -0400 |
commit | ea40ac7e86eb398e390280e5fa25a710fdbbbea8 (patch) | |
tree | befd58c0badba4131ab2c604bba06943c80146c5 /include/uapi/linux/nvgpu.h | |
parent | 5ecc45b5e7f16e00b2407d4259759228ccbdcf4b (diff) |
gpu: nvgpu: remove channel cycle stats ioctls
Cycle stats and cycle stats snapshot ioctls have been moved to
debug node. Removing channel ioctls.
Bug 2660206
Bug 220464613
Change-Id: I3aecdf4a8310eeb38de2de5ac076048891afe436
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030992
(cherry picked from commit f20424ea6a7c6fcf977630e3e95d9e78418f13b8)
Signed-off-by: Gagan Grover <ggrover@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2092020
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Daifuku <pdaifuku@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/uapi/linux/nvgpu.h')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 27 |
1 files changed, 2 insertions, 25 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 2c130d82..873e787f 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -114,9 +114,9 @@ struct nvgpu_gpu_zbc_query_table_args { | |||
114 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2) | 114 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2) |
115 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | 115 | /* sync fence FDs are available in, e.g., submit_gpfifo */ |
116 | #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3) | 116 | #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3) |
117 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ | 117 | /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */ |
118 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4) | 118 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4) |
119 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ | 119 | /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */ |
120 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6) | 120 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6) |
121 | /* User-space managed address spaces support */ | 121 | /* User-space managed address spaces support */ |
122 | #define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7) | 122 | #define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7) |
@@ -1624,11 +1624,6 @@ struct nvgpu_wait_args { | |||
1624 | } condition; /* determined by type field */ | 1624 | } condition; /* determined by type field */ |
1625 | }; | 1625 | }; |
1626 | 1626 | ||
1627 | /* cycle stats support */ | ||
1628 | struct nvgpu_cycle_stats_args { | ||
1629 | __u32 dmabuf_fd; | ||
1630 | } __packed; | ||
1631 | |||
1632 | struct nvgpu_set_timeout_args { | 1627 | struct nvgpu_set_timeout_args { |
1633 | __u32 timeout; | 1628 | __u32 timeout; |
1634 | } __packed; | 1629 | } __packed; |
@@ -1677,20 +1672,6 @@ struct nvgpu_notification { | |||
1677 | #define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 | 1672 | #define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 |
1678 | }; | 1673 | }; |
1679 | 1674 | ||
1680 | /* cycle stats snapshot buffer support for mode E */ | ||
1681 | struct nvgpu_cycle_stats_snapshot_args { | ||
1682 | __u32 cmd; /* in: command to handle */ | ||
1683 | __u32 dmabuf_fd; /* in: dma buffer handler */ | ||
1684 | __u32 extra; /* in/out: extra payload e.g.*/ | ||
1685 | /* counter/start perfmon */ | ||
1686 | __u32 pad0[1]; | ||
1687 | }; | ||
1688 | |||
1689 | /* valid commands to control cycle stats shared buffer */ | ||
1690 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH 0 | ||
1691 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH 1 | ||
1692 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH 2 | ||
1693 | |||
1694 | /* configure watchdog per-channel */ | 1675 | /* configure watchdog per-channel */ |
1695 | struct nvgpu_channel_wdt_args { | 1676 | struct nvgpu_channel_wdt_args { |
1696 | __u32 wdt_status; | 1677 | __u32 wdt_status; |
@@ -1789,8 +1770,6 @@ struct nvgpu_reschedule_runlist_args { | |||
1789 | _IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args) | 1770 | _IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args) |
1790 | #define NVGPU_IOCTL_CHANNEL_WAIT \ | 1771 | #define NVGPU_IOCTL_CHANNEL_WAIT \ |
1791 | _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args) | 1772 | _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args) |
1792 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS \ | ||
1793 | _IOWR(NVGPU_IOCTL_MAGIC, 106, struct nvgpu_cycle_stats_args) | ||
1794 | #define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \ | 1773 | #define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \ |
1795 | _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args) | 1774 | _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args) |
1796 | #define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \ | 1775 | #define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \ |
@@ -1811,8 +1790,6 @@ struct nvgpu_reschedule_runlist_args { | |||
1811 | _IO(NVGPU_IOCTL_MAGIC, 116) | 1790 | _IO(NVGPU_IOCTL_MAGIC, 116) |
1812 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \ | 1791 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \ |
1813 | _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args) | 1792 | _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args) |
1814 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \ | ||
1815 | _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args) | ||
1816 | #define NVGPU_IOCTL_CHANNEL_WDT \ | 1793 | #define NVGPU_IOCTL_CHANNEL_WDT \ |
1817 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) | 1794 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) |
1818 | #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ | 1795 | #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ |