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author | Deepak Nibade <dnibade@nvidia.com> | 2016-03-31 03:03:19 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-07 11:43:49 -0400 |
commit | e87ba53235151cccee181489ceb5e35b131e7d2d (patch) | |
tree | 478b71365cebaab36879c1020c6582842c8d5760 /include/uapi/linux/nvgpu.h | |
parent | 76ab6c1e5b351b069cde3ae8137e3fbdf4994d16 (diff) |
gpu: nvgpu: add channel event id support
With NVGPU_IOCTL_CHANNEL_EVENTS_CTRL, nvgpu can
raise events to User space. But user space
cannot distinguish between various types of events.
To overcome this, we need finer-grained API to
deliver various events to user space.
Remove old API NVGPU_IOCTL_CHANNEL_EVENTS_CTRL,
and all the support for this API (we can remove
this since User space has not started using this
API at all)
Add new API NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL
which will accept an event_id (like BPT.INT or
BPT.PAUSE), a command to enable the event,
and return a file descriptor on which
we can raise the event (if cmd=enable)
Event is disabled when file descriptor is closed
Add file operations "gk20a_event_id_ops"
to support polling on event fd
Also add API gk20a_channel_get_event_data_from_id()
to get event_data of event from its id
Bug 200089620
Change-Id: I5288f19f38ff49448c46338c33b2a927c9e02254
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1030775
(cherry picked from commit 5721ce2735950440bedc2b86f851db08ed593275)
Reviewed-on: http://git-master/r/1120318
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'include/uapi/linux/nvgpu.h')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 64ac45b5..6fed9e9f 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -825,17 +825,6 @@ struct nvgpu_notification { | |||
825 | #define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 | 825 | #define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 |
826 | }; | 826 | }; |
827 | 827 | ||
828 | /* Enable/disable/clear event notifications */ | ||
829 | struct nvgpu_channel_events_ctrl_args { | ||
830 | __u32 cmd; /* in */ | ||
831 | __u32 _pad0[1]; | ||
832 | }; | ||
833 | |||
834 | /* valid event ctrl values */ | ||
835 | #define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_DISABLE 0 | ||
836 | #define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_ENABLE 1 | ||
837 | #define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_CLEAR 2 | ||
838 | |||
839 | /* cycle stats snapshot buffer support for mode E */ | 828 | /* cycle stats snapshot buffer support for mode E */ |
840 | struct nvgpu_cycle_stats_snapshot_args { | 829 | struct nvgpu_cycle_stats_snapshot_args { |
841 | __u32 cmd; /* in: command to handle */ | 830 | __u32 cmd; /* in: command to handle */ |
@@ -886,6 +875,20 @@ struct nvgpu_timeslice_args { | |||
886 | __u32 reserved; | 875 | __u32 reserved; |
887 | }; | 876 | }; |
888 | 877 | ||
878 | struct nvgpu_event_id_ctrl_args { | ||
879 | __u32 cmd; /* in */ | ||
880 | __u32 event_id; /* in */ | ||
881 | __s32 event_fd; /* out */ | ||
882 | __u32 padding; | ||
883 | }; | ||
884 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 | ||
885 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 | ||
886 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 | ||
887 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 5 | ||
888 | |||
889 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 | ||
890 | |||
891 | |||
889 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ | 892 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ |
890 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) | 893 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) |
891 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ | 894 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ |
@@ -922,8 +925,8 @@ struct nvgpu_timeslice_args { | |||
922 | _IO(NVGPU_IOCTL_MAGIC, 115) | 925 | _IO(NVGPU_IOCTL_MAGIC, 115) |
923 | #define NVGPU_IOCTL_CHANNEL_FORCE_RESET \ | 926 | #define NVGPU_IOCTL_CHANNEL_FORCE_RESET \ |
924 | _IO(NVGPU_IOCTL_MAGIC, 116) | 927 | _IO(NVGPU_IOCTL_MAGIC, 116) |
925 | #define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL \ | 928 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \ |
926 | _IOW(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_channel_events_ctrl_args) | 929 | _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args) |
927 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \ | 930 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \ |
928 | _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args) | 931 | _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args) |
929 | #define NVGPU_IOCTL_CHANNEL_WDT \ | 932 | #define NVGPU_IOCTL_CHANNEL_WDT \ |