diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-03-09 04:21:43 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-19 11:07:03 -0400 |
commit | 04e45bc943e9703c26f229dfbe558d94418acbe1 (patch) | |
tree | 541c62a32055255e82cc953b79b50c8925903f12 /include/uapi/linux/nvgpu.h | |
parent | 9cf7e23f57d8669d99886a3c82d4997b94c35df8 (diff) |
gpu: nvgpu: support storing/reading single SM error state
Add support to store error state of single SM before
preprocessing SM exception
Error state is stored as :
struct nvgpu_dbg_gpu_sm_error_state_record {
u32 hww_global_esr;
u32 hww_warp_esr;
u64 hww_warp_esr_pc;
u32 hww_global_esr_report_mask;
u32 hww_warp_esr_report_mask;
}
Note that we can safely append new fields to above
structure in the future if required
Also, add IOCTL NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE
to support reading SM's error state by user space
Bug 200156699
Change-Id: I9a62cb01e8a35c720b52d5d202986347706c7308
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1120329
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/uapi/linux/nvgpu.h')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 16d60261..96619015 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -676,8 +676,35 @@ struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args { | |||
676 | #define NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE \ | 676 | #define NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE \ |
677 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 13, struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args) | 677 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 13, struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args) |
678 | 678 | ||
679 | |||
680 | struct nvgpu_dbg_gpu_sm_error_state_record { | ||
681 | __u32 hww_global_esr; | ||
682 | __u32 hww_warp_esr; | ||
683 | __u64 hww_warp_esr_pc; | ||
684 | __u32 hww_global_esr_report_mask; | ||
685 | __u32 hww_warp_esr_report_mask; | ||
686 | |||
687 | /* | ||
688 | * Notes | ||
689 | * - This struct can be safely appended with new fields. However, always | ||
690 | * keep the structure size multiple of 8 and make sure that the binary | ||
691 | * layout does not change between 32-bit and 64-bit architectures. | ||
692 | */ | ||
693 | }; | ||
694 | |||
695 | struct nvgpu_dbg_gpu_read_single_sm_error_state_args { | ||
696 | __u32 sm_id; | ||
697 | __u32 padding; | ||
698 | __u64 sm_error_state_record_mem; | ||
699 | __u64 sm_error_state_record_size; | ||
700 | }; | ||
701 | |||
702 | #define NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE \ | ||
703 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 14, struct nvgpu_dbg_gpu_read_single_sm_error_state_args) | ||
704 | |||
705 | |||
679 | #define NVGPU_DBG_GPU_IOCTL_LAST \ | 706 | #define NVGPU_DBG_GPU_IOCTL_LAST \ |
680 | _IOC_NR(NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE) | 707 | _IOC_NR(NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE) |
681 | 708 | ||
682 | #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ | 709 | #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ |
683 | sizeof(struct nvgpu_dbg_gpu_perfbuf_map_args) | 710 | sizeof(struct nvgpu_dbg_gpu_perfbuf_map_args) |