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authorseshendra Gadagottu <sgadagottu@nvidia.com>2017-06-29 18:59:05 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-05 18:40:25 -0400
commit6d758eb81bcbff4e50df5c9fa67a369a4e1f2074 (patch)
tree8b6f62c1cb64f878c13746b8f14d42a2d45105e6 /include/uapi/linux/nvgpu-t19x.h
parent37fa5128ec260bc9ebb2e902ac2dfe9baead4656 (diff)
gpu: nvgpu: gv11b: support for full subcontext
Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'include/uapi/linux/nvgpu-t19x.h')
-rw-r--r--include/uapi/linux/nvgpu-t19x.h22
1 files changed, 21 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h
index 6a10fb77..96514a88 100644
--- a/include/uapi/linux/nvgpu-t19x.h
+++ b/include/uapi/linux/nvgpu-t19x.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * NVGPU Public Interface Header 2 * NVGPU Public Interface Header
3 * 3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -27,4 +27,24 @@
27#define NVGPU_GPU_ARCH_GV110 0x00000150 27#define NVGPU_GPU_ARCH_GV110 0x00000150
28#define NVGPU_GPU_IMPL_GV11B 0x0000000B 28#define NVGPU_GPU_IMPL_GV11B 0x0000000B
29 29
30/* subcontexts are available */
31#define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22)
32
33struct nvgpu_tsg_bind_channel_ex_args {
34 /* in: channel fd */
35 __s32 channel_fd;
36
37 /* in: VEID in Volta */
38 __u32 subcontext_id;
39
40 __u64 reserved[2];
41};
42
43#define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \
44 _IOWR(NVGPU_TSG_IOCTL_MAGIC, 11, struct nvgpu_tsg_bind_channel_ex_args)
45
46#define NVGPU_TSG_IOCTL_MAX NVGPU_TSG_IOCTL_BIND_CHANNEL_EX
47
48#define NVGPU_TSG_IOCTL_MAX_ARG sizeof(struct nvgpu_tsg_bind_channel_ex_args)
49
30#endif /* _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ */ 50#endif /* _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ */