diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-07-25 02:18:20 -0400 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:37 -0400 |
| commit | 14f47ad1f01fe7dce06081072bc8a03ea80841c2 (patch) | |
| tree | 89d67a87a3ea911ee7e9a6aab1ca7f21f60c7402 /include/trace | |
| parent | 14315a95613f7323283c70cf14d870e58b8bdb54 (diff) | |
gpu: nvgpu: Update GM20b GPCPLL initial configuration
- Set initial output rate to 1/3 of VCO minimum.
- Cleared global BYPASSCTRL to get ready for enabling PLL (this
won't bring PLL out of bypass, since SEL_VCO register is cleared).
- Added debugfs nodes for BYPASSCTRL and SEL_VCO state.
Bug 1450787
Change-Id: I10b068b006b7e9fbdf7854eff0cfd5cfdc1dd546
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447750
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'include/trace')
0 files changed, 0 insertions, 0 deletions