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authorAlex Van Brunt <avanbrunt@nvidia.com>2016-04-04 12:22:01 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:11 -0500
commitaed4008ffae6532033b2ba6ea9bed4b3e7979de5 (patch)
tree2a5be21b094c1683779bddf7333bc29070d5c88b /include/linux
parent0a98bb9fcf09eaf6f39aa8a5bc69c1457c11933a (diff)
include: linux: import tegra_vgpu_t18x.h from kernel-t18x
include/linux/tegra_vgpu_t18x.h was missed while spliting the nvgpu driver off. This patch imports it into the nvgpu repo. bug 200187033 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Change-Id: Ia46384241bd0e24a8a560c3b13b5fd3523c9cc68 Reviewed-on: http://git-master/r/1119779 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/tegra_vgpu_t18x.h42
1 files changed, 42 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu_t18x.h b/include/linux/tegra_vgpu_t18x.h
new file mode 100644
index 00000000..121f4103
--- /dev/null
+++ b/include/linux/tegra_vgpu_t18x.h
@@ -0,0 +1,42 @@
1/*
2 * Tegra GPU Virtualization Interfaces to Server
3 *
4 * Copyright (c) 2015, NVIDIA Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __TEGRA_VGPU_T18X_H
20#define __TEGRA_VGPU_T18X_H
21
22enum {
23 TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN,
24 TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL,
25 TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL,
26 TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB,
27 TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST
28};
29
30enum {
31 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI,
32 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP,
33 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA,
34 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP,
35 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST
36};
37
38enum {
39 TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64
40};
41
42#endif