diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-10-16 11:58:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-08 22:26:30 -0500 |
commit | 738bee03730a905d98361cd1260f9b79e3c12bf7 (patch) | |
tree | c82887ee55df77fe8409edac086a973df193d989 /include/linux/tegra_vgpu_t19x.h | |
parent | 075852f042b9b3a3d48180378e6d2a709708cc41 (diff) |
gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channel
Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id
and runqueu_sel to RM server. Use this command in gv11b's
implementation of gops->fifo.tsg_bind_channel.
Jira EVLR-1751
Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579840
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu_t19x.h')
-rw-r--r-- | include/linux/tegra_vgpu_t19x.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index fe39230e..38dbbf60 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h | |||
@@ -17,6 +17,7 @@ | |||
17 | #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 | 17 | #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 |
18 | #define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 | 18 | #define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 |
19 | #define TEGRA_VGPU_CMD_MAP_SYNCPT 102 | 19 | #define TEGRA_VGPU_CMD_MAP_SYNCPT 102 |
20 | #define TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX 103 | ||
20 | 21 | ||
21 | struct tegra_vgpu_alloc_ctx_header_params { | 22 | struct tegra_vgpu_alloc_ctx_header_params { |
22 | u64 ch_handle; | 23 | u64 ch_handle; |
@@ -35,10 +36,18 @@ struct tegra_vgpu_map_syncpt_params { | |||
35 | u8 prot; | 36 | u8 prot; |
36 | }; | 37 | }; |
37 | 38 | ||
39 | struct tegra_vgpu_tsg_bind_channel_ex_params { | ||
40 | u32 tsg_id; | ||
41 | u64 ch_handle; | ||
42 | u32 subctx_id; | ||
43 | u32 runqueue_sel; | ||
44 | }; | ||
45 | |||
38 | union tegra_vgpu_t19x_params { | 46 | union tegra_vgpu_t19x_params { |
39 | struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; | 47 | struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; |
40 | struct tegra_vgpu_free_ctx_header_params free_ctx_header; | 48 | struct tegra_vgpu_free_ctx_header_params free_ctx_header; |
41 | struct tegra_vgpu_map_syncpt_params map_syncpt; | 49 | struct tegra_vgpu_map_syncpt_params map_syncpt; |
50 | struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; | ||
42 | }; | 51 | }; |
43 | 52 | ||
44 | #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 | 53 | #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 |