gpu: nvgpu: add zbc support to vgpu

For both adding and querying zbc entry, added callbacks in gr ops.
Native gpu driver (gk20a) and vgpu will both hook there. For vgpu, it
will add or query zbc entry from RM server.

Bug 1558561

Change-Id: If8a4850ecfbff41d8592664f5f93ad8c25f6fbce
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/732775
(cherry picked from commit a3787cf971128904c2712338087685b02673065d)
Reviewed-on: http://git-master/r/737880
(cherry picked from commit fca2a0457c968656dc29455608f35acab094d816)
Reviewed-on: http://git-master/r/753278
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 28 insertions, 1 deletions

diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index e1674440..a295c9ef 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -62,7 +62,9 @@ enum {
         TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL,
         TEGRA_VGPU_CMD_CACHE_MAINT,
         TEGRA_VGPU_CMD_SUBMIT_RUNLIST,
-        TEGRA_VGPU_CMD_GET_ZCULL_INFO
+        TEGRA_VGPU_CMD_GET_ZCULL_INFO,
+        TEGRA_VGPU_CMD_ZBC_SET_TABLE,
+        TEGRA_VGPU_CMD_ZBC_QUERY_TABLE
 };
 
 struct tegra_vgpu_connect_params {
@@ -191,6 +193,29 @@ struct tegra_vgpu_zcull_info_params {
         u32 subregion_count;
 };
 
+#define TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE         4
+#define TEGRA_VGPU_ZBC_TYPE_INVALID             0
+#define TEGRA_VGPU_ZBC_TYPE_COLOR               1
+#define TEGRA_VGPU_ZBC_TYPE_DEPTH               2
+
+struct tegra_vgpu_zbc_set_table_params {
+        u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
+        u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
+        u32 depth;
+        u32 format;
+        u32 type;     /* color or depth */
+};
+
+struct tegra_vgpu_zbc_query_table_params {
+        u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
+        u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
+        u32 depth;
+        u32 ref_cnt;
+        u32 format;
+        u32 type;             /* color or depth */
+        u32 index_size;       /* [out] size, [in] index */
+};
+
 struct tegra_vgpu_cmd_msg {
         u32 cmd;
         int ret;
@@ -211,6 +236,8 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_runlist_params runlist;
                 struct tegra_vgpu_golden_ctx_params golden_ctx;
                 struct tegra_vgpu_zcull_info_params zcull_info;
+                struct tegra_vgpu_zbc_set_table_params zbc_set_table;
+                struct tegra_vgpu_zbc_query_table_params zbc_query_table;
         } params;
 };