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authorRichard Zhao <rizhao@nvidia.com>2016-07-26 20:48:58 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-08-15 14:41:25 -0400
commitdeffbf8ee2017d4ea804f35946673dd0f6e0fcf2 (patch)
tree811b5d8a5da49d27a6581301772df54eacc8a55a /include/linux/tegra_vgpu.h
parentead314881633c128905c6aaeb5b6e4bf0cc1bb17 (diff)
gpu: nvgpu: vgpu: get constants of gpc_tpc_count/mask arrays
It'll cover multi-gpcs. JIRA VFND-2103 Change-Id: Ie82bdaad360294696c5a679d694f6f0e2364ca2e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1194631 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h14
1 files changed, 11 insertions, 3 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 4b308316..fdab9b06 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -117,7 +117,7 @@ enum {
117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */ 117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */ 118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */
119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */ 119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */
120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, 120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, /* deprecated */
121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ 121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */ 122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */ 123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */
@@ -125,13 +125,13 @@ enum {
125 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */ 125 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */
126 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */ 126 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */
127 TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */ 127 TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */
128 TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, 128 TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, /* deprecated */
129 TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */ 129 TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
130 TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */ 130 TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
131 TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */ 131 TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
132 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */ 132 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
133 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */ 133 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */
134 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, 134 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */
135 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ 135 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
136}; 136};
137 137
@@ -403,6 +403,9 @@ struct tegra_vgpu_gpu_clk_rate_params {
403 u32 rate; /* in kHz */ 403 u32 rate; /* in kHz */
404}; 404};
405 405
406#define TEGRA_VGPU_MAX_GPC_COUNT 16
407#define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16
408
406struct tegra_vgpu_constants_params { 409struct tegra_vgpu_constants_params {
407 u32 arch; 410 u32 arch;
408 u32 impl; 411 u32 impl;
@@ -427,6 +430,11 @@ struct tegra_vgpu_constants_params {
427 u32 fbp_en_mask; 430 u32 fbp_en_mask;
428 u32 ltc_per_fbp; 431 u32 ltc_per_fbp;
429 u32 max_lts_per_ltc; 432 u32 max_lts_per_ltc;
433 u8 gpc_tpc_count[TEGRA_VGPU_MAX_GPC_COUNT];
434 /* mask bits should be equal or larger than
435 * TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC
436 */
437 u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT];
430}; 438};
431 439
432struct tegra_vgpu_cmd_msg { 440struct tegra_vgpu_cmd_msg {