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author | Sachit Kadle <skadle@nvidia.com> | 2016-11-04 20:48:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-12-19 18:39:47 -0500 |
commit | c1750f45f5239508e7a67db0627552f87943ec9f (patch) | |
tree | 638889829e65bc1f51254791da99610beaa538f1 /include/linux/tegra_vgpu.h | |
parent | 6ea4a81f4da565eb07e4eedbe7f80305b5715cf2 (diff) |
gpu: nvgpu: add tsg_open HAL interface
Add HAL interface for TSG open, which is intended to
be called from the exisiting gk20a_tsg_open function.
The tsg_open entryoint is only implemented for vgpu,
as the server needs to clear metadata when a tsg is opened.
Bug 200215060
Change-Id: Icc8fd602f31e52d9fa9b2e7786b665b9e7b9294e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1249218
(cherry picked from commit 35c86f7c796c6574d3dc336e20012ea5c16d7cb4)
Reviewed-on: http://git-master/r/1256468
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r-- | include/linux/tegra_vgpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 456622a4..79698d23 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -98,6 +98,7 @@ enum { | |||
98 | TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, | 98 | TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, |
99 | TEGRA_VGPU_CMD_GET_CONSTANTS = 62, | 99 | TEGRA_VGPU_CMD_GET_CONSTANTS = 62, |
100 | TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, | 100 | TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, |
101 | TEGRA_VGPU_CMD_TSG_OPEN = 64, | ||
101 | }; | 102 | }; |
102 | 103 | ||
103 | struct tegra_vgpu_connect_params { | 104 | struct tegra_vgpu_connect_params { |
@@ -387,6 +388,10 @@ struct tegra_vgpu_tsg_timeslice_params { | |||
387 | u32 timeslice_us; | 388 | u32 timeslice_us; |
388 | }; | 389 | }; |
389 | 390 | ||
391 | struct tegra_vgpu_tsg_open_params { | ||
392 | u32 tsg_id; | ||
393 | }; | ||
394 | |||
390 | /* level follows nvgpu.h definitions */ | 395 | /* level follows nvgpu.h definitions */ |
391 | struct tegra_vgpu_tsg_runlist_interleave_params { | 396 | struct tegra_vgpu_tsg_runlist_interleave_params { |
392 | u32 tsg_id; | 397 | u32 tsg_id; |
@@ -486,6 +491,7 @@ struct tegra_vgpu_cmd_msg { | |||
486 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; | 491 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; |
487 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | 492 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; |
488 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | 493 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; |
494 | struct tegra_vgpu_tsg_open_params tsg_open; | ||
489 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | 495 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; |
490 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | 496 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; |
491 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; | 497 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; |