diff options
author | Richard Zhao <rizhao@nvidia.com> | 2015-07-23 18:10:42 -0400 |
---|---|---|
committer | Richard Zhao <rizhao@nvidia.com> | 2015-08-19 08:12:00 -0400 |
commit | a88e58cc9d2c4b9f852716240b3cabc9449d8679 (patch) | |
tree | 5965b2645913695ed36e61aa4c42fdb60045cf42 /include/linux/tegra_vgpu.h | |
parent | db8bce518bcf2a1b46e5897f55469f348a16c9a2 (diff) |
gpu: nvgpu: vgpu: add t210 gm20b support
- add hal initializaiton
- create folders vgpu/gk20a and vgpu/gm20b for specific code
Bug 1653185
Change-Id: If94d45e22a1d73d2e4916673736cc29751be4e40
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/774148
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r-- | include/linux/tegra_vgpu.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 7c4aa323..70914fa3 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -89,7 +89,14 @@ enum { | |||
89 | TEGRA_VGPU_ATTRIB_L2_SIZE, | 89 | TEGRA_VGPU_ATTRIB_L2_SIZE, |
90 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, | 90 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, |
91 | TEGRA_VGPU_ATTRIB_NUM_FBPS, | 91 | TEGRA_VGPU_ATTRIB_NUM_FBPS, |
92 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK | 92 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK, |
93 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP, | ||
94 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC, | ||
95 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK, | ||
96 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE, | ||
97 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE, | ||
98 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC, | ||
99 | TEGRA_VGPU_ATTRIB_LTC_COUNT | ||
93 | }; | 100 | }; |
94 | 101 | ||
95 | struct tegra_vgpu_attrib_params { | 102 | struct tegra_vgpu_attrib_params { |
@@ -100,6 +107,7 @@ struct tegra_vgpu_attrib_params { | |||
100 | struct tegra_vgpu_as_share_params { | 107 | struct tegra_vgpu_as_share_params { |
101 | u64 size; | 108 | u64 size; |
102 | u64 handle; | 109 | u64 handle; |
110 | u32 big_page_size; | ||
103 | }; | 111 | }; |
104 | 112 | ||
105 | struct tegra_vgpu_as_bind_share_params { | 113 | struct tegra_vgpu_as_bind_share_params { |