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authorRichard Zhao <rizhao@nvidia.com>2015-12-04 18:25:46 -0500
committerVladislav Buzov <vbuzov@nvidia.com>2016-01-10 23:06:12 -0500
commit942936bae027cb774caaf257c22eb42be32dc2ec (patch)
treef6fecfeb859116765acf0db1aaf1fefba1f567c6 /include/linux/tegra_vgpu.h
parentf1d41774627efe612ee0ef0868d7233c5f2038f3 (diff)
gpu: nvgpu: vgpu: add set sm debug mode support
JIRA VFND-1006 Bug 1594604 Change-Id: If6eb7ae22b5b0557faddd3d68deb791abb24bec4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/923233 (cherry picked from commit 9e14ca393c3044be702c50524a9ef3a2c3a6270c) Reviewed-on: http://git-master/r/841866 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index b7bcc905..dbfa06d5 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -71,7 +71,8 @@ enum {
71 TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, 71 TEGRA_VGPU_CMD_ZBC_QUERY_TABLE,
72 TEGRA_VGPU_CMD_AS_MAP_EX, 72 TEGRA_VGPU_CMD_AS_MAP_EX,
73 TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, 73 TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS,
74 TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE 74 TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
75 TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE
75}; 76};
76 77
77struct tegra_vgpu_connect_params { 78struct tegra_vgpu_connect_params {
@@ -264,6 +265,12 @@ struct tegra_vgpu_mmu_debug_mode {
264 u32 enable; 265 u32 enable;
265}; 266};
266 267
268struct tegra_vgpu_sm_debug_mode {
269 u64 handle;
270 u64 sms;
271 u32 enable;
272};
273
267struct tegra_vgpu_cmd_msg { 274struct tegra_vgpu_cmd_msg {
268 u32 cmd; 275 u32 cmd;
269 int ret; 276 int ret;
@@ -289,6 +296,7 @@ struct tegra_vgpu_cmd_msg {
289 struct tegra_vgpu_zbc_query_table_params zbc_query_table; 296 struct tegra_vgpu_zbc_query_table_params zbc_query_table;
290 struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; 297 struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers;
291 struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; 298 struct tegra_vgpu_mmu_debug_mode mmu_debug_mode;
299 struct tegra_vgpu_sm_debug_mode sm_debug_mode;
292 char padding[192]; 300 char padding[192];
293 } params; 301 } params;
294}; 302};