diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-01-14 20:40:48 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-01-25 18:22:22 -0500 |
commit | 8fb33d92b03b9ee2db421c69252822d09477cce5 (patch) | |
tree | ca3708bc20bb13a743a50a0a5660f42e487dea9f /include/linux/tegra_vgpu.h | |
parent | 42b0f49d42eeadffc221bd4d9990010dfebd4a10 (diff) |
gpu: nvgpu: vgpu: add channel_set_priority support
- add gops.fifo.channel_set_priority and move current code
as native callback.
- implement the callback for vgpu
Bug 1701079
Change-Id: If1cd13ea4478d11d578da2f682598e0c4522bcaf
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/932829
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r-- | include/linux/tegra_vgpu.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index b0e25c60..280ca9c0 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -73,7 +73,8 @@ enum { | |||
73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, | 73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, |
74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, | 74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, |
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, | 75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, |
76 | TEGRA_VGPU_CMD_REG_OPS | 76 | TEGRA_VGPU_CMD_REG_OPS, |
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY | ||
77 | }; | 78 | }; |
78 | 79 | ||
79 | struct tegra_vgpu_connect_params { | 80 | struct tegra_vgpu_connect_params { |
@@ -292,6 +293,11 @@ struct tegra_vgpu_reg_ops_params { | |||
292 | u32 is_profiler; | 293 | u32 is_profiler; |
293 | }; | 294 | }; |
294 | 295 | ||
296 | struct tegra_vgpu_channel_priority_params { | ||
297 | u64 handle; | ||
298 | u32 priority; | ||
299 | }; | ||
300 | |||
295 | struct tegra_vgpu_cmd_msg { | 301 | struct tegra_vgpu_cmd_msg { |
296 | u32 cmd; | 302 | u32 cmd; |
297 | int ret; | 303 | int ret; |
@@ -319,6 +325,7 @@ struct tegra_vgpu_cmd_msg { | |||
319 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; | 325 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; |
320 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | 326 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; |
321 | struct tegra_vgpu_reg_ops_params reg_ops; | 327 | struct tegra_vgpu_reg_ops_params reg_ops; |
328 | struct tegra_vgpu_channel_priority_params channel_priority; | ||
322 | char padding[192]; | 329 | char padding[192]; |
323 | } params; | 330 | } params; |
324 | }; | 331 | }; |