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authorRichard Zhao <rizhao@nvidia.com>2016-07-25 18:12:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-08-15 14:41:23 -0400
commit843bbc726c7283666a18d9ff899350e0cef18330 (patch)
tree5811b36c7aa7ec7e2b24dcae83e08cb513d27e13 /include/linux/tegra_vgpu.h
parent233862859a759b14353d743c0bce7d0df18e49ca (diff)
gpu: nvgpu: vgpu: add getting sm version constants
move below attributes to constants: TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH JIRA VFND-2103 Change-Id: I5d6aa8f4a49e65307989ef02d223c3ee31fcdeed Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190481 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index ef4c36d9..d30ae41d 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -120,7 +120,7 @@ enum {
120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, 120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ 121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */ 122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, 123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */
124 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, 124 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10,
125 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, 125 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11,
126 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, 126 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12,
@@ -417,6 +417,9 @@ struct tegra_vgpu_constants_params {
417 u32 slices_per_ltc; 417 u32 slices_per_ltc;
418 u32 comptags_per_cacheline; 418 u32 comptags_per_cacheline;
419 u32 comptag_lines; 419 u32 comptag_lines;
420 u32 sm_arch_sm_version;
421 u32 sm_arch_spa_version;
422 u32 sm_arch_warp_count;
420}; 423};
421 424
422struct tegra_vgpu_cmd_msg { 425struct tegra_vgpu_cmd_msg {