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authorAingara Paramakuru <aparamakuru@nvidia.com>2016-03-04 10:15:08 -0500
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-03-23 14:04:19 -0400
commit7d45a7361d104674d921dffed0f7051b0aaf1059 (patch)
tree555a79b7896a0bf30d6146f281dadfd6d3c5812e /include/linux/tegra_vgpu.h
parent6e946ad3a3cf1b189d5d7705427de4d607de7f3b (diff)
gpu: nvgpu: vgpu: add channel interleave support
Update vgpu back-end to send channel interleave request to server. JIRA VFND-1313 Bug 1729664 Change-Id: I2433aef485135ae9222dec238e25aedc19257744 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1028976 (cherry picked from commit df3c5dc410839d126cc0574064d23e58102689b8) Reviewed-on: http://git-master/r/1026049 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 280ca9c0..5f697e78 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Tegra GPU Virtualization Interfaces to Server 2 * Tegra GPU Virtualization Interfaces to Server
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -74,7 +74,8 @@ enum {
74 TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, 74 TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
75 TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, 75 TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE,
76 TEGRA_VGPU_CMD_REG_OPS, 76 TEGRA_VGPU_CMD_REG_OPS,
77 TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY 77 TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY,
78 TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE
78}; 79};
79 80
80struct tegra_vgpu_connect_params { 81struct tegra_vgpu_connect_params {
@@ -298,6 +299,12 @@ struct tegra_vgpu_channel_priority_params {
298 u32 priority; 299 u32 priority;
299}; 300};
300 301
302/* level follows nvgpu.h definitions */
303struct tegra_vgpu_channel_runlist_interleave_params {
304 u64 handle;
305 u32 level;
306};
307
301struct tegra_vgpu_cmd_msg { 308struct tegra_vgpu_cmd_msg {
302 u32 cmd; 309 u32 cmd;
303 int ret; 310 int ret;
@@ -326,6 +333,7 @@ struct tegra_vgpu_cmd_msg {
326 struct tegra_vgpu_sm_debug_mode sm_debug_mode; 333 struct tegra_vgpu_sm_debug_mode sm_debug_mode;
327 struct tegra_vgpu_reg_ops_params reg_ops; 334 struct tegra_vgpu_reg_ops_params reg_ops;
328 struct tegra_vgpu_channel_priority_params channel_priority; 335 struct tegra_vgpu_channel_priority_params channel_priority;
336 struct tegra_vgpu_channel_runlist_interleave_params channel_interleave;
329 char padding[192]; 337 char padding[192];
330 } params; 338 } params;
331}; 339};