gpu: nvgpu: hal for timestamps correlation

In order to perform timestamps correlation for FECS
traces, we need to collect GPU / GPU timestamps
samples. In virtualization case, it is possible for
a guest to get GPU timestamps by using read_ptimer.
However, if the CPU timestamp is read on guest side,
and the GPU timestamp is read on vm-server side,
then it introduces some latency that will create an
artificial offset for GPU timestamps (~2 us in
average). For better CPU / GPU timestamps correlation,
Added a command to collect all timestamps on vm-server
side.

Bug 1900475

Change-Id: Idfdc6ae4c16c501dc5e00053a5b75932c55148d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1472447
(cherry picked from commit 56f56b5cd9d2e75cf7d2613b5e115bfebdbee0ce)
Reviewed-on: http://git-master/r/1489183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 18 insertions, 0 deletions

diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index daef7d98..67f51806 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -101,6 +101,7 @@ enum {
         TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67,
         TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68,
         TEGRA_VGPU_CMD_PROF_MGT = 72,
+        TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74,
 };
 
 struct tegra_vgpu_connect_params {
@@ -389,6 +390,22 @@ struct tegra_vgpu_read_ptimer_params {
         u64 time;
 };
 
+#define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT      16
+#define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC     1
+struct tegra_vgpu_get_timestamps_zipper_params {
+        /* timestamp pairs */
+        struct {
+                /* gpu timestamp value */
+                u64 cpu_timestamp;
+                /* raw GPU counter (PTIMER) value */
+                u64 gpu_timestamp;
+        } samples[TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT];
+        /* number of pairs to read */
+        u32 count;
+        /* cpu clock source id */
+        u32 source_id;
+};
+
 struct tegra_vgpu_set_powergate_params {
         u32 mode;
 };
@@ -518,6 +535,7 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_suspend_resume_contexts resume_contexts;
                 struct tegra_vgpu_clear_sm_error_state clear_sm_error_state;
                 struct tegra_vgpu_prof_mgt_params prof_management;
+                struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper;
                 char padding[192];
         } params;
 };