diff options
author | Aingara Paramakuru <aparamakuru@nvidia.com> | 2015-08-27 13:51:32 -0400 |
---|---|---|
committer | Alex Van Brunt <avanbrunt@nvidia.com> | 2015-10-02 21:20:05 -0400 |
commit | 3e08593d4563a3162d47c61fc2c70ab0b42fb93c (patch) | |
tree | 2358d799b1d52b5b7841d7e19ab0ce1e28c64f52 /include/linux/tegra_vgpu.h | |
parent | e233b0fdcdf19ed6356a31fed04654f2ee103d98 (diff) |
gpu: nvgpu: vgpu: add new GMMU map interface
The server now exposes a new GMMU map interface that
can accept a scatter-gather list. This is needed to support
SMMU-bypass configurations.
Bug 1677153
JIRA VFND-689
Change-Id: I7b5af145db57dcebe2c9125ec90c689798d7e69e
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/792558
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r-- | include/linux/tegra_vgpu.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 2b327d09..6fc298e0 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -64,7 +64,8 @@ enum { | |||
64 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST, | 64 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST, |
65 | TEGRA_VGPU_CMD_GET_ZCULL_INFO, | 65 | TEGRA_VGPU_CMD_GET_ZCULL_INFO, |
66 | TEGRA_VGPU_CMD_ZBC_SET_TABLE, | 66 | TEGRA_VGPU_CMD_ZBC_SET_TABLE, |
67 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE | 67 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, |
68 | TEGRA_VGPU_CMD_AS_MAP_EX | ||
68 | }; | 69 | }; |
69 | 70 | ||
70 | struct tegra_vgpu_connect_params { | 71 | struct tegra_vgpu_connect_params { |
@@ -136,6 +137,25 @@ struct tegra_vgpu_as_map_params { | |||
136 | u32 ctag_offset; | 137 | u32 ctag_offset; |
137 | }; | 138 | }; |
138 | 139 | ||
140 | struct tegra_vgpu_as_map_ex_params { | ||
141 | u64 handle; | ||
142 | u64 gpu_va; | ||
143 | u64 size; | ||
144 | u32 mem_desc_count; | ||
145 | u8 pgsz_idx; | ||
146 | u8 iova; | ||
147 | u8 kind; | ||
148 | u8 cacheable; | ||
149 | u8 clear_ctags; | ||
150 | u8 prot; | ||
151 | u32 ctag_offset; | ||
152 | }; | ||
153 | |||
154 | struct tegra_vgpu_mem_desc { | ||
155 | u64 addr; | ||
156 | u64 length; | ||
157 | }; | ||
158 | |||
139 | struct tegra_vgpu_as_invalidate_params { | 159 | struct tegra_vgpu_as_invalidate_params { |
140 | u64 handle; | 160 | u64 handle; |
141 | }; | 161 | }; |
@@ -236,6 +256,7 @@ struct tegra_vgpu_cmd_msg { | |||
236 | struct tegra_vgpu_as_share_params as_share; | 256 | struct tegra_vgpu_as_share_params as_share; |
237 | struct tegra_vgpu_as_bind_share_params as_bind_share; | 257 | struct tegra_vgpu_as_bind_share_params as_bind_share; |
238 | struct tegra_vgpu_as_map_params as_map; | 258 | struct tegra_vgpu_as_map_params as_map; |
259 | struct tegra_vgpu_as_map_ex_params as_map_ex; | ||
239 | struct tegra_vgpu_as_invalidate_params as_invalidate; | 260 | struct tegra_vgpu_as_invalidate_params as_invalidate; |
240 | struct tegra_vgpu_channel_config_params channel_config; | 261 | struct tegra_vgpu_channel_config_params channel_config; |
241 | struct tegra_vgpu_ramfc_params ramfc; | 262 | struct tegra_vgpu_ramfc_params ramfc; |