gpu: nvgpu: vgpu: add regops support

Added new RM Server command for regops.

JIRA VFND-1128
Bug 1700139

Change-Id: Ia1cc63e993c29c91f87440c241077fa91edb9e53
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/923235
(cherry picked from commit 7de22e42cfd2e419ad64178b9f1f1ee16273bd03)
Reviewed-on: http://git-master/r/841330
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

1 files changed, 23 insertions, 1 deletions

diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 4db3a16f..b0e25c60 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -72,7 +72,8 @@ enum {
         TEGRA_VGPU_CMD_AS_MAP_EX,
         TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS,
         TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
-        TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE
+        TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE,
+        TEGRA_VGPU_CMD_REG_OPS
 };
 
 struct tegra_vgpu_connect_params {
@@ -271,6 +272,26 @@ struct tegra_vgpu_sm_debug_mode {
         u32 enable;
 };
 
+struct tegra_vgpu_reg_op {
+        u8 op;
+        u8 type;
+        u8 status;
+        u8 quad;
+        u32 group_mask;
+        u32 sub_group_mask;
+        u32 offset;
+        u32 value_lo;
+        u32 value_hi;
+        u32 and_n_mask_lo;
+        u32 and_n_mask_hi;
+};
+
+struct tegra_vgpu_reg_ops_params {
+        u64 handle;
+        u64 num_ops;
+        u32 is_profiler;
+};
+
 struct tegra_vgpu_cmd_msg {
         u32 cmd;
         int ret;
@@ -297,6 +318,7 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers;
                 struct tegra_vgpu_mmu_debug_mode mmu_debug_mode;
                 struct tegra_vgpu_sm_debug_mode sm_debug_mode;
+                struct tegra_vgpu_reg_ops_params reg_ops;
                 char padding[192];
         } params;
 };