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authorRichard Zhao <rizhao@nvidia.com>2016-07-25 14:19:21 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-08-15 14:41:21 -0400
commit233862859a759b14353d743c0bce7d0df18e49ca (patch)
tree11bf4894ec20d9fc67e3842269b48e748261a8ef /include/linux/tegra_vgpu.h
parent47fe8460e96413c10ec84261895418d6b59bc690 (diff)
gpu: nvgpu: vgpu: add getting ltc constants
move below attributes to constants: TEGRA_VGPU_ATTRIB_COMPTAG_LINES TEGRA_VGPU_ATTRIB_L2_SIZE TEGRA_VGPU_ATTRIB_CACHELINE_SIZE TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE TEGRA_VGPU_ATTRIB_SLICES_PER_LTC TEGRA_VGPU_ATTRIB_LTC_COUNT JIRA VFND-2103 Change-Id: Iecf9717ee553a16ffe8de445be5bfe5a99c3a094 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190480 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h18
1 files changed, 12 insertions, 6 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 504a31ad..ef4c36d9 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -114,22 +114,22 @@ enum {
114 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */ 114 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
115 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */ 115 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */
116 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */ 116 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */
117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, 117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, 118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4,
119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, 119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5,
120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, 120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ 121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, 122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, 123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9,
124 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, 124 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10,
125 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, 125 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11,
126 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, 126 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12,
127 TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, 127 TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13,
128 TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, 128 TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14,
129 TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, 129 TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
130 TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, 130 TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
131 TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, 131 TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
132 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, 132 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
133 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, 133 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19,
134 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, 134 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
135 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ 135 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
@@ -411,6 +411,12 @@ struct tegra_vgpu_constants_params {
411 u32 num_channels; 411 u32 num_channels;
412 u32 golden_ctx_size; 412 u32 golden_ctx_size;
413 u32 zcull_ctx_size; 413 u32 zcull_ctx_size;
414 u32 l2_size;
415 u32 ltc_count;
416 u32 cacheline_size;
417 u32 slices_per_ltc;
418 u32 comptags_per_cacheline;
419 u32 comptag_lines;
414}; 420};
415 421
416struct tegra_vgpu_cmd_msg { 422struct tegra_vgpu_cmd_msg {