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authorRichard Zhao <rizhao@nvidia.com>2016-06-08 17:57:41 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-06-16 17:06:55 -0400
commit22d0233d3a2c7e2805f0251e43e776fa07469c8b (patch)
treed7651d6942af2795bf82459397307fbf0de9efe2 /include/linux/tegra_vgpu.h
parent86225cb04eb040a83400d5ad6619b3c2318a53f8 (diff)
gpu: nvgpu: vgpu: add read ptimer support
Bug 1395833 Change-Id: Id0d427b6a1ddaecfeec33c61a6161679cf596c92 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159588 (cherry picked from commit d33aa89420990626fb377c56ed5517a00f717c2a) Reviewed-on: http://git-master/r/1158897 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 9a31ff40..fc701eb3 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -95,6 +95,7 @@ enum {
95 TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE, 95 TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE,
96 TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET, 96 TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET,
97 TEGRA_VGPU_CMD_CHANNEL_ENABLE, 97 TEGRA_VGPU_CMD_CHANNEL_ENABLE,
98 TEGRA_VGPU_CMD_READ_PTIMER,
98}; 99};
99 100
100struct tegra_vgpu_connect_params { 101struct tegra_vgpu_connect_params {
@@ -389,6 +390,10 @@ struct tegra_vgpu_tsg_runlist_interleave_params {
389 u32 level; 390 u32 level;
390}; 391};
391 392
393struct tegra_vgpu_read_ptimer_params {
394 u64 time;
395};
396
392struct tegra_vgpu_cmd_msg { 397struct tegra_vgpu_cmd_msg {
393 u32 cmd; 398 u32 cmd;
394 int ret; 399 int ret;
@@ -429,6 +434,7 @@ struct tegra_vgpu_cmd_msg {
429 struct tegra_vgpu_tsg_preempt_params tsg_preempt; 434 struct tegra_vgpu_tsg_preempt_params tsg_preempt;
430 struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; 435 struct tegra_vgpu_tsg_timeslice_params tsg_timeslice;
431 struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; 436 struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave;
437 struct tegra_vgpu_read_ptimer_params read_ptimer;
432 char padding[192]; 438 char padding[192];
433 } params; 439 } params;
434}; 440};