gpu: nvgpu: Add MC HAL is_intr1_pending

Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit
that is passed as parameter to is_intr1_pending. The API is passed
contents of intr1 register and an engine number, and returns true
if there's an interrupt pending for the engine.

JIRA NVGPU-26

Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497870
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 86 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 2ede539e..bd93cc33 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -142,6 +142,8 @@ enum gk20a_cbc_op {
 
 #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
 
+enum nvgpu_unit;
+
 struct gpu_ops {
         struct {
                 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
@@ -851,6 +853,7 @@ struct gpu_ops {
                 void (*disable)(struct gk20a *g, u32 units);
                 void (*reset)(struct gk20a *g, u32 units);
                 u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
+                bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
         } mc;
         struct {
                 void (*show_dump)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index bc11b14d..2cdcaaeb 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -20,6 +20,7 @@
 
 #include <nvgpu/timers.h>
 #include <nvgpu/atomic.h>
+#include <nvgpu/unit.h>
 
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
@@ -134,7 +135,7 @@ void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 mc_intr_1)
         u32 engine_enum = ENGINE_INVAL_GK20A;
         int ops_old, ops_new, ops = 0;
 
-        if (mc_intr_1 & mc_intr_0_pfifo_pending_f())
+        if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1))
                 ops |= gk20a_fifo_nonstall_isr(g);
 
         for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
@@ -287,6 +288,30 @@ u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
         return val;
 }
 
+bool mc_gk20a_is_intr1_pending(struct gk20a *g,
+                               enum nvgpu_unit unit, u32 mc_intr_1)
+{
+        u32 mask = 0;
+        bool is_pending;
+
+        switch (unit) {
+        case NVGPU_UNIT_FIFO:
+                mask = mc_intr_0_pfifo_pending_f();
+                break;
+        default:
+                break;
+        }
+
+        if (mask == 0) {
+                nvgpu_err(g, "unknown unit %d", unit);
+                is_pending = false;
+        } else {
+                is_pending = (mc_intr_1 & mask) ? true : false;
+        }
+
+        return is_pending;
+}
+
 void gk20a_init_mc(struct gpu_ops *gops)
 {
         gops->mc.intr_enable = mc_gk20a_intr_enable;
@@ -302,4 +327,5 @@ void gk20a_init_mc(struct gpu_ops *gops)
         gops->mc.disable = gk20a_mc_disable;
         gops->mc.reset = gk20a_mc_reset;
         gops->mc.boot_0 = gk20a_mc_boot_0;
+        gops->mc.is_intr1_pending = mc_gk20a_is_intr1_pending;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
index 2b4a183e..6c0d159a 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
@@ -31,4 +31,6 @@ void gk20a_mc_enable(struct gk20a *g, u32 units);
 void gk20a_mc_disable(struct gk20a *g, u32 units);
 void gk20a_mc_reset(struct gk20a *g, u32 units);
 u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
+bool mc_gk20a_is_intr1_pending(struct gk20a *g,
+                enum nvgpu_unit unit, u32 mc_intr_1);
 #endif
diff --git a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
index ebb9780d..7330a027 100644
--- a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
@@ -32,4 +32,5 @@ void gm20b_init_mc(struct gpu_ops *gops)
         gops->mc.disable = gk20a_mc_disable;
         gops->mc.reset = gk20a_mc_reset;
         gops->mc.boot_0 = gk20a_mc_boot_0;
+        gops->mc.is_intr1_pending = mc_gk20a_is_intr1_pending;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index bfc7a3d4..7ccea370 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -19,6 +19,7 @@
 #include "mc_gp10b.h"
 
 #include <nvgpu/atomic.h>
+#include <nvgpu/unit.h>
 
 #include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
 
@@ -169,6 +170,30 @@ void mc_gp10b_intr_stall_resume(struct gk20a *g)
                         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
 }
 
+static bool mc_gp10b_is_intr1_pending(struct gk20a *g,
+                                      enum nvgpu_unit unit, u32 mc_intr_1)
+{
+        u32 mask = 0;
+        bool is_pending;
+
+        switch (unit) {
+        case NVGPU_UNIT_FIFO:
+                mask = mc_intr_pfifo_pending_f();
+                break;
+        default:
+                break;
+        }
+
+        if (mask == 0) {
+                nvgpu_err(g, "unknown unit %d", unit);
+                is_pending = false;
+        } else {
+                is_pending = (mc_intr_1 & mask) ? true : false;
+        }
+
+        return is_pending;
+}
+
 void gp10b_init_mc(struct gpu_ops *gops)
 {
         gops->mc.intr_enable = mc_gp10b_intr_enable;
@@ -184,4 +209,5 @@ void gp10b_init_mc(struct gpu_ops *gops)
         gops->mc.disable = gk20a_mc_disable;
         gops->mc.reset = gk20a_mc_reset;
         gops->mc.boot_0 = gk20a_mc_boot_0;
+        gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending;
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/unit.h b/drivers/gpu/nvgpu/include/nvgpu/unit.h
new file mode 100644
index 00000000..e209eb59
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/unit.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __NVGPU_UNITS_H__
+#define __NVGPU_UNITS_H__
+
+/*
+ * Enumeration of all units intended to be used by any HAL that requires
+ * unit as parameter.
+ *
+ * Units are added to the enumeration as needed, so it is not complete.
+ */
+enum nvgpu_unit {
+        NVGPU_UNIT_FIFO,
+};
+
+#endif