diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-06-28 07:23:41 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-04 02:44:30 -0400 |
commit | fbeca4a8414c03a1564d7a370964187be51a3e6c (patch) | |
tree | 4ba412c53e52678b9e115fd1ec80655bd2380f46 /drivers | |
parent | 2f712e22303471b8dd2f9388c874d12b07aed258 (diff) |
gpu: nvgpu: Falcon controller wait for halt
- Added nvgpu_flcn_wait_for_halt() interface to wait for
falcon halt, which block till falcon halt or timeout
expire for selected falcon controller
- Replaced falcon wait for halt code with method
nvgpu_flcn_wait_for_halt()
NVGPU JIRA-99
Change-Id: Ie1809dc29ff65bddc7ef2859a9ee9b4f0003b127
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1510201
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/bios_gm206.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 1 |
5 files changed, 27 insertions, 39 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index b6589bd1..ba2fb3fe 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -102,6 +102,26 @@ bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn) | |||
102 | return status; | 102 | return status; |
103 | } | 103 | } |
104 | 104 | ||
105 | int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout) | ||
106 | { | ||
107 | struct gk20a *g = flcn->g; | ||
108 | struct nvgpu_timeout to; | ||
109 | int status = 0; | ||
110 | |||
111 | nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); | ||
112 | do { | ||
113 | if (nvgpu_flcn_get_cpu_halted_status(flcn)) | ||
114 | break; | ||
115 | |||
116 | nvgpu_udelay(10); | ||
117 | } while (!nvgpu_timeout_expired(&to)); | ||
118 | |||
119 | if (nvgpu_timeout_peek_expired(&to)) | ||
120 | status = -EBUSY; | ||
121 | |||
122 | return status; | ||
123 | } | ||
124 | |||
105 | bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn) | 125 | bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn) |
106 | { | 126 | { |
107 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | 127 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; |
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index 216fd594..7aec21e7 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c | |||
@@ -166,8 +166,6 @@ out: | |||
166 | static int gm206_bios_preos(struct gk20a *g) | 166 | static int gm206_bios_preos(struct gk20a *g) |
167 | { | 167 | { |
168 | int err = 0; | 168 | int err = 0; |
169 | int val; | ||
170 | struct nvgpu_timeout timeout; | ||
171 | 169 | ||
172 | gk20a_dbg_fn(""); | 170 | gk20a_dbg_fn(""); |
173 | 171 | ||
@@ -196,17 +194,8 @@ static int gm206_bios_preos(struct gk20a *g) | |||
196 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | 194 | gk20a_writel(g, pwr_falcon_cpuctl_r(), |
197 | pwr_falcon_cpuctl_startcpu_f(1)); | 195 | pwr_falcon_cpuctl_startcpu_f(1)); |
198 | 196 | ||
199 | nvgpu_timeout_init(g, &timeout, | 197 | if (nvgpu_flcn_wait_for_halt(g->pmu.flcn, |
200 | PMU_BOOT_TIMEOUT_MAX / | 198 | PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT)) { |
201 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
202 | NVGPU_TIMER_CPU_TIMER); | ||
203 | do { | ||
204 | val = pwr_falcon_cpuctl_halt_intr_v( | ||
205 | gk20a_readl(g, pwr_falcon_cpuctl_r())); | ||
206 | nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); | ||
207 | } while (!val && !nvgpu_timeout_expired(&timeout)); | ||
208 | |||
209 | if (nvgpu_timeout_peek_expired(&timeout)) { | ||
210 | err = -ETIMEDOUT; | 199 | err = -ETIMEDOUT; |
211 | goto out; | 200 | goto out; |
212 | } | 201 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 08a58abb..e440e179 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1488,22 +1488,11 @@ err_done: | |||
1488 | */ | 1488 | */ |
1489 | static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms) | 1489 | static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms) |
1490 | { | 1490 | { |
1491 | struct nvgpu_pmu *pmu = &g->pmu; | ||
1491 | u32 data = 0; | 1492 | u32 data = 0; |
1492 | int ret = -EBUSY; | 1493 | int ret = -EBUSY; |
1493 | struct nvgpu_timeout timeout; | ||
1494 | |||
1495 | nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); | ||
1496 | |||
1497 | do { | ||
1498 | data = gk20a_readl(g, pwr_falcon_cpuctl_r()); | ||
1499 | if (data & pwr_falcon_cpuctl_halt_intr_m()) { | ||
1500 | /* CPU is halted break */ | ||
1501 | ret = 0; | ||
1502 | break; | ||
1503 | } | ||
1504 | nvgpu_udelay(1); | ||
1505 | } while (!nvgpu_timeout_expired(&timeout)); | ||
1506 | 1494 | ||
1495 | ret = nvgpu_flcn_wait_for_halt(pmu->flcn, timeout_ms); | ||
1507 | if (ret) { | 1496 | if (ret) { |
1508 | nvgpu_err(g, "ACR boot timed out"); | 1497 | nvgpu_err(g, "ACR boot timed out"); |
1509 | return ret; | 1498 | return ret; |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 06f62a99..20171309 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -57,20 +57,9 @@ int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) | |||
57 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | 57 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) |
58 | { | 58 | { |
59 | u32 data = 0; | 59 | u32 data = 0; |
60 | int completion = -EBUSY; | 60 | int completion = 0; |
61 | struct nvgpu_timeout to; | ||
62 | |||
63 | nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); | ||
64 | do { | ||
65 | data = gk20a_readl(g, psec_falcon_cpuctl_r()); | ||
66 | if (data & psec_falcon_cpuctl_halt_intr_m()) { | ||
67 | /*CPU is halted break*/ | ||
68 | completion = 0; | ||
69 | break; | ||
70 | } | ||
71 | nvgpu_udelay(1); | ||
72 | } while (!nvgpu_timeout_expired(&to)); | ||
73 | 61 | ||
62 | completion = nvgpu_flcn_wait_for_halt(&g->sec2_flcn, timeout); | ||
74 | if (completion) { | 63 | if (completion) { |
75 | nvgpu_err(g, "ACR boot timed out"); | 64 | nvgpu_err(g, "ACR boot timed out"); |
76 | return completion; | 65 | return completion; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index a1a57cd1..3079c79e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -166,6 +166,7 @@ struct nvgpu_falcon { | |||
166 | }; | 166 | }; |
167 | 167 | ||
168 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); | 168 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); |
169 | int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout); | ||
169 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); | 170 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); |
170 | void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, | 171 | void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, |
171 | u32 intr_mask, u32 intr_dest); | 172 | u32 intr_mask, u32 intr_dest); |