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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-03-23 11:43:53 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-23 17:15:25 -0400
commitfb64e1f1b9c2162f521dfe3956655accb911d6a7 (patch)
tree15236c00323c8d24102f5a1221f1b313d62bfac2 /drivers
parentc25e1da93e09a421b8c2b91df720d4bc603db378 (diff)
gpu: nvgpu: Add support for gm204 and gm206
Add support for chips gm204 and gm206. Adds also support for reading VBIOS and booting devinit and pre-os images on PMU. Change-Id: I4824b44245611e5379ace62793cc37158048f432 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120467 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/Makefile7
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h43
-rw-r--r--drivers/gpu/nvgpu/gk20a/hal.c11
-rw-r--r--drivers/gpu/nvgpu/gm206/bios_gm206.c718
-rw-r--r--drivers/gpu/nvgpu/gm206/bios_gm206.h19
-rw-r--r--drivers/gpu/nvgpu/gm206/fifo_gm206.c31
-rw-r--r--drivers/gpu/nvgpu/gm206/fifo_gm206.h18
-rw-r--r--drivers/gpu/nvgpu/gm206/gr_gm206.c92
-rw-r--r--drivers/gpu/nvgpu/gm206/gr_gm206.h23
-rw-r--r--drivers/gpu/nvgpu/gm206/hal_gm206.c206
-rw-r--r--drivers/gpu/nvgpu/gm206/hal_gm206.h19
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_bus_gm206.h193
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_ccsr_gm206.h125
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_ce2_gm206.h81
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_ctxsw_prog_gm206.h253
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_fb_gm206.h337
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h553
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_flush_gm206.h181
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_fuse_gm206.h129
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_gmmu_gm206.h1189
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_gr_gm206.h3681
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_ltc_gm206.h497
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_mc_gm206.h281
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_pbdma_gm206.h505
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_perf_gm206.h205
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_pri_ringmaster_gm206.h145
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_pri_ringstation_sys_gm206.h69
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_proj_gm206.h149
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_pwr_gm206.h825
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_ram_gm206.h445
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_timer_gm206.h109
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_top_gm206.h169
-rw-r--r--drivers/gpu/nvgpu/gm206/hw_xve_gm206.h69
34 files changed, 11381 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 57e32006..e140589a 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -73,7 +73,12 @@ nvgpu-y := \
73 gm20b/mc_gm20b.o \ 73 gm20b/mc_gm20b.o \
74 gm20b/debug_gm20b.o \ 74 gm20b/debug_gm20b.o \
75 gm20b/cde_gm20b.o \ 75 gm20b/cde_gm20b.o \
76 gm20b/therm_gm20b.o 76 gm20b/therm_gm20b.o \
77 gm206/bios_gm206.o \
78 gm206/fifo_gm206.o \
79 gm206/hal_gm206.o \
80 gm206/gr_gm206.o
81
77nvgpu-$(CONFIG_TEGRA_GK20A) += gk20a/platform_gk20a_tegra.o 82nvgpu-$(CONFIG_TEGRA_GK20A) += gk20a/platform_gk20a_tegra.o
78nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o 83nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o
79nvgpu-$(CONFIG_GK20A_PCI) += pci.o 84nvgpu-$(CONFIG_GK20A_PCI) += pci.o
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 3ae30e88..3ab26fb9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -792,6 +792,11 @@ int gk20a_pm_finalize_poweron(struct device *dev)
792 if (err) 792 if (err)
793 goto done; 793 goto done;
794 794
795 if (g->ops.bios.init)
796 err = g->ops.bios.init(g);
797 if (err)
798 goto done;
799
795 if (!tegra_platform_is_silicon()) 800 if (!tegra_platform_is_silicon())
796 gk20a_writel(g, bus_intr_en_0_r(), 0x0); 801 gk20a_writel(g, bus_intr_en_0_r(), 0x0);
797 else 802 else
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 49da164c..f5b4bb3f 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -592,6 +592,40 @@ struct gpu_ops {
592 592
593 int (*get_litter_value)(struct gk20a *g, enum nvgpu_litter_value value); 593 int (*get_litter_value)(struct gk20a *g, enum nvgpu_litter_value value);
594 int (*chip_init_gpu_characteristics)(struct gk20a *g); 594 int (*chip_init_gpu_characteristics)(struct gk20a *g);
595
596 struct {
597 int (*init)(struct gk20a *g);
598 } bios;
599};
600
601struct nvgpu_bios_ucode {
602 u8 *bootloader;
603 u32 bootloader_phys_base;
604 u32 bootloader_size;
605 u8 *ucode;
606 u32 phys_base;
607 u32 size;
608 u8 *dmem;
609 u32 dmem_phys_base;
610 u32 dmem_size;
611 u32 code_entry_point;
612};
613
614struct nvgpu_bios {
615 u8 *data;
616
617 struct nvgpu_bios_ucode devinit;
618 struct nvgpu_bios_ucode preos;
619
620 u8 *devinit_tables;
621 u32 devinit_tables_size;
622 u8 *bootscripts;
623 u32 bootscripts_size;
624
625 u32 devinit_tables_phys_base;
626 u32 devinit_script_phys_base;
627
628 u32 expansion_rom_offset;
595}; 629};
596 630
597struct gk20a { 631struct gk20a {
@@ -763,6 +797,9 @@ struct gk20a {
763 bool mmu_debug_ctrl; 797 bool mmu_debug_ctrl;
764 798
765 u32 tpc_fs_mask_user; 799 u32 tpc_fs_mask_user;
800
801 struct nvgpu_bios bios;
802 struct debugfs_blob_wrapper bios_blob;
766}; 803};
767 804
768static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) 805static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
@@ -1020,6 +1057,12 @@ gk20a_request_firmware(struct gk20a *g, const char *fw_name);
1020#define GK20A_GPUID_GM20B \ 1057#define GK20A_GPUID_GM20B \
1021 GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B) 1058 GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B)
1022 1059
1060#define GK20A_GPUID_GM204 \
1061 GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM204)
1062
1063#define GK20A_GPUID_GM206 \
1064 GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM206)
1065
1023int gk20a_init_gpu_characteristics(struct gk20a *g); 1066int gk20a_init_gpu_characteristics(struct gk20a *g);
1024 1067
1025void gk20a_pbus_isr(struct gk20a *g); 1068void gk20a_pbus_isr(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c
index 16ba4a03..52ec108b 100644
--- a/drivers/gpu/nvgpu/gk20a/hal.c
+++ b/drivers/gpu/nvgpu/gk20a/hal.c
@@ -16,6 +16,7 @@
16#include "gk20a.h" 16#include "gk20a.h"
17#include "hal_gk20a.h" 17#include "hal_gk20a.h"
18#include "gm20b/hal_gm20b.h" 18#include "gm20b/hal_gm20b.h"
19#include "gm206/hal_gm206.h"
19 20
20#ifdef CONFIG_ARCH_TEGRA_18x_SOC 21#ifdef CONFIG_ARCH_TEGRA_18x_SOC
21#include "nvgpu_gpuid_t18x.h" 22#include "nvgpu_gpuid_t18x.h"
@@ -38,11 +39,21 @@ int gpu_init_hal(struct gk20a *g)
38 if (gm20b_init_hal(g)) 39 if (gm20b_init_hal(g))
39 return -ENODEV; 40 return -ENODEV;
40 break; 41 break;
42 case GK20A_GPUID_GM204:
43 case GK20A_GPUID_GM206:
44 gk20a_dbg_info("gm20x detected");
45 if (gm206_init_hal(g))
46 return -ENODEV;
47 break;
41#if defined(CONFIG_ARCH_TEGRA_18x_SOC) 48#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
42 case TEGRA_18x_GPUID: 49 case TEGRA_18x_GPUID:
43 if (TEGRA_18x_GPUID_HAL(g)) 50 if (TEGRA_18x_GPUID_HAL(g))
44 return -ENODEV; 51 return -ENODEV;
45 break; 52 break;
53 case TEGRA_18x_GPUID2:
54 if (TEGRA_18x_GPUID2_HAL(g))
55 return -ENODEV;
56 break;
46#endif 57#endif
47#if defined(CONFIG_ARCH_TEGRA_19x_SOC) 58#if defined(CONFIG_ARCH_TEGRA_19x_SOC)
48 case TEGRA_19x_GPUID: 59 case TEGRA_19x_GPUID:
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c
new file mode 100644
index 00000000..005507bc
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c
@@ -0,0 +1,718 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/types.h>
16
17#include "gk20a/gk20a.h"
18#include "gm20b/fifo_gm20b.h"
19#include "fifo_gm206.h"
20#include "hw_pwr_gm206.h"
21#include "hw_mc_gm206.h"
22#include "hw_xve_gm206.h"
23#include "hw_top_gm206.h"
24
25#define BIT_HEADER_ID 0xb8ff
26#define BIT_HEADER_SIGNATURE 0x00544942
27#define BIOS_SIZE 0x40000
28#define NV_PCFG 0x88000
29#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */
30#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */
31
32static u16 gm206_bios_rdu16(struct gk20a *g, int offset)
33{
34 u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset];
35 return val;
36}
37
38static u32 gm206_bios_rdu32(struct gk20a *g, int offset)
39{
40 u32 val = (g->bios.data[offset+3] << 24) +
41 (g->bios.data[offset+2] << 16) +
42 (g->bios.data[offset+1] << 8) +
43 g->bios.data[offset];
44 return val;
45}
46
47struct bit {
48 u16 id;
49 u32 signature;
50 u16 bcd_version;
51 u8 header_size;
52 u8 token_size;
53 u8 token_entries;
54 u8 header_checksum;
55} __packed;
56
57struct bit_token {
58 u8 token_id;
59 u8 data_version;
60 u16 data_size;
61 u16 data_ptr;
62} __packed;
63
64#define TOKEN_ID_NVINIT_PTRS 0x49
65#define TOKEN_ID_FALCON_DATA 0x70
66
67struct nvinit_ptrs {
68 u16 initscript_table_ptr;
69 u16 macro_index_table_ptr;
70 u16 macro_table_ptr;
71 u16 condition_table_ptr;
72 u16 io_condition_table_ptr;
73 u16 io_flag_condition_table_ptr;
74 u16 init_function_table_ptr;
75 u16 vbios_private_table_ptr;
76 u16 data_arrays_table_ptr;
77 u16 pcie_settings_script_ptr;
78 u16 devinit_tables_ptr;
79 u16 devinit_tables_size;
80 u16 bootscripts_ptr;
81 u16 bootscripts_size;
82 u16 nvlink_config_data_ptr;
83} __packed;
84
85struct falcon_data_v2 {
86 u32 falcon_ucode_table_ptr;
87} __packed;
88
89struct falcon_ucode_table_hdr_v1 {
90 u8 version;
91 u8 header_size;
92 u8 entry_size;
93 u8 entry_count;
94 u8 desc_version;
95 u8 desc_size;
96} __packed;
97
98struct falcon_ucode_table_entry_v1 {
99 u8 application_id;
100 u8 target_id;
101 u32 desc_ptr;
102} __packed;
103
104#define TARGET_ID_PMU 0x01
105#define APPLICATION_ID_DEVINIT 0x04
106#define APPLICATION_ID_PRE_OS 0x01
107
108struct falcon_ucode_desc_v1 {
109 union {
110 u32 v_desc;
111 u32 stored_size;
112 } hdr_size;
113 u32 uncompressed_size;
114 u32 virtual_entry;
115 u32 interface_offset;
116 u32 imem_phys_base;
117 u32 imem_load_size;
118 u32 imem_virt_base;
119 u32 imem_sec_base;
120 u32 imem_sec_size;
121 u32 dmem_offset;
122 u32 dmem_phys_base;
123 u32 dmem_load_size;
124} __packed;
125
126struct application_interface_table_hdr_v1 {
127 u8 version;
128 u8 header_size;
129 u8 entry_size;
130 u8 entry_count;
131} __packed;
132
133struct application_interface_entry_v1 {
134 u32 id;
135 u32 dmem_offset;
136} __packed;
137
138#define APPINFO_ID_DEVINIT 0x01
139
140struct devinit_engine_interface {
141 u32 field0;
142 u32 field1;
143 u32 tables_phys_base;
144 u32 tables_virt_base;
145 u32 script_phys_base;
146 u32 script_virt_base;
147 u32 script_virt_entry;
148 u16 script_size;
149 u8 memory_strap_count;
150 u8 reserved;
151 u32 memory_information_table_virt_base;
152 u32 empty_script_virt_base;
153 u32 cond_table_virt_base;
154 u32 io_cond_table_virt_base;
155 u32 data_arrays_table_virt_base;
156 u32 gpio_assignment_table_virt_base;
157} __packed;
158
159struct pci_exp_rom {
160 u16 sig;
161 u8 reserved[0x16];
162 u16 pci_data_struct_ptr;
163 u32 size_of_block;
164} __packed;
165
166struct pci_data_struct {
167 u32 sig;
168 u16 vendor_id;
169 u16 device_id;
170 u16 device_list_ptr;
171 u16 pci_data_struct_len;
172 u8 pci_data_struct_rev;
173 u8 class_code[3];
174 u16 image_len;
175 u16 vendor_rom_rev;
176 u8 code_type;
177 u8 last_image;
178 u16 max_runtime_image_len;
179} __packed;
180
181struct pci_ext_data_struct {
182 u32 sig;
183 u16 nv_pci_data_ext_rev;
184 u16 nv_pci_data_ext_len;
185 u16 sub_image_len;
186 u8 priv_last_image;
187 u8 flags;
188} __packed;
189
190static void gm206_bios_parse_rom(struct gk20a *g)
191{
192 int offset = 0;
193 int last = 0;
194
195 while (!last) {
196 struct pci_exp_rom *pci_rom;
197 struct pci_data_struct *pci_data;
198 struct pci_ext_data_struct *pci_ext_data;
199
200 pci_rom = (struct pci_exp_rom *)&g->bios.data[offset];
201 gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x",
202 pci_rom->sig, pci_rom->pci_data_struct_ptr,
203 pci_rom->size_of_block);
204
205 pci_data =
206 (struct pci_data_struct *)
207 &g->bios.data[offset + pci_rom->pci_data_struct_ptr];
208 gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x",
209 pci_data->sig, pci_data->pci_data_struct_len,
210 pci_data->image_len, pci_data->code_type,
211 pci_data->last_image,
212 pci_data->max_runtime_image_len);
213
214 if (pci_data->code_type == 0x3) {
215 pci_ext_data = (struct pci_ext_data_struct *)
216 &g->bios.data[(offset +
217 pci_rom->pci_data_struct_ptr +
218 pci_data->pci_data_struct_len +
219 0xf)
220 & ~0xf];
221 gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
222 pci_ext_data->sig,
223 pci_ext_data->nv_pci_data_ext_rev,
224 pci_ext_data->nv_pci_data_ext_len,
225 pci_ext_data->sub_image_len,
226 pci_ext_data->priv_last_image,
227 pci_ext_data->flags);
228
229 gk20a_dbg_fn("expansion rom offset %x",
230 pci_data->image_len * 512);
231 g->bios.expansion_rom_offset =
232 pci_data->image_len * 512;
233 offset += pci_ext_data->sub_image_len * 512;
234 last = pci_ext_data->priv_last_image;
235 } else {
236 offset += pci_data->image_len * 512;
237 last = pci_data->last_image;
238 }
239 }
240}
241
242static void gm206_bios_parse_nvinit_ptrs(struct gk20a *g, int offset)
243{
244 struct nvinit_ptrs nvinit_ptrs;
245
246 memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs));
247 gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr,
248 nvinit_ptrs.devinit_tables_size);
249 gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr,
250 nvinit_ptrs.bootscripts_size);
251
252 g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr];
253 g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size;
254 g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr];
255 g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size;
256}
257
258static void gm206_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
259{
260 struct devinit_engine_interface interface;
261
262 memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface));
263 gk20a_dbg_fn("devinit tables phys %x script phys %x size %d",
264 interface.tables_phys_base,
265 interface.script_phys_base,
266 interface.script_size);
267
268 g->bios.devinit_tables_phys_base = interface.tables_phys_base;
269 g->bios.devinit_script_phys_base = interface.script_phys_base;
270}
271
272static int gm206_bios_parse_appinfo_table(struct gk20a *g, int offset)
273{
274 struct application_interface_table_hdr_v1 hdr;
275 int i;
276
277 memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
278
279 gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d",
280 hdr.version, hdr.header_size,
281 hdr.entry_size, hdr.entry_count);
282
283 if (hdr.version != 1)
284 return 0;
285
286 offset += sizeof(hdr);
287 for (i = 0; i < hdr.entry_count; i++) {
288 struct application_interface_entry_v1 entry;
289
290 memcpy(&entry, &g->bios.data[offset], sizeof(entry));
291
292 gk20a_dbg_fn("appInfo id %d dmem_offset %d",
293 entry.id, entry.dmem_offset);
294
295 if (entry.id == APPINFO_ID_DEVINIT)
296 gm206_bios_parse_devinit_appinfo(g, entry.dmem_offset);
297
298 offset += hdr.entry_size;
299 }
300
301 return 0;
302}
303
304static int gm206_bios_parse_falcon_ucode_desc(struct gk20a *g,
305 struct nvgpu_bios_ucode *ucode, int offset)
306{
307 struct falcon_ucode_desc_v1 desc;
308
309 memcpy(&desc, &g->bios.data[offset], sizeof(desc));
310 gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d",
311 desc.hdr_size.stored_size, desc.uncompressed_size);
312 gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x",
313 desc.virtual_entry, desc.interface_offset);
314 gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x",
315 desc.imem_phys_base, desc.imem_load_size,
316 desc.imem_virt_base, desc.imem_sec_base,
317 desc.imem_sec_size);
318 gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d",
319 desc.dmem_offset, desc.dmem_phys_base,
320 desc.dmem_load_size);
321
322 if (desc.hdr_size.stored_size != desc.uncompressed_size) {
323 gk20a_dbg_info("does not match");
324 return -EINVAL;
325 }
326
327 ucode->code_entry_point = desc.virtual_entry;
328 ucode->bootloader = &g->bios.data[offset] + sizeof(desc);
329 ucode->bootloader_phys_base = desc.imem_phys_base;
330 ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
331 ucode->ucode = ucode->bootloader + ucode->bootloader_size;
332 ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size;
333 ucode->size = desc.imem_sec_size;
334 ucode->dmem = ucode->bootloader + desc.dmem_offset;
335 ucode->dmem_phys_base = desc.dmem_phys_base;
336 ucode->dmem_size = desc.dmem_load_size;
337
338 return gm206_bios_parse_appinfo_table(g,
339 offset + sizeof(desc) +
340 desc.dmem_offset + desc.interface_offset);
341}
342
343static int gm206_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
344{
345 struct falcon_ucode_table_hdr_v1 hdr;
346 int i;
347
348 memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
349 gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
350 hdr.version, hdr.header_size,
351 hdr.entry_size, hdr.entry_count,
352 hdr.desc_version, hdr.desc_size);
353
354 if (hdr.version != 1)
355 return -EINVAL;
356
357 offset += hdr.header_size;
358
359 for (i = 0; i < hdr.entry_count; i++) {
360 struct falcon_ucode_table_entry_v1 entry;
361
362 memcpy(&entry, &g->bios.data[offset], sizeof(entry));
363
364 gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x",
365 entry.application_id, entry.target_id,
366 entry.desc_ptr);
367
368 if (entry.target_id == TARGET_ID_PMU &&
369 entry.application_id == APPLICATION_ID_DEVINIT) {
370 int err;
371
372 err = gm206_bios_parse_falcon_ucode_desc(g,
373 &g->bios.devinit, entry.desc_ptr);
374 if (err)
375 err = gm206_bios_parse_falcon_ucode_desc(g,
376 &g->bios.devinit,
377 entry.desc_ptr +
378 g->bios.expansion_rom_offset);
379
380 if (err)
381 gk20a_err(dev_from_gk20a(g),
382 "could not parse devinit ucode desc");
383 } else if (entry.target_id == TARGET_ID_PMU &&
384 entry.application_id == APPLICATION_ID_PRE_OS) {
385 int err;
386
387 err = gm206_bios_parse_falcon_ucode_desc(g,
388 &g->bios.preos, entry.desc_ptr);
389 if (err)
390 err = gm206_bios_parse_falcon_ucode_desc(g,
391 &g->bios.preos,
392 entry.desc_ptr +
393 g->bios.expansion_rom_offset);
394
395 if (err)
396 gk20a_err(dev_from_gk20a(g),
397 "could not parse preos ucode desc");
398 }
399
400 offset += hdr.entry_size;
401 }
402
403 return 0;
404}
405
406static void gm206_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
407{
408 struct falcon_data_v2 falcon_data;
409 int err;
410
411 memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data));
412 gk20a_dbg_fn("falcon ucode table ptr %x",
413 falcon_data.falcon_ucode_table_ptr);
414 err = gm206_bios_parse_falcon_ucode_table(g,
415 falcon_data.falcon_ucode_table_ptr);
416 if (err)
417 err = gm206_bios_parse_falcon_ucode_table(g,
418 falcon_data.falcon_ucode_table_ptr +
419 g->bios.expansion_rom_offset);
420
421 if (err)
422 gk20a_err(dev_from_gk20a(g),
423 "could not parse falcon ucode table");
424}
425
426static void gm206_bios_parse_bit(struct gk20a *g, int offset)
427{
428 struct bit bit;
429 struct bit_token bit_token;
430 int i;
431
432 gk20a_dbg_fn("");
433 memcpy(&bit, &g->bios.data[offset], sizeof(bit));
434
435 gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature);
436 gk20a_dbg_info("tokens: %d entries * %d bytes",
437 bit.token_entries, bit.token_size);
438
439 offset += bit.header_size;
440 for (i = 0; i < bit.token_entries; i++) {
441 memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token));
442
443 gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d",
444 bit_token.token_id, bit_token.data_ptr,
445 bit_token.data_size, bit_token.data_version);
446
447 switch (bit_token.token_id) {
448 case TOKEN_ID_NVINIT_PTRS:
449 gm206_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
450 break;
451 case TOKEN_ID_FALCON_DATA:
452 if (bit_token.data_version == 2)
453 gm206_bios_parse_falcon_data_v2(g,
454 bit_token.data_ptr);
455 break;
456 default:
457 break;
458 }
459
460 offset += bit.token_size;
461 }
462 gk20a_dbg_fn("done");
463}
464
465static void upload_code(struct gk20a *g, u32 dst,
466 u8 *src, u32 size, u8 port, bool sec)
467{
468 u32 i, words;
469 u32 *src_u32 = (u32 *)src;
470 u32 blk;
471 u32 tag = 0;
472
473 gk20a_dbg_info("upload %d bytes to %x", size, dst);
474
475 words = size >> 2;
476
477 blk = dst >> 8;
478 tag = blk;
479
480 gk20a_dbg_info("upload %d words to %x block %d",
481 words, dst, blk);
482
483 gk20a_writel(g, pwr_falcon_imemc_r(port),
484 pwr_falcon_imemc_offs_f(dst >> 2) |
485 pwr_falcon_imemc_blk_f(blk) |
486 pwr_falcon_imemc_aincw_f(1) |
487 sec << 28);
488
489 for (i = 0; i < words; i++) {
490 if (i % 64 == 0) {
491 gk20a_writel(g, 0x10a188, tag);
492 tag++;
493 }
494
495 gk20a_writel(g, pwr_falcon_imemd_r(port), src_u32[i]);
496 }
497
498 while (i % 64) {
499 gk20a_writel(g, pwr_falcon_imemd_r(port), 0);
500 i++;
501 }
502}
503
504static void upload_data(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port)
505{
506 u32 i, words;
507 u32 *src_u32 = (u32 *)src;
508 u32 blk;
509
510 gk20a_dbg_info("upload %d bytes to %x", size, dst);
511
512 words = DIV_ROUND_UP(size, 4);
513
514 blk = dst >> 8;
515
516 gk20a_dbg_info("upload %d words to %x blk %d",
517 words, dst, blk);
518 gk20a_writel(g, pwr_falcon_dmemc_r(port),
519 pwr_falcon_dmemc_offs_f(dst >> 2) |
520 pwr_falcon_dmemc_blk_f(blk) |
521 pwr_falcon_dmemc_aincw_f(1));
522
523 for (i = 0; i < words; i++)
524 gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]);
525}
526
527static int gm206_bios_devinit(struct gk20a *g)
528{
529 int retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT;
530 int err = 0;
531 int val;
532
533 gk20a_dbg_fn("");
534 g->ops.pmu.reset(g);
535
536 do {
537 u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
538 (pwr_falcon_dmactl_dmem_scrubbing_m() |
539 pwr_falcon_dmactl_imem_scrubbing_m());
540
541 if (!w) {
542 gk20a_dbg_fn("done");
543 break;
544 }
545 udelay(PMU_BOOT_TIMEOUT_DEFAULT);
546 } while (--retries || !tegra_platform_is_silicon());
547
548 /* todo check retries */
549 upload_code(g, g->bios.devinit.bootloader_phys_base,
550 g->bios.devinit.bootloader,
551 g->bios.devinit.bootloader_size,
552 0, 0);
553 upload_code(g, g->bios.devinit.phys_base,
554 g->bios.devinit.ucode,
555 g->bios.devinit.size,
556 0, 1);
557 upload_data(g, g->bios.devinit.dmem_phys_base,
558 g->bios.devinit.dmem,
559 g->bios.devinit.dmem_size,
560 0);
561 upload_data(g, g->bios.devinit_tables_phys_base,
562 g->bios.devinit_tables,
563 g->bios.devinit_tables_size,
564 0);
565 upload_data(g, g->bios.devinit_script_phys_base,
566 g->bios.bootscripts,
567 g->bios.bootscripts_size,
568 0);
569
570 gk20a_writel(g, pwr_falcon_bootvec_r(),
571 pwr_falcon_bootvec_vec_f(g->bios.devinit.code_entry_point));
572 gk20a_writel(g, pwr_falcon_dmactl_r(),
573 pwr_falcon_dmactl_require_ctx_f(0));
574 gk20a_writel(g, pwr_falcon_cpuctl_r(),
575 pwr_falcon_cpuctl_startcpu_f(1));
576
577 retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT;
578 do {
579 val = top_scratch1_devinit_completed_v(
580 gk20a_readl(g, top_scratch1_r()));
581 udelay(PMU_BOOT_TIMEOUT_DEFAULT);
582 } while (!val && retries--);
583
584 gk20a_writel(g, pwr_falcon_irqsclr_r(),
585 pwr_falcon_irqstat_halt_true_f());
586 gk20a_readl(g, pwr_falcon_irqsclr_r());
587
588 if (!retries)
589 err = -EINVAL;
590
591 gk20a_dbg_fn("done");
592 return err;
593}
594
595static int gm206_bios_preos(struct gk20a *g)
596{
597 int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT;
598 int err = 0;
599 int val;
600
601 gk20a_dbg_fn("");
602 g->ops.pmu.reset(g);
603
604 do {
605 u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
606 (pwr_falcon_dmactl_dmem_scrubbing_m() |
607 pwr_falcon_dmactl_imem_scrubbing_m());
608
609 if (!w) {
610 gk20a_dbg_fn("done");
611 break;
612 }
613 udelay(GR_IDLE_CHECK_DEFAULT);
614 } while (--retries || !tegra_platform_is_silicon());
615
616 /* todo check retries */
617 upload_code(g, g->bios.preos.bootloader_phys_base,
618 g->bios.preos.bootloader,
619 g->bios.preos.bootloader_size,
620 0, 0);
621 upload_code(g, g->bios.preos.phys_base,
622 g->bios.preos.ucode,
623 g->bios.preos.size,
624 0, 1);
625 upload_data(g, g->bios.preos.dmem_phys_base,
626 g->bios.preos.dmem,
627 g->bios.preos.dmem_size,
628 0);
629
630 gk20a_writel(g, pwr_falcon_bootvec_r(),
631 pwr_falcon_bootvec_vec_f(g->bios.preos.code_entry_point));
632 gk20a_writel(g, pwr_falcon_dmactl_r(),
633 pwr_falcon_dmactl_require_ctx_f(0));
634 gk20a_writel(g, pwr_falcon_cpuctl_r(),
635 pwr_falcon_cpuctl_startcpu_f(1));
636
637 retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT;
638 do {
639 val = pwr_falcon_cpuctl_halt_intr_v(
640 gk20a_readl(g, pwr_falcon_cpuctl_r()));
641 udelay(PMU_BOOT_TIMEOUT_DEFAULT);
642 } while (!val && retries--);
643
644 gk20a_writel(g, pwr_falcon_irqsclr_r(),
645 pwr_falcon_irqstat_halt_true_f());
646 gk20a_readl(g, pwr_falcon_irqsclr_r());
647
648 if (!retries)
649 err = -EINVAL;
650
651 gk20a_dbg_fn("done");
652 return err;
653}
654
655static int gm206_bios_init(struct gk20a *g)
656{
657 int i;
658 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
659 struct dentry *d;
660 int err;
661
662 gk20a_dbg_fn("");
663 g->bios.data = kzalloc(BIOS_SIZE, GFP_KERNEL);
664 if (!g->bios.data)
665 return -ENOMEM;
666
667 gk20a_dbg_info("reading bios");
668 gk20a_writel(g, NV_PCFG + xve_rom_ctrl_r(),
669 xve_rom_ctrl_rom_shadow_disabled_f());
670 for (i = 0; i < BIOS_SIZE/4; i++) {
671 u32 val = be32_to_cpu(gk20a_readl(g, 0x300000 + i*4));
672
673 g->bios.data[(i*4)] = (val >> 24) & 0xff;
674 g->bios.data[(i*4)+1] = (val >> 16) & 0xff;
675 g->bios.data[(i*4)+2] = (val >> 8) & 0xff;
676 g->bios.data[(i*4)+3] = val & 0xff;
677 }
678 gk20a_writel(g, NV_PCFG + xve_rom_ctrl_r(),
679 xve_rom_ctrl_rom_shadow_enabled_f());
680
681 gm206_bios_parse_rom(g);
682 gk20a_dbg_info("read bios");
683 for (i = 0; i < BIOS_SIZE; i++) {
684 if (gm206_bios_rdu16(g, i) == BIT_HEADER_ID &&
685 gm206_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) {
686 gm206_bios_parse_bit(g, i);
687 }
688 }
689
690 g->bios_blob.data = g->bios.data;
691 g->bios_blob.size = BIOS_SIZE;
692
693 d = debugfs_create_blob("bios", S_IRUGO, platform->debugfs,
694 &g->bios_blob);
695 if (!d)
696 gk20a_err(g->dev, "No debugfs?");
697
698 gk20a_dbg_fn("done");
699
700 err = gm206_bios_devinit(g);
701 if (err) {
702 gk20a_err(g->dev, "devinit failed");
703 return err;
704 }
705
706 err = gm206_bios_preos(g);
707 if (err) {
708 gk20a_err(g->dev, "pre-os failed");
709 return err;
710 }
711
712 return 0;
713}
714
715void gm206_init_bios(struct gpu_ops *gops)
716{
717 gops->bios.init = gm206_bios_init;
718}
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.h b/drivers/gpu/nvgpu/gm206/bios_gm206.h
new file mode 100644
index 00000000..28bfd7b8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef NVGPU_BIOS_GM206_H
15#define NVGPU_BIOS_GM206_H
16struct gpu_ops;
17
18void gm206_init_bios(struct gpu_ops *gops);
19#endif
diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.c b/drivers/gpu/nvgpu/gm206/fifo_gm206.c
new file mode 100644
index 00000000..c78f256c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/fifo_gm206.c
@@ -0,0 +1,31 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/types.h>
16
17#include "gk20a/gk20a.h"
18#include "gm20b/fifo_gm20b.h"
19#include "fifo_gm206.h"
20#include "hw_ccsr_gm206.h"
21
22static u32 gm206_fifo_get_num_fifos(struct gk20a *g)
23{
24 return ccsr_channel__size_1_v();
25}
26
27void gm206_init_fifo(struct gpu_ops *gops)
28{
29 gm20b_init_fifo(gops);
30 gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos;
31}
diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.h b/drivers/gpu/nvgpu/gm206/fifo_gm206.h
new file mode 100644
index 00000000..5cad0e8a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/fifo_gm206.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef NVGPU_FIFO_GM206_H
15#define NVGPU_FIFO_GM206_H
16struct gpu_ops;
17void gm206_init_fifo(struct gpu_ops *gops);
18#endif
diff --git a/drivers/gpu/nvgpu/gm206/gr_gm206.c b/drivers/gpu/nvgpu/gm206/gr_gm206.c
new file mode 100644
index 00000000..cad080ac
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/gr_gm206.c
@@ -0,0 +1,92 @@
1/*
2 * gm206 GR
3 *
4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/delay.h> /* for mdelay */
18#include <linux/io.h>
19#include <linux/tegra-fuse.h>
20#include <linux/vmalloc.h>
21
22#include "gk20a/gk20a.h"
23
24#include "gm20b/gr_gm20b.h"
25#include "gr_gm206.h"
26#include "hw_fb_gm206.h"
27#include "hw_gr_gm206.h"
28
29static void gr_gm206_init_gpc_mmu(struct gk20a *g)
30{
31 u32 temp;
32
33 gk20a_dbg_info("initialize gpc mmu");
34
35 temp = gk20a_readl(g, fb_mmu_ctrl_r());
36 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
37 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
38 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
39 gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
40 gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
41 gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
42 gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
43 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
44 gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
45 gr_gpcs_pri_mmu_ctrl_mmu_disable_m();
46 gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
47 gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
48 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
49
50 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
51 gk20a_readl(g, fb_mmu_debug_ctrl_r()));
52 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
53 gk20a_readl(g, fb_mmu_debug_wr_r()));
54 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
55 gk20a_readl(g, fb_mmu_debug_rd_r()));
56
57 gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(),
58 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
59 /* TODO: num_active_ltcs2! */
60 gk20a_writel(g, 0x50833c, gk20a_readl(g, 0x100804));
61}
62
63static void gr_gm206_bundle_cb_defaults(struct gk20a *g)
64{
65 struct gr_gk20a *gr = &g->gr;
66
67 gr->bundle_cb_default_size =
68 gr_scc_bundle_cb_size_div_256b__prod_v();
69 gr->min_gpm_fifo_depth =
70 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
71 gr->bundle_cb_token_limit =
72 gr_pd_ab_dist_cfg2_token_limit_init_v();
73}
74
75static void gr_gm206_cb_size_default(struct gk20a *g)
76{
77 struct gr_gk20a *gr = &g->gr;
78
79 if (!gr->attrib_cb_default_size)
80 gr->attrib_cb_default_size =
81 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
82 gr->alpha_cb_default_size =
83 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
84}
85
86void gm206_init_gr(struct gpu_ops *gops)
87{
88 gm20b_init_gr(gops);
89 gops->gr.init_gpc_mmu = gr_gm206_init_gpc_mmu;
90 gops->gr.bundle_cb_defaults = gr_gm206_bundle_cb_defaults;
91 gops->gr.cb_size_default = gr_gm206_cb_size_default;
92}
diff --git a/drivers/gpu/nvgpu/gm206/gr_gm206.h b/drivers/gpu/nvgpu/gm206/gr_gm206.h
new file mode 100644
index 00000000..740685e8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/gr_gm206.h
@@ -0,0 +1,23 @@
1/*
2 * GM206 GR
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GM206_GR_H
17#define _NVGPU_GM206_GR_H
18
19struct gpu_ops;
20
21void gm206_init_gr(struct gpu_ops *gops);
22
23#endif
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c
new file mode 100644
index 00000000..aa6b676f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c
@@ -0,0 +1,206 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/types.h>
15#include <linux/printk.h>
16
17#include <linux/types.h>
18
19#include "gk20a/gk20a.h"
20
21#include "gm20b/mc_gm20b.h"
22#include "gm20b/ltc_gm20b.h"
23#include "gm20b/mm_gm20b.h"
24#include "gm20b/ce2_gm20b.h"
25#include "gm20b/fb_gm20b.h"
26#include "gm20b/pmu_gm20b.h"
27#include "gm20b/gr_gm20b.h"
28#include "gm20b/gr_ctx_gm20b.h"
29#include "gm20b/gm20b_gating_reglist.h"
30#include "gm20b/regops_gm20b.h"
31#include "gm20b/cde_gm20b.h"
32#include "gm20b/therm_gm20b.h"
33#include "gm20b/clk_gm20b.h"
34#include "gm20b/debug_gm20b.h"
35
36#include "fifo_gm206.h"
37#include "bios_gm206.h"
38#include "gr_gm206.h"
39#include "hw_proj_gm206.h"
40
41static struct gpu_ops gm206_ops = {
42 .clock_gating = {
43 .slcg_bus_load_gating_prod =
44 gm20b_slcg_bus_load_gating_prod,
45 .slcg_ce2_load_gating_prod =
46 gm20b_slcg_ce2_load_gating_prod,
47 .slcg_chiplet_load_gating_prod =
48 gm20b_slcg_chiplet_load_gating_prod,
49 .slcg_ctxsw_firmware_load_gating_prod =
50 gm20b_slcg_ctxsw_firmware_load_gating_prod,
51 .slcg_fb_load_gating_prod =
52 gm20b_slcg_fb_load_gating_prod,
53 .slcg_fifo_load_gating_prod =
54 gm20b_slcg_fifo_load_gating_prod,
55 .slcg_gr_load_gating_prod =
56 gr_gm20b_slcg_gr_load_gating_prod,
57 .slcg_ltc_load_gating_prod =
58 ltc_gm20b_slcg_ltc_load_gating_prod,
59 .slcg_perf_load_gating_prod =
60 gm20b_slcg_perf_load_gating_prod,
61 .slcg_priring_load_gating_prod =
62 gm20b_slcg_priring_load_gating_prod,
63 .slcg_pmu_load_gating_prod =
64 gm20b_slcg_pmu_load_gating_prod,
65 .slcg_therm_load_gating_prod =
66 gm20b_slcg_therm_load_gating_prod,
67 .slcg_xbar_load_gating_prod =
68 gm20b_slcg_xbar_load_gating_prod,
69 .blcg_bus_load_gating_prod =
70 gm20b_blcg_bus_load_gating_prod,
71 .blcg_ctxsw_firmware_load_gating_prod =
72 gm20b_blcg_ctxsw_firmware_load_gating_prod,
73 .blcg_fb_load_gating_prod =
74 gm20b_blcg_fb_load_gating_prod,
75 .blcg_fifo_load_gating_prod =
76 gm20b_blcg_fifo_load_gating_prod,
77 .blcg_gr_load_gating_prod =
78 gm20b_blcg_gr_load_gating_prod,
79 .blcg_ltc_load_gating_prod =
80 gm20b_blcg_ltc_load_gating_prod,
81 .blcg_pwr_csb_load_gating_prod =
82 gm20b_blcg_pwr_csb_load_gating_prod,
83 .blcg_pmu_load_gating_prod =
84 gm20b_blcg_pmu_load_gating_prod,
85 .blcg_xbar_load_gating_prod =
86 gm20b_blcg_xbar_load_gating_prod,
87 .pg_gr_load_gating_prod =
88 gr_gm20b_pg_gr_load_gating_prod,
89 }
90};
91
92static int gm206_get_litter_value(struct gk20a *g,
93 enum nvgpu_litter_value value)
94{
95 int ret = -EINVAL;
96
97 switch (value) {
98 case GPU_LIT_NUM_GPCS:
99 ret = proj_scal_litter_num_gpcs_v();
100 break;
101 case GPU_LIT_NUM_PES_PER_GPC:
102 ret = proj_scal_litter_num_pes_per_gpc_v();
103 break;
104 case GPU_LIT_NUM_ZCULL_BANKS:
105 ret = proj_scal_litter_num_zcull_banks_v();
106 break;
107 case GPU_LIT_NUM_TPC_PER_GPC:
108 ret = proj_scal_litter_num_tpc_per_gpc_v();
109 break;
110 case GPU_LIT_NUM_FBPS:
111 ret = proj_scal_litter_num_fbps_v();
112 break;
113 case GPU_LIT_GPC_BASE:
114 ret = proj_gpc_base_v();
115 break;
116 case GPU_LIT_GPC_STRIDE:
117 ret = proj_gpc_stride_v();
118 break;
119 case GPU_LIT_GPC_SHARED_BASE:
120 ret = proj_gpc_shared_base_v();
121 break;
122 case GPU_LIT_TPC_IN_GPC_BASE:
123 ret = proj_tpc_in_gpc_base_v();
124 break;
125 case GPU_LIT_TPC_IN_GPC_STRIDE:
126 ret = proj_tpc_in_gpc_stride_v();
127 break;
128 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
129 ret = proj_tpc_in_gpc_shared_base_v();
130 break;
131 case GPU_LIT_PPC_IN_GPC_STRIDE:
132 ret = proj_ppc_in_gpc_stride_v();
133 break;
134 case GPU_LIT_ROP_BASE:
135 ret = proj_rop_base_v();
136 break;
137 case GPU_LIT_ROP_STRIDE:
138 ret = proj_rop_stride_v();
139 break;
140 case GPU_LIT_ROP_SHARED_BASE:
141 ret = proj_rop_shared_base_v();
142 break;
143 case GPU_LIT_HOST_NUM_PBDMA:
144 ret = proj_host_num_pbdma_v();
145 break;
146 case GPU_LIT_LTC_STRIDE:
147 ret = proj_ltc_stride_v();
148 break;
149 case GPU_LIT_LTS_STRIDE:
150 ret = proj_lts_stride_v();
151 break;
152 case GPU_LIT_NUM_FBPAS:
153 ret = proj_scal_litter_num_fbpas_v();
154 break;
155 case GPU_LIT_FBPA_STRIDE:
156 ret = proj_fbpa_stride_v();
157 break;
158 default:
159 BUG();
160 break;
161 }
162
163 return ret;
164}
165
166int gm206_init_hal(struct gk20a *g)
167{
168 struct gpu_ops *gops = &g->ops;
169 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
170
171 *gops = gm206_ops;
172
173 gops->privsecurity = 0;
174 gops->securegpccs = 0;
175
176 gm20b_init_mc(gops);
177 gm20b_init_ltc(gops);
178 gm206_init_gr(gops);
179 gm20b_init_ltc(gops);
180 gm20b_init_fb(gops);
181 g->ops.fb.set_use_full_comp_tag_line = NULL;
182 gm206_init_fifo(gops);
183 gm20b_init_ce2(gops);
184 gm20b_init_gr_ctx(gops);
185 gm20b_init_mm(gops);
186 gm20b_init_pmu_ops(gops);
187 gm20b_init_clk_ops(gops);
188 gm20b_init_regops(gops);
189 gm20b_init_debug_ops(gops);
190 gm20b_init_cde_ops(gops);
191 gm20b_init_therm_ops(gops);
192 gm206_init_bios(gops);
193 gops->name = "gm206";
194 gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
195 gops->get_litter_value = gm206_get_litter_value;
196 gops->gr_ctx.use_dma_for_fw_bootstrap = false;
197
198 c->twod_class = FERMI_TWOD_A;
199 c->threed_class = MAXWELL_B;
200 c->compute_class = MAXWELL_COMPUTE_B;
201 c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A;
202 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
203 c->dma_copy_class = MAXWELL_DMA_COPY_A;
204
205 return 0;
206}
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.h b/drivers/gpu/nvgpu/gm206/hal_gm206.h
new file mode 100644
index 00000000..b7fab24c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hal_gm206.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef _NVGPU_HAL_GM206_H
15#define _NVGPU_HAL_GM206_H
16struct gk20a;
17
18int gm206_init_hal(struct gk20a *gops);
19#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_bus_gm206.h b/drivers/gpu/nvgpu/gm206/hw_bus_gm206.h
new file mode 100644
index 00000000..de1884f5
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_bus_gm206.h
@@ -0,0 +1,193 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_bus_gm206_h_
51#define _hw_bus_gm206_h_
52
53static inline u32 bus_bar1_block_r(void)
54{
55 return 0x00001704;
56}
57static inline u32 bus_bar1_block_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 bus_bar1_block_target_vid_mem_f(void)
62{
63 return 0x0;
64}
65static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
66{
67 return 0x20000000;
68}
69static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
70{
71 return 0x30000000;
72}
73static inline u32 bus_bar1_block_mode_virtual_f(void)
74{
75 return 0x80000000;
76}
77static inline u32 bus_bar2_block_r(void)
78{
79 return 0x00001714;
80}
81static inline u32 bus_bar2_block_ptr_f(u32 v)
82{
83 return (v & 0xfffffff) << 0;
84}
85static inline u32 bus_bar2_block_target_vid_mem_f(void)
86{
87 return 0x0;
88}
89static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
90{
91 return 0x20000000;
92}
93static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
94{
95 return 0x30000000;
96}
97static inline u32 bus_bar2_block_mode_virtual_f(void)
98{
99 return 0x80000000;
100}
101static inline u32 bus_bar1_block_ptr_shift_v(void)
102{
103 return 0x0000000c;
104}
105static inline u32 bus_bar2_block_ptr_shift_v(void)
106{
107 return 0x0000000c;
108}
109static inline u32 bus_bind_status_r(void)
110{
111 return 0x00001710;
112}
113static inline u32 bus_bind_status_bar1_pending_v(u32 r)
114{
115 return (r >> 0) & 0x1;
116}
117static inline u32 bus_bind_status_bar1_pending_empty_f(void)
118{
119 return 0x0;
120}
121static inline u32 bus_bind_status_bar1_pending_busy_f(void)
122{
123 return 0x1;
124}
125static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
126{
127 return (r >> 1) & 0x1;
128}
129static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
130{
131 return 0x0;
132}
133static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
134{
135 return 0x2;
136}
137static inline u32 bus_bind_status_bar2_pending_v(u32 r)
138{
139 return (r >> 2) & 0x1;
140}
141static inline u32 bus_bind_status_bar2_pending_empty_f(void)
142{
143 return 0x0;
144}
145static inline u32 bus_bind_status_bar2_pending_busy_f(void)
146{
147 return 0x4;
148}
149static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
150{
151 return (r >> 3) & 0x1;
152}
153static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
154{
155 return 0x0;
156}
157static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
158{
159 return 0x8;
160}
161static inline u32 bus_intr_0_r(void)
162{
163 return 0x00001100;
164}
165static inline u32 bus_intr_0_pri_squash_m(void)
166{
167 return 0x1 << 1;
168}
169static inline u32 bus_intr_0_pri_fecserr_m(void)
170{
171 return 0x1 << 2;
172}
173static inline u32 bus_intr_0_pri_timeout_m(void)
174{
175 return 0x1 << 3;
176}
177static inline u32 bus_intr_en_0_r(void)
178{
179 return 0x00001140;
180}
181static inline u32 bus_intr_en_0_pri_squash_m(void)
182{
183 return 0x1 << 1;
184}
185static inline u32 bus_intr_en_0_pri_fecserr_m(void)
186{
187 return 0x1 << 2;
188}
189static inline u32 bus_intr_en_0_pri_timeout_m(void)
190{
191 return 0x1 << 3;
192}
193#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_ccsr_gm206.h b/drivers/gpu/nvgpu/gm206/hw_ccsr_gm206.h
new file mode 100644
index 00000000..729ad2e9
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_ccsr_gm206.h
@@ -0,0 +1,125 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ccsr_gm206_h_
51#define _hw_ccsr_gm206_h_
52
53static inline u32 ccsr_channel_inst_r(u32 i)
54{
55 return 0x00800000 + i*8;
56}
57static inline u32 ccsr_channel_inst__size_1_v(void)
58{
59 return 0x00001000;
60}
61static inline u32 ccsr_channel_inst_ptr_f(u32 v)
62{
63 return (v & 0xfffffff) << 0;
64}
65static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
66{
67 return 0x0;
68}
69static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
70{
71 return 0x20000000;
72}
73static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
74{
75 return 0x30000000;
76}
77static inline u32 ccsr_channel_inst_bind_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 ccsr_channel_inst_bind_true_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 ccsr_channel_r(u32 i)
86{
87 return 0x00800004 + i*8;
88}
89static inline u32 ccsr_channel__size_1_v(void)
90{
91 return 0x00001000;
92}
93static inline u32 ccsr_channel_enable_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 ccsr_channel_enable_set_f(u32 v)
98{
99 return (v & 0x1) << 10;
100}
101static inline u32 ccsr_channel_enable_set_true_f(void)
102{
103 return 0x400;
104}
105static inline u32 ccsr_channel_enable_clr_true_f(void)
106{
107 return 0x800;
108}
109static inline u32 ccsr_channel_status_v(u32 r)
110{
111 return (r >> 24) & 0xf;
112}
113static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
114{
115 return 0x00000002;
116}
117static inline u32 ccsr_channel_busy_v(u32 r)
118{
119 return (r >> 28) & 0x1;
120}
121static inline u32 ccsr_channel_next_v(u32 r)
122{
123 return (r >> 1) & 0x1;
124}
125#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_ce2_gm206.h b/drivers/gpu/nvgpu/gm206/hw_ce2_gm206.h
new file mode 100644
index 00000000..2eda4a9e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_ce2_gm206.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ce2_gm206_h_
51#define _hw_ce2_gm206_h_
52
53static inline u32 ce2_intr_status_r(void)
54{
55 return 0x00106908;
56}
57static inline u32 ce2_intr_status_blockpipe_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 ce2_intr_status_blockpipe_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 ce2_intr_status_launcherr_pending_f(void)
74{
75 return 0x4;
76}
77static inline u32 ce2_intr_status_launcherr_reset_f(void)
78{
79 return 0x4;
80}
81#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_ctxsw_prog_gm206.h b/drivers/gpu/nvgpu/gm206/hw_ctxsw_prog_gm206.h
new file mode 100644
index 00000000..adb2f64c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_ctxsw_prog_gm206.h
@@ -0,0 +1,253 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ctxsw_prog_gm206_h_
51#define _hw_ctxsw_prog_gm206_h_
52
53static inline u32 ctxsw_prog_fecs_header_v(void)
54{
55 return 0x00000100;
56}
57static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
58{
59 return 0x00000008;
60}
61static inline u32 ctxsw_prog_main_image_patch_count_o(void)
62{
63 return 0x00000010;
64}
65static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
66{
67 return 0x00000014;
68}
69static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
70{
71 return 0x00000018;
72}
73static inline u32 ctxsw_prog_main_image_zcull_o(void)
74{
75 return 0x0000001c;
76}
77static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
82{
83 return 0x00000002;
84}
85static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
86{
87 return 0x00000020;
88}
89static inline u32 ctxsw_prog_main_image_pm_o(void)
90{
91 return 0x00000028;
92}
93static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
94{
95 return 0x7 << 0;
96}
97static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
98{
99 return 0x0;
100}
101static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
102{
103 return 0x7 << 3;
104}
105static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
106{
107 return 0x8;
108}
109static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
110{
111 return 0x0;
112}
113static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
114{
115 return 0x0000002c;
116}
117static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
118{
119 return 0x000000f4;
120}
121static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
122{
123 return 0x000000f8;
124}
125static inline u32 ctxsw_prog_main_image_magic_value_o(void)
126{
127 return 0x000000fc;
128}
129static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
130{
131 return 0x600dc0de;
132}
133static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
134{
135 return 0x0000000c;
136}
137static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
138{
139 return (r >> 0) & 0xffff;
140}
141static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
142{
143 return 0x000000f4;
144}
145static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
146{
147 return (r >> 0) & 0xffff;
148}
149static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
150{
151 return (r >> 16) & 0xffff;
152}
153static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
154{
155 return 0x000000f8;
156}
157static inline u32 ctxsw_prog_local_magic_value_o(void)
158{
159 return 0x000000fc;
160}
161static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
162{
163 return 0xad0becab;
164}
165static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
166{
167 return 0x000000ec;
168}
169static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
170{
171 return (r >> 0) & 0xffff;
172}
173static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
174{
175 return (r >> 16) & 0xff;
176}
177static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
178{
179 return 0x00000100;
180}
181static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
182{
183 return 0x00000004;
184}
185static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
186{
187 return 0x00000000;
188}
189static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
190{
191 return 0x00000002;
192}
193static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
194{
195 return 0x000000a0;
196}
197static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
198{
199 return 2;
200}
201static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
202{
203 return (v & 0x3) << 0;
204}
205static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
206{
207 return 0x3 << 0;
208}
209static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
210{
211 return (r >> 0) & 0x3;
212}
213static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
214{
215 return 0x0;
216}
217static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
218{
219 return 0x2;
220}
221static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
222{
223 return 0x000000a4;
224}
225static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
226{
227 return 0x000000a8;
228}
229static inline u32 ctxsw_prog_main_image_misc_options_o(void)
230{
231 return 0x0000003c;
232}
233static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
234{
235 return 0x1 << 3;
236}
237static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
238{
239 return 0x0;
240}
241static inline u32 ctxsw_prog_main_image_preemption_options_o(void)
242{
243 return 0x00000060;
244}
245static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v)
246{
247 return (v & 0x3) << 0;
248}
249static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void)
250{
251 return 0x1;
252}
253#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_fb_gm206.h b/drivers/gpu/nvgpu/gm206/hw_fb_gm206.h
new file mode 100644
index 00000000..6d4b31c6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_fb_gm206.h
@@ -0,0 +1,337 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fb_gm206_h_
51#define _hw_fb_gm206_h_
52
53static inline u32 fb_fbhub_num_active_ltcs_r(void)
54{
55 return 0x00100800;
56}
57static inline u32 fb_mmu_ctrl_r(void)
58{
59 return 0x00100c80;
60}
61static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
62{
63 return (v & 0x1) << 0;
64}
65static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
66{
67 return 0x0;
68}
69static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
70{
71 return 0x1;
72}
73static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
74{
75 return (r >> 15) & 0x1;
76}
77static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
82{
83 return (r >> 16) & 0xff;
84}
85static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
86{
87 return (r >> 11) & 0x1;
88}
89static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
90{
91 return 0x800;
92}
93static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
94{
95 return 0x0;
96}
97static inline u32 fb_priv_mmu_phy_secure_r(void)
98{
99 return 0x00100ce4;
100}
101static inline u32 fb_mmu_invalidate_pdb_r(void)
102{
103 return 0x00100cb8;
104}
105static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
106{
107 return 0x0;
108}
109static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
110{
111 return 0x2;
112}
113static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
114{
115 return (v & 0xfffffff) << 4;
116}
117static inline u32 fb_mmu_invalidate_r(void)
118{
119 return 0x00100cbc;
120}
121static inline u32 fb_mmu_invalidate_all_va_true_f(void)
122{
123 return 0x1;
124}
125static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
126{
127 return 0x2;
128}
129static inline u32 fb_mmu_invalidate_trigger_s(void)
130{
131 return 1;
132}
133static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
134{
135 return (v & 0x1) << 31;
136}
137static inline u32 fb_mmu_invalidate_trigger_m(void)
138{
139 return 0x1 << 31;
140}
141static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
142{
143 return (r >> 31) & 0x1;
144}
145static inline u32 fb_mmu_invalidate_trigger_true_f(void)
146{
147 return 0x80000000;
148}
149static inline u32 fb_mmu_debug_wr_r(void)
150{
151 return 0x00100cc8;
152}
153static inline u32 fb_mmu_debug_wr_aperture_s(void)
154{
155 return 2;
156}
157static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
158{
159 return (v & 0x3) << 0;
160}
161static inline u32 fb_mmu_debug_wr_aperture_m(void)
162{
163 return 0x3 << 0;
164}
165static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
166{
167 return (r >> 0) & 0x3;
168}
169static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
170{
171 return 0x0;
172}
173static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
174{
175 return 0x2;
176}
177static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
178{
179 return 0x3;
180}
181static inline u32 fb_mmu_debug_wr_vol_false_f(void)
182{
183 return 0x0;
184}
185static inline u32 fb_mmu_debug_wr_vol_true_v(void)
186{
187 return 0x00000001;
188}
189static inline u32 fb_mmu_debug_wr_vol_true_f(void)
190{
191 return 0x4;
192}
193static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
194{
195 return (v & 0xfffffff) << 4;
196}
197static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
198{
199 return 0x0000000c;
200}
201static inline u32 fb_mmu_debug_rd_r(void)
202{
203 return 0x00100ccc;
204}
205static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
206{
207 return 0x0;
208}
209static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
210{
211 return 0x2;
212}
213static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
214{
215 return 0x3;
216}
217static inline u32 fb_mmu_debug_rd_vol_false_f(void)
218{
219 return 0x0;
220}
221static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
222{
223 return (v & 0xfffffff) << 4;
224}
225static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
226{
227 return 0x0000000c;
228}
229static inline u32 fb_mmu_debug_ctrl_r(void)
230{
231 return 0x00100cc4;
232}
233static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
234{
235 return (r >> 16) & 0x1;
236}
237static inline u32 fb_mmu_debug_ctrl_debug_m(void)
238{
239 return 0x1 << 16;
240}
241static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
242{
243 return 0x00000001;
244}
245static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
246{
247 return 0x10000;
248}
249static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
250{
251 return 0x00000000;
252}
253static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
254{
255 return 0x0;
256}
257static inline u32 fb_mmu_vpr_info_r(void)
258{
259 return 0x00100cd0;
260}
261static inline u32 fb_mmu_vpr_info_index_f(u32 v)
262{
263 return (v & 0x3) << 0;
264}
265static inline u32 fb_mmu_vpr_info_index_v(u32 r)
266{
267 return (r >> 0) & 0x3;
268}
269static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
274{
275 return 0x00000001;
276}
277static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
278{
279 return 0x00000002;
280}
281static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
282{
283 return 0x00000003;
284}
285static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
286{
287 return (v & 0x1) << 2;
288}
289static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
290{
291 return (r >> 2) & 0x1;
292}
293static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
294{
295 return 0x00000000;
296}
297static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
298{
299 return 0x00000001;
300}
301static inline u32 fb_mmu_wpr_info_r(void)
302{
303 return 0x00100cd4;
304}
305static inline u32 fb_mmu_wpr_info_index_f(u32 v)
306{
307 return (v & 0xf) << 0;
308}
309static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
310{
311 return 0x00000000;
312}
313static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
314{
315 return 0x00000001;
316}
317static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
318{
319 return 0x00000002;
320}
321static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
322{
323 return 0x00000003;
324}
325static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
326{
327 return 0x00000004;
328}
329static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
330{
331 return 0x00000005;
332}
333static inline u32 fb_niso_flush_sysmem_addr_r(void)
334{
335 return 0x00100c10;
336}
337#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h b/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h
new file mode 100644
index 00000000..56654124
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h
@@ -0,0 +1,553 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fifo_gm206_h_
51#define _hw_fifo_gm206_h_
52
53static inline u32 fifo_bar1_base_r(void)
54{
55 return 0x00002254;
56}
57static inline u32 fifo_bar1_base_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
62{
63 return 0x0000000c;
64}
65static inline u32 fifo_bar1_base_valid_false_f(void)
66{
67 return 0x0;
68}
69static inline u32 fifo_bar1_base_valid_true_f(void)
70{
71 return 0x10000000;
72}
73static inline u32 fifo_runlist_base_r(void)
74{
75 return 0x00002270;
76}
77static inline u32 fifo_runlist_base_ptr_f(u32 v)
78{
79 return (v & 0xfffffff) << 0;
80}
81static inline u32 fifo_runlist_base_target_vid_mem_f(void)
82{
83 return 0x0;
84}
85static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
86{
87 return 0x20000000;
88}
89static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
90{
91 return 0x30000000;
92}
93static inline u32 fifo_runlist_r(void)
94{
95 return 0x00002274;
96}
97static inline u32 fifo_runlist_engine_f(u32 v)
98{
99 return (v & 0xf) << 20;
100}
101static inline u32 fifo_eng_runlist_base_r(u32 i)
102{
103 return 0x00002280 + i*8;
104}
105static inline u32 fifo_eng_runlist_base__size_1_v(void)
106{
107 return 0x00000007;
108}
109static inline u32 fifo_eng_runlist_r(u32 i)
110{
111 return 0x00002284 + i*8;
112}
113static inline u32 fifo_eng_runlist__size_1_v(void)
114{
115 return 0x00000007;
116}
117static inline u32 fifo_eng_runlist_length_f(u32 v)
118{
119 return (v & 0xffff) << 0;
120}
121static inline u32 fifo_eng_runlist_length_max_v(void)
122{
123 return 0x0000ffff;
124}
125static inline u32 fifo_eng_runlist_pending_true_f(void)
126{
127 return 0x100000;
128}
129static inline u32 fifo_pb_timeslice_r(u32 i)
130{
131 return 0x00002350 + i*4;
132}
133static inline u32 fifo_pb_timeslice_timeout_16_f(void)
134{
135 return 0x10;
136}
137static inline u32 fifo_pb_timeslice_timescale_0_f(void)
138{
139 return 0x0;
140}
141static inline u32 fifo_pb_timeslice_enable_true_f(void)
142{
143 return 0x10000000;
144}
145static inline u32 fifo_pbdma_map_r(u32 i)
146{
147 return 0x00002390 + i*4;
148}
149static inline u32 fifo_intr_0_r(void)
150{
151 return 0x00002100;
152}
153static inline u32 fifo_intr_0_bind_error_pending_f(void)
154{
155 return 0x1;
156}
157static inline u32 fifo_intr_0_bind_error_reset_f(void)
158{
159 return 0x1;
160}
161static inline u32 fifo_intr_0_sched_error_pending_f(void)
162{
163 return 0x100;
164}
165static inline u32 fifo_intr_0_sched_error_reset_f(void)
166{
167 return 0x100;
168}
169static inline u32 fifo_intr_0_chsw_error_pending_f(void)
170{
171 return 0x10000;
172}
173static inline u32 fifo_intr_0_chsw_error_reset_f(void)
174{
175 return 0x10000;
176}
177static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
178{
179 return 0x800000;
180}
181static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
182{
183 return 0x800000;
184}
185static inline u32 fifo_intr_0_lb_error_pending_f(void)
186{
187 return 0x1000000;
188}
189static inline u32 fifo_intr_0_lb_error_reset_f(void)
190{
191 return 0x1000000;
192}
193static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
194{
195 return 0x8000000;
196}
197static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
198{
199 return 0x8000000;
200}
201static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
202{
203 return 0x10000000;
204}
205static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
206{
207 return 0x20000000;
208}
209static inline u32 fifo_intr_0_runlist_event_pending_f(void)
210{
211 return 0x40000000;
212}
213static inline u32 fifo_intr_0_channel_intr_pending_f(void)
214{
215 return 0x80000000;
216}
217static inline u32 fifo_intr_en_0_r(void)
218{
219 return 0x00002140;
220}
221static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
222{
223 return (v & 0x1) << 8;
224}
225static inline u32 fifo_intr_en_0_sched_error_m(void)
226{
227 return 0x1 << 8;
228}
229static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
230{
231 return (v & 0x1) << 28;
232}
233static inline u32 fifo_intr_en_0_mmu_fault_m(void)
234{
235 return 0x1 << 28;
236}
237static inline u32 fifo_intr_en_1_r(void)
238{
239 return 0x00002528;
240}
241static inline u32 fifo_intr_bind_error_r(void)
242{
243 return 0x0000252c;
244}
245static inline u32 fifo_intr_sched_error_r(void)
246{
247 return 0x0000254c;
248}
249static inline u32 fifo_intr_sched_error_code_f(u32 v)
250{
251 return (v & 0xff) << 0;
252}
253static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
254{
255 return 0x0000000a;
256}
257static inline u32 fifo_intr_chsw_error_r(void)
258{
259 return 0x0000256c;
260}
261static inline u32 fifo_intr_mmu_fault_id_r(void)
262{
263 return 0x0000259c;
264}
265static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
266{
267 return 0x00000000;
268}
269static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
270{
271 return 0x0;
272}
273static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
274{
275 return 0x00002800 + i*16;
276}
277static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
278{
279 return (r >> 0) & 0xfffffff;
280}
281static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
282{
283 return 0x0000000c;
284}
285static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
286{
287 return 0x00002804 + i*16;
288}
289static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
290{
291 return 0x00002808 + i*16;
292}
293static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
294{
295 return 0x0000280c + i*16;
296}
297static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
298{
299 return (r >> 0) & 0xf;
300}
301static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
302{
303 return (r >> 6) & 0x1;
304}
305static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
306{
307 return 0x00000000;
308}
309static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
310{
311 return 0x00000001;
312}
313static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
314{
315 return (r >> 8) & 0x3f;
316}
317static inline u32 fifo_intr_pbdma_id_r(void)
318{
319 return 0x000025a0;
320}
321static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
322{
323 return (v & 0x1) << (0 + i*1);
324}
325static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
326{
327 return 0x00000003;
328}
329static inline u32 fifo_intr_runlist_r(void)
330{
331 return 0x00002a00;
332}
333static inline u32 fifo_fb_timeout_r(void)
334{
335 return 0x00002a04;
336}
337static inline u32 fifo_fb_timeout_period_m(void)
338{
339 return 0x3fffffff << 0;
340}
341static inline u32 fifo_fb_timeout_period_max_f(void)
342{
343 return 0x3fffffff;
344}
345static inline u32 fifo_error_sched_disable_r(void)
346{
347 return 0x0000262c;
348}
349static inline u32 fifo_sched_disable_r(void)
350{
351 return 0x00002630;
352}
353static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
354{
355 return (v & 0x1) << (0 + i*1);
356}
357static inline u32 fifo_sched_disable_runlist_m(u32 i)
358{
359 return 0x1 << (0 + i*1);
360}
361static inline u32 fifo_sched_disable_true_v(void)
362{
363 return 0x00000001;
364}
365static inline u32 fifo_preempt_r(void)
366{
367 return 0x00002634;
368}
369static inline u32 fifo_preempt_pending_true_f(void)
370{
371 return 0x100000;
372}
373static inline u32 fifo_preempt_type_channel_f(void)
374{
375 return 0x0;
376}
377static inline u32 fifo_preempt_type_tsg_f(void)
378{
379 return 0x1000000;
380}
381static inline u32 fifo_preempt_chid_f(u32 v)
382{
383 return (v & 0xfff) << 0;
384}
385static inline u32 fifo_preempt_id_f(u32 v)
386{
387 return (v & 0xfff) << 0;
388}
389static inline u32 fifo_trigger_mmu_fault_r(u32 i)
390{
391 return 0x00002a30 + i*4;
392}
393static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
394{
395 return (v & 0x1f) << 0;
396}
397static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
398{
399 return (v & 0x1) << 8;
400}
401static inline u32 fifo_engine_status_r(u32 i)
402{
403 return 0x00002640 + i*8;
404}
405static inline u32 fifo_engine_status__size_1_v(void)
406{
407 return 0x00000008;
408}
409static inline u32 fifo_engine_status_id_v(u32 r)
410{
411 return (r >> 0) & 0xfff;
412}
413static inline u32 fifo_engine_status_id_type_v(u32 r)
414{
415 return (r >> 12) & 0x1;
416}
417static inline u32 fifo_engine_status_id_type_chid_v(void)
418{
419 return 0x00000000;
420}
421static inline u32 fifo_engine_status_id_type_tsgid_v(void)
422{
423 return 0x00000001;
424}
425static inline u32 fifo_engine_status_ctx_status_v(u32 r)
426{
427 return (r >> 13) & 0x7;
428}
429static inline u32 fifo_engine_status_ctx_status_valid_v(void)
430{
431 return 0x00000001;
432}
433static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
434{
435 return 0x00000005;
436}
437static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
438{
439 return 0x00000006;
440}
441static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
442{
443 return 0x00000007;
444}
445static inline u32 fifo_engine_status_next_id_v(u32 r)
446{
447 return (r >> 16) & 0xfff;
448}
449static inline u32 fifo_engine_status_next_id_type_v(u32 r)
450{
451 return (r >> 28) & 0x1;
452}
453static inline u32 fifo_engine_status_next_id_type_chid_v(void)
454{
455 return 0x00000000;
456}
457static inline u32 fifo_engine_status_faulted_v(u32 r)
458{
459 return (r >> 30) & 0x1;
460}
461static inline u32 fifo_engine_status_faulted_true_v(void)
462{
463 return 0x00000001;
464}
465static inline u32 fifo_engine_status_engine_v(u32 r)
466{
467 return (r >> 31) & 0x1;
468}
469static inline u32 fifo_engine_status_engine_idle_v(void)
470{
471 return 0x00000000;
472}
473static inline u32 fifo_engine_status_engine_busy_v(void)
474{
475 return 0x00000001;
476}
477static inline u32 fifo_engine_status_ctxsw_v(u32 r)
478{
479 return (r >> 15) & 0x1;
480}
481static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
482{
483 return 0x00000001;
484}
485static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
486{
487 return 0x8000;
488}
489static inline u32 fifo_pbdma_status_r(u32 i)
490{
491 return 0x00003080 + i*4;
492}
493static inline u32 fifo_pbdma_status__size_1_v(void)
494{
495 return 0x00000003;
496}
497static inline u32 fifo_pbdma_status_id_v(u32 r)
498{
499 return (r >> 0) & 0xfff;
500}
501static inline u32 fifo_pbdma_status_id_type_v(u32 r)
502{
503 return (r >> 12) & 0x1;
504}
505static inline u32 fifo_pbdma_status_id_type_chid_v(void)
506{
507 return 0x00000000;
508}
509static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
510{
511 return 0x00000001;
512}
513static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
514{
515 return (r >> 13) & 0x7;
516}
517static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
518{
519 return 0x00000001;
520}
521static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
522{
523 return 0x00000005;
524}
525static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
526{
527 return 0x00000006;
528}
529static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
530{
531 return 0x00000007;
532}
533static inline u32 fifo_pbdma_status_next_id_v(u32 r)
534{
535 return (r >> 16) & 0xfff;
536}
537static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
538{
539 return (r >> 28) & 0x1;
540}
541static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
542{
543 return 0x00000000;
544}
545static inline u32 fifo_pbdma_status_chsw_v(u32 r)
546{
547 return (r >> 15) & 0x1;
548}
549static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
550{
551 return 0x00000001;
552}
553#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_flush_gm206.h b/drivers/gpu/nvgpu/gm206/hw_flush_gm206.h
new file mode 100644
index 00000000..8a37aecb
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_flush_gm206.h
@@ -0,0 +1,181 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_flush_gm206_h_
51#define _hw_flush_gm206_h_
52
53static inline u32 flush_l2_system_invalidate_r(void)
54{
55 return 0x00070004;
56}
57static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
58{
59 return (r >> 0) & 0x1;
60}
61static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
66{
67 return 0x1;
68}
69static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
70{
71 return (r >> 1) & 0x1;
72}
73static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 flush_l2_flush_dirty_r(void)
78{
79 return 0x00070010;
80}
81static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
82{
83 return (r >> 0) & 0x1;
84}
85static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
90{
91 return 0x0;
92}
93static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
94{
95 return 0x00000001;
96}
97static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
98{
99 return 0x1;
100}
101static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
102{
103 return (r >> 1) & 0x1;
104}
105static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
110{
111 return 0x0;
112}
113static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 flush_l2_clean_comptags_r(void)
118{
119 return 0x0007000c;
120}
121static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
122{
123 return (r >> 0) & 0x1;
124}
125static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
126{
127 return 0x00000000;
128}
129static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
130{
131 return 0x0;
132}
133static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
138{
139 return 0x1;
140}
141static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
142{
143 return (r >> 1) & 0x1;
144}
145static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
146{
147 return 0x00000000;
148}
149static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
150{
151 return 0x0;
152}
153static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 flush_fb_flush_r(void)
158{
159 return 0x00070000;
160}
161static inline u32 flush_fb_flush_pending_v(u32 r)
162{
163 return (r >> 0) & 0x1;
164}
165static inline u32 flush_fb_flush_pending_busy_v(void)
166{
167 return 0x00000001;
168}
169static inline u32 flush_fb_flush_pending_busy_f(void)
170{
171 return 0x1;
172}
173static inline u32 flush_fb_flush_outstanding_v(u32 r)
174{
175 return (r >> 1) & 0x1;
176}
177static inline u32 flush_fb_flush_outstanding_true_v(void)
178{
179 return 0x00000001;
180}
181#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_fuse_gm206.h b/drivers/gpu/nvgpu/gm206/hw_fuse_gm206.h
new file mode 100644
index 00000000..f556ccfb
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_fuse_gm206.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fuse_gm206_h_
51#define _hw_fuse_gm206_h_
52
53static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
54{
55 return 0x00021c38 + i*4;
56}
57static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
58{
59 return 0x00021838 + i*4;
60}
61static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
62{
63 return 0x00021944;
64}
65static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
66{
67 return (v & 0x3) << 0;
68}
69static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
70{
71 return 0x3 << 0;
72}
73static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
74{
75 return (r >> 0) & 0x3;
76}
77static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
78{
79 return 0x00021948;
80}
81static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
82{
83 return (v & 0x1) << 0;
84}
85static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
86{
87 return 0x1 << 0;
88}
89static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
90{
91 return (r >> 0) & 0x1;
92}
93static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
94{
95 return 0x1;
96}
97static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
98{
99 return 0x0;
100}
101static inline u32 fuse_status_opt_fbio_r(void)
102{
103 return 0x00021c14;
104}
105static inline u32 fuse_status_opt_fbio_data_f(u32 v)
106{
107 return (v & 0xffff) << 0;
108}
109static inline u32 fuse_status_opt_fbio_data_m(void)
110{
111 return 0xffff << 0;
112}
113static inline u32 fuse_status_opt_fbio_data_v(u32 r)
114{
115 return (r >> 0) & 0xffff;
116}
117static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
118{
119 return 0x00021d70 + i*4;
120}
121static inline u32 fuse_status_opt_fbp_r(void)
122{
123 return 0x00021d38;
124}
125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
126{
127 return (r >> (0 + i*0)) & 0x1;
128}
129#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_gmmu_gm206.h b/drivers/gpu/nvgpu/gm206/hw_gmmu_gm206.h
new file mode 100644
index 00000000..c098de69
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_gmmu_gm206.h
@@ -0,0 +1,1189 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gmmu_gm206_h_
51#define _hw_gmmu_gm206_h_
52
53static inline u32 gmmu_pde_aperture_big_w(void)
54{
55 return 0;
56}
57static inline u32 gmmu_pde_aperture_big_invalid_f(void)
58{
59 return 0x0;
60}
61static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
62{
63 return 0x1;
64}
65static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
66{
67 return 0x2;
68}
69static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
70{
71 return 0x3;
72}
73static inline u32 gmmu_pde_size_w(void)
74{
75 return 0;
76}
77static inline u32 gmmu_pde_size_full_f(void)
78{
79 return 0x0;
80}
81static inline u32 gmmu_pde_address_big_sys_f(u32 v)
82{
83 return (v & 0xfffffff) << 4;
84}
85static inline u32 gmmu_pde_address_big_sys_w(void)
86{
87 return 0;
88}
89static inline u32 gmmu_pde_aperture_small_w(void)
90{
91 return 1;
92}
93static inline u32 gmmu_pde_aperture_small_invalid_f(void)
94{
95 return 0x0;
96}
97static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
98{
99 return 0x1;
100}
101static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
102{
103 return 0x2;
104}
105static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
106{
107 return 0x3;
108}
109static inline u32 gmmu_pde_vol_small_w(void)
110{
111 return 1;
112}
113static inline u32 gmmu_pde_vol_small_true_f(void)
114{
115 return 0x4;
116}
117static inline u32 gmmu_pde_vol_small_false_f(void)
118{
119 return 0x0;
120}
121static inline u32 gmmu_pde_vol_big_w(void)
122{
123 return 1;
124}
125static inline u32 gmmu_pde_vol_big_true_f(void)
126{
127 return 0x8;
128}
129static inline u32 gmmu_pde_vol_big_false_f(void)
130{
131 return 0x0;
132}
133static inline u32 gmmu_pde_address_small_sys_f(u32 v)
134{
135 return (v & 0xfffffff) << 4;
136}
137static inline u32 gmmu_pde_address_small_sys_w(void)
138{
139 return 1;
140}
141static inline u32 gmmu_pde_address_shift_v(void)
142{
143 return 0x0000000c;
144}
145static inline u32 gmmu_pde__size_v(void)
146{
147 return 0x00000008;
148}
149static inline u32 gmmu_pte__size_v(void)
150{
151 return 0x00000008;
152}
153static inline u32 gmmu_pte_valid_w(void)
154{
155 return 0;
156}
157static inline u32 gmmu_pte_valid_true_f(void)
158{
159 return 0x1;
160}
161static inline u32 gmmu_pte_valid_false_f(void)
162{
163 return 0x0;
164}
165static inline u32 gmmu_pte_privilege_w(void)
166{
167 return 0;
168}
169static inline u32 gmmu_pte_privilege_true_f(void)
170{
171 return 0x2;
172}
173static inline u32 gmmu_pte_privilege_false_f(void)
174{
175 return 0x0;
176}
177static inline u32 gmmu_pte_address_sys_f(u32 v)
178{
179 return (v & 0xfffffff) << 4;
180}
181static inline u32 gmmu_pte_address_sys_w(void)
182{
183 return 0;
184}
185static inline u32 gmmu_pte_vol_w(void)
186{
187 return 1;
188}
189static inline u32 gmmu_pte_vol_true_f(void)
190{
191 return 0x1;
192}
193static inline u32 gmmu_pte_vol_false_f(void)
194{
195 return 0x0;
196}
197static inline u32 gmmu_pte_aperture_w(void)
198{
199 return 1;
200}
201static inline u32 gmmu_pte_aperture_video_memory_f(void)
202{
203 return 0x0;
204}
205static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
206{
207 return 0x4;
208}
209static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
210{
211 return 0x6;
212}
213static inline u32 gmmu_pte_read_only_w(void)
214{
215 return 0;
216}
217static inline u32 gmmu_pte_read_only_true_f(void)
218{
219 return 0x4;
220}
221static inline u32 gmmu_pte_write_disable_w(void)
222{
223 return 1;
224}
225static inline u32 gmmu_pte_write_disable_true_f(void)
226{
227 return 0x80000000;
228}
229static inline u32 gmmu_pte_read_disable_w(void)
230{
231 return 1;
232}
233static inline u32 gmmu_pte_read_disable_true_f(void)
234{
235 return 0x40000000;
236}
237static inline u32 gmmu_pte_comptagline_f(u32 v)
238{
239 return (v & 0x1ffff) << 12;
240}
241static inline u32 gmmu_pte_comptagline_w(void)
242{
243 return 1;
244}
245static inline u32 gmmu_pte_address_shift_v(void)
246{
247 return 0x0000000c;
248}
249static inline u32 gmmu_pte_kind_f(u32 v)
250{
251 return (v & 0xff) << 4;
252}
253static inline u32 gmmu_pte_kind_w(void)
254{
255 return 1;
256}
257static inline u32 gmmu_pte_kind_invalid_v(void)
258{
259 return 0x000000ff;
260}
261static inline u32 gmmu_pte_kind_pitch_v(void)
262{
263 return 0x00000000;
264}
265static inline u32 gmmu_pte_kind_z16_v(void)
266{
267 return 0x00000001;
268}
269static inline u32 gmmu_pte_kind_z16_2c_v(void)
270{
271 return 0x00000002;
272}
273static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
274{
275 return 0x00000003;
276}
277static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
278{
279 return 0x00000004;
280}
281static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
282{
283 return 0x00000005;
284}
285static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
286{
287 return 0x00000006;
288}
289static inline u32 gmmu_pte_kind_z16_2z_v(void)
290{
291 return 0x00000007;
292}
293static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
294{
295 return 0x00000008;
296}
297static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
298{
299 return 0x00000009;
300}
301static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
302{
303 return 0x0000000a;
304}
305static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
306{
307 return 0x0000000b;
308}
309static inline u32 gmmu_pte_kind_z16_4cz_v(void)
310{
311 return 0x0000000c;
312}
313static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
314{
315 return 0x0000000d;
316}
317static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
318{
319 return 0x0000000e;
320}
321static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
322{
323 return 0x0000000f;
324}
325static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
326{
327 return 0x00000010;
328}
329static inline u32 gmmu_pte_kind_s8z24_v(void)
330{
331 return 0x00000011;
332}
333static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
334{
335 return 0x00000012;
336}
337static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
338{
339 return 0x00000013;
340}
341static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
342{
343 return 0x00000014;
344}
345static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
346{
347 return 0x00000015;
348}
349static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
350{
351 return 0x00000016;
352}
353static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
354{
355 return 0x00000017;
356}
357static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
358{
359 return 0x00000018;
360}
361static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
362{
363 return 0x00000019;
364}
365static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
366{
367 return 0x0000001a;
368}
369static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
370{
371 return 0x0000001b;
372}
373static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
374{
375 return 0x0000001c;
376}
377static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
378{
379 return 0x0000001d;
380}
381static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
382{
383 return 0x0000001e;
384}
385static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
386{
387 return 0x0000001f;
388}
389static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
390{
391 return 0x00000020;
392}
393static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
394{
395 return 0x00000021;
396}
397static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
398{
399 return 0x00000022;
400}
401static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
402{
403 return 0x00000023;
404}
405static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
406{
407 return 0x00000024;
408}
409static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
410{
411 return 0x00000025;
412}
413static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
414{
415 return 0x00000026;
416}
417static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
418{
419 return 0x00000027;
420}
421static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
422{
423 return 0x00000028;
424}
425static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
426{
427 return 0x00000029;
428}
429static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
430{
431 return 0x0000002e;
432}
433static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
434{
435 return 0x0000002f;
436}
437static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
438{
439 return 0x00000030;
440}
441static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
442{
443 return 0x00000031;
444}
445static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
446{
447 return 0x00000032;
448}
449static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
450{
451 return 0x00000033;
452}
453static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
454{
455 return 0x00000034;
456}
457static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
458{
459 return 0x00000035;
460}
461static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
462{
463 return 0x0000003a;
464}
465static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
466{
467 return 0x0000003b;
468}
469static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
470{
471 return 0x0000003c;
472}
473static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
474{
475 return 0x0000003d;
476}
477static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
478{
479 return 0x0000003e;
480}
481static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
482{
483 return 0x0000003f;
484}
485static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
486{
487 return 0x00000040;
488}
489static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
490{
491 return 0x00000041;
492}
493static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
494{
495 return 0x00000042;
496}
497static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
498{
499 return 0x00000043;
500}
501static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
502{
503 return 0x00000044;
504}
505static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
506{
507 return 0x00000045;
508}
509static inline u32 gmmu_pte_kind_z24s8_v(void)
510{
511 return 0x00000046;
512}
513static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
514{
515 return 0x00000047;
516}
517static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
518{
519 return 0x00000048;
520}
521static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
522{
523 return 0x00000049;
524}
525static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
526{
527 return 0x0000004a;
528}
529static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
530{
531 return 0x0000004b;
532}
533static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
534{
535 return 0x0000004c;
536}
537static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
538{
539 return 0x0000004d;
540}
541static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
542{
543 return 0x0000004e;
544}
545static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
546{
547 return 0x0000004f;
548}
549static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
550{
551 return 0x00000050;
552}
553static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
554{
555 return 0x00000051;
556}
557static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
558{
559 return 0x00000052;
560}
561static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
562{
563 return 0x00000053;
564}
565static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
566{
567 return 0x00000054;
568}
569static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
570{
571 return 0x00000055;
572}
573static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
574{
575 return 0x00000056;
576}
577static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
578{
579 return 0x00000057;
580}
581static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
582{
583 return 0x00000058;
584}
585static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
586{
587 return 0x00000059;
588}
589static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
590{
591 return 0x0000005a;
592}
593static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
594{
595 return 0x0000005b;
596}
597static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
598{
599 return 0x0000005c;
600}
601static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
602{
603 return 0x0000005d;
604}
605static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
606{
607 return 0x0000005e;
608}
609static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
610{
611 return 0x00000063;
612}
613static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
614{
615 return 0x00000064;
616}
617static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
618{
619 return 0x00000065;
620}
621static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
622{
623 return 0x00000066;
624}
625static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
626{
627 return 0x00000067;
628}
629static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
630{
631 return 0x00000068;
632}
633static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
634{
635 return 0x00000069;
636}
637static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
638{
639 return 0x0000006a;
640}
641static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
642{
643 return 0x0000006f;
644}
645static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
646{
647 return 0x00000070;
648}
649static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
650{
651 return 0x00000071;
652}
653static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
654{
655 return 0x00000072;
656}
657static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
658{
659 return 0x00000073;
660}
661static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
662{
663 return 0x00000074;
664}
665static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
666{
667 return 0x00000075;
668}
669static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
670{
671 return 0x00000076;
672}
673static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
674{
675 return 0x00000077;
676}
677static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
678{
679 return 0x00000078;
680}
681static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
682{
683 return 0x00000079;
684}
685static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
686{
687 return 0x0000007a;
688}
689static inline u32 gmmu_pte_kind_zf32_v(void)
690{
691 return 0x0000007b;
692}
693static inline u32 gmmu_pte_kind_zf32_1z_v(void)
694{
695 return 0x0000007c;
696}
697static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
698{
699 return 0x0000007d;
700}
701static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
702{
703 return 0x0000007e;
704}
705static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
706{
707 return 0x0000007f;
708}
709static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
710{
711 return 0x00000080;
712}
713static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
714{
715 return 0x00000081;
716}
717static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
718{
719 return 0x00000082;
720}
721static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
722{
723 return 0x00000083;
724}
725static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
726{
727 return 0x00000084;
728}
729static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
730{
731 return 0x00000085;
732}
733static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
734{
735 return 0x00000086;
736}
737static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
738{
739 return 0x00000087;
740}
741static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
742{
743 return 0x00000088;
744}
745static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
746{
747 return 0x00000089;
748}
749static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
750{
751 return 0x0000008a;
752}
753static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
754{
755 return 0x0000008b;
756}
757static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
758{
759 return 0x0000008c;
760}
761static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
762{
763 return 0x0000008d;
764}
765static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
766{
767 return 0x0000008e;
768}
769static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
770{
771 return 0x0000008f;
772}
773static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
774{
775 return 0x00000090;
776}
777static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
778{
779 return 0x00000091;
780}
781static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
782{
783 return 0x00000092;
784}
785static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
786{
787 return 0x00000097;
788}
789static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
790{
791 return 0x00000098;
792}
793static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
794{
795 return 0x00000099;
796}
797static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
798{
799 return 0x0000009a;
800}
801static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
802{
803 return 0x0000009b;
804}
805static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
806{
807 return 0x0000009c;
808}
809static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
810{
811 return 0x0000009d;
812}
813static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
814{
815 return 0x0000009e;
816}
817static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
818{
819 return 0x0000009f;
820}
821static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
822{
823 return 0x000000a0;
824}
825static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
826{
827 return 0x000000a1;
828}
829static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
830{
831 return 0x000000a2;
832}
833static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
834{
835 return 0x000000a3;
836}
837static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
838{
839 return 0x000000a4;
840}
841static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
842{
843 return 0x000000a5;
844}
845static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
846{
847 return 0x000000a6;
848}
849static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
850{
851 return 0x000000a7;
852}
853static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
854{
855 return 0x000000a8;
856}
857static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
858{
859 return 0x000000a9;
860}
861static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
862{
863 return 0x000000aa;
864}
865static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
866{
867 return 0x000000ab;
868}
869static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
870{
871 return 0x000000ac;
872}
873static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
874{
875 return 0x000000ad;
876}
877static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
878{
879 return 0x000000ae;
880}
881static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
882{
883 return 0x000000b3;
884}
885static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
886{
887 return 0x000000b4;
888}
889static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
890{
891 return 0x000000b5;
892}
893static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
894{
895 return 0x000000b6;
896}
897static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
898{
899 return 0x000000b7;
900}
901static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
902{
903 return 0x000000b8;
904}
905static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
906{
907 return 0x000000b9;
908}
909static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
910{
911 return 0x000000ba;
912}
913static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
914{
915 return 0x000000bb;
916}
917static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
918{
919 return 0x000000bc;
920}
921static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
922{
923 return 0x000000bd;
924}
925static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
926{
927 return 0x000000be;
928}
929static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
930{
931 return 0x000000bf;
932}
933static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
934{
935 return 0x000000c0;
936}
937static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
938{
939 return 0x000000c1;
940}
941static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
942{
943 return 0x000000c2;
944}
945static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
946{
947 return 0x000000c3;
948}
949static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
950{
951 return 0x000000c4;
952}
953static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
954{
955 return 0x000000c5;
956}
957static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
958{
959 return 0x000000c6;
960}
961static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
962{
963 return 0x000000c7;
964}
965static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
966{
967 return 0x000000c8;
968}
969static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
970{
971 return 0x000000ce;
972}
973static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
974{
975 return 0x000000cf;
976}
977static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
978{
979 return 0x000000d0;
980}
981static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
982{
983 return 0x000000d1;
984}
985static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
986{
987 return 0x000000d2;
988}
989static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
990{
991 return 0x000000d3;
992}
993static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
994{
995 return 0x000000d4;
996}
997static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
998{
999 return 0x000000d5;
1000}
1001static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1002{
1003 return 0x000000d6;
1004}
1005static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1006{
1007 return 0x000000d7;
1008}
1009static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1010{
1011 return 0x000000fe;
1012}
1013static inline u32 gmmu_pte_kind_c32_2c_v(void)
1014{
1015 return 0x000000d8;
1016}
1017static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1018{
1019 return 0x000000d9;
1020}
1021static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1022{
1023 return 0x000000da;
1024}
1025static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1026{
1027 return 0x000000db;
1028}
1029static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1030{
1031 return 0x000000dc;
1032}
1033static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1034{
1035 return 0x000000dd;
1036}
1037static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1038{
1039 return 0x000000de;
1040}
1041static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
1042{
1043 return 0x000000cc;
1044}
1045static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1046{
1047 return 0x000000df;
1048}
1049static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1050{
1051 return 0x000000e0;
1052}
1053static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1054{
1055 return 0x000000e1;
1056}
1057static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1058{
1059 return 0x000000e2;
1060}
1061static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1062{
1063 return 0x000000e3;
1064}
1065static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1066{
1067 return 0x000000e4;
1068}
1069static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1070{
1071 return 0x000000e5;
1072}
1073static inline u32 gmmu_pte_kind_c64_2c_v(void)
1074{
1075 return 0x000000e6;
1076}
1077static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1078{
1079 return 0x000000e7;
1080}
1081static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1082{
1083 return 0x000000e8;
1084}
1085static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1086{
1087 return 0x000000e9;
1088}
1089static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1090{
1091 return 0x000000ea;
1092}
1093static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1094{
1095 return 0x000000eb;
1096}
1097static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1098{
1099 return 0x000000ec;
1100}
1101static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
1102{
1103 return 0x000000cd;
1104}
1105static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1106{
1107 return 0x000000ed;
1108}
1109static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1110{
1111 return 0x000000ee;
1112}
1113static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1114{
1115 return 0x000000ef;
1116}
1117static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1118{
1119 return 0x000000f0;
1120}
1121static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1122{
1123 return 0x000000f1;
1124}
1125static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1126{
1127 return 0x000000f2;
1128}
1129static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1130{
1131 return 0x000000f3;
1132}
1133static inline u32 gmmu_pte_kind_c128_2c_v(void)
1134{
1135 return 0x000000f4;
1136}
1137static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1138{
1139 return 0x000000f5;
1140}
1141static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1142{
1143 return 0x000000f6;
1144}
1145static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1146{
1147 return 0x000000f7;
1148}
1149static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1150{
1151 return 0x000000f8;
1152}
1153static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1154{
1155 return 0x000000f9;
1156}
1157static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1158{
1159 return 0x000000fa;
1160}
1161static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1162{
1163 return 0x000000fb;
1164}
1165static inline u32 gmmu_pte_kind_x8c24_v(void)
1166{
1167 return 0x000000fc;
1168}
1169static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1170{
1171 return 0x000000fd;
1172}
1173static inline u32 gmmu_pte_kind_smsked_message_v(void)
1174{
1175 return 0x000000ca;
1176}
1177static inline u32 gmmu_pte_kind_smhost_message_v(void)
1178{
1179 return 0x000000cb;
1180}
1181static inline u32 gmmu_pte_kind_s8_v(void)
1182{
1183 return 0x0000002a;
1184}
1185static inline u32 gmmu_pte_kind_s8_2s_v(void)
1186{
1187 return 0x0000002b;
1188}
1189#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_gr_gm206.h b/drivers/gpu/nvgpu/gm206/hw_gr_gm206.h
new file mode 100644
index 00000000..011e3142
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_gr_gm206.h
@@ -0,0 +1,3681 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gr_gm206_h_
51#define _hw_gr_gm206_h_
52
53static inline u32 gr_intr_r(void)
54{
55 return 0x00400100;
56}
57static inline u32 gr_intr_notify_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 gr_intr_notify_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 gr_intr_semaphore_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 gr_intr_semaphore_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 gr_intr_illegal_method_pending_f(void)
74{
75 return 0x10;
76}
77static inline u32 gr_intr_illegal_method_reset_f(void)
78{
79 return 0x10;
80}
81static inline u32 gr_intr_illegal_notify_pending_f(void)
82{
83 return 0x40;
84}
85static inline u32 gr_intr_illegal_notify_reset_f(void)
86{
87 return 0x40;
88}
89static inline u32 gr_intr_firmware_method_f(u32 v)
90{
91 return (v & 0x1) << 8;
92}
93static inline u32 gr_intr_firmware_method_pending_f(void)
94{
95 return 0x100;
96}
97static inline u32 gr_intr_firmware_method_reset_f(void)
98{
99 return 0x100;
100}
101static inline u32 gr_intr_illegal_class_pending_f(void)
102{
103 return 0x20;
104}
105static inline u32 gr_intr_illegal_class_reset_f(void)
106{
107 return 0x20;
108}
109static inline u32 gr_intr_fecs_error_pending_f(void)
110{
111 return 0x80000;
112}
113static inline u32 gr_intr_fecs_error_reset_f(void)
114{
115 return 0x80000;
116}
117static inline u32 gr_intr_class_error_pending_f(void)
118{
119 return 0x100000;
120}
121static inline u32 gr_intr_class_error_reset_f(void)
122{
123 return 0x100000;
124}
125static inline u32 gr_intr_exception_pending_f(void)
126{
127 return 0x200000;
128}
129static inline u32 gr_intr_exception_reset_f(void)
130{
131 return 0x200000;
132}
133static inline u32 gr_fecs_intr_r(void)
134{
135 return 0x00400144;
136}
137static inline u32 gr_class_error_r(void)
138{
139 return 0x00400110;
140}
141static inline u32 gr_class_error_code_v(u32 r)
142{
143 return (r >> 0) & 0xffff;
144}
145static inline u32 gr_intr_nonstall_r(void)
146{
147 return 0x00400120;
148}
149static inline u32 gr_intr_nonstall_trap_pending_f(void)
150{
151 return 0x2;
152}
153static inline u32 gr_intr_en_r(void)
154{
155 return 0x0040013c;
156}
157static inline u32 gr_exception_r(void)
158{
159 return 0x00400108;
160}
161static inline u32 gr_exception_fe_m(void)
162{
163 return 0x1 << 0;
164}
165static inline u32 gr_exception_gpc_m(void)
166{
167 return 0x1 << 24;
168}
169static inline u32 gr_exception_memfmt_m(void)
170{
171 return 0x1 << 1;
172}
173static inline u32 gr_exception_ds_m(void)
174{
175 return 0x1 << 4;
176}
177static inline u32 gr_exception1_r(void)
178{
179 return 0x00400118;
180}
181static inline u32 gr_exception1_gpc_0_pending_f(void)
182{
183 return 0x1;
184}
185static inline u32 gr_exception2_r(void)
186{
187 return 0x0040011c;
188}
189static inline u32 gr_exception_en_r(void)
190{
191 return 0x00400138;
192}
193static inline u32 gr_exception_en_fe_m(void)
194{
195 return 0x1 << 0;
196}
197static inline u32 gr_exception1_en_r(void)
198{
199 return 0x00400130;
200}
201static inline u32 gr_exception2_en_r(void)
202{
203 return 0x00400134;
204}
205static inline u32 gr_gpfifo_ctl_r(void)
206{
207 return 0x00400500;
208}
209static inline u32 gr_gpfifo_ctl_access_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
214{
215 return 0x0;
216}
217static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
218{
219 return 0x1;
220}
221static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
222{
223 return (v & 0x1) << 16;
224}
225static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
226{
227 return 0x00000001;
228}
229static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
230{
231 return 0x10000;
232}
233static inline u32 gr_gpfifo_status_r(void)
234{
235 return 0x00400504;
236}
237static inline u32 gr_trapped_addr_r(void)
238{
239 return 0x00400704;
240}
241static inline u32 gr_trapped_addr_mthd_v(u32 r)
242{
243 return (r >> 2) & 0xfff;
244}
245static inline u32 gr_trapped_addr_subch_v(u32 r)
246{
247 return (r >> 16) & 0x7;
248}
249static inline u32 gr_trapped_data_lo_r(void)
250{
251 return 0x00400708;
252}
253static inline u32 gr_trapped_data_hi_r(void)
254{
255 return 0x0040070c;
256}
257static inline u32 gr_status_r(void)
258{
259 return 0x00400700;
260}
261static inline u32 gr_status_fe_method_upper_v(u32 r)
262{
263 return (r >> 1) & 0x1;
264}
265static inline u32 gr_status_fe_method_lower_v(u32 r)
266{
267 return (r >> 2) & 0x1;
268}
269static inline u32 gr_status_fe_method_lower_idle_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 gr_status_fe_gi_v(u32 r)
274{
275 return (r >> 21) & 0x1;
276}
277static inline u32 gr_status_mask_r(void)
278{
279 return 0x00400610;
280}
281static inline u32 gr_status_1_r(void)
282{
283 return 0x00400604;
284}
285static inline u32 gr_status_2_r(void)
286{
287 return 0x00400608;
288}
289static inline u32 gr_engine_status_r(void)
290{
291 return 0x0040060c;
292}
293static inline u32 gr_engine_status_value_busy_f(void)
294{
295 return 0x1;
296}
297static inline u32 gr_pri_be0_becs_be_exception_r(void)
298{
299 return 0x00410204;
300}
301static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
302{
303 return 0x00410208;
304}
305static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
306{
307 return 0x00502c90;
308}
309static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
310{
311 return 0x00502c94;
312}
313static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
314{
315 return 0x00504508;
316}
317static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
318{
319 return 0x0050450c;
320}
321static inline u32 gr_activity_0_r(void)
322{
323 return 0x00400380;
324}
325static inline u32 gr_activity_1_r(void)
326{
327 return 0x00400384;
328}
329static inline u32 gr_activity_2_r(void)
330{
331 return 0x00400388;
332}
333static inline u32 gr_activity_4_r(void)
334{
335 return 0x00400390;
336}
337static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
338{
339 return 0x00501000;
340}
341static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
342{
343 return 0x00419000;
344}
345static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
346{
347 return 0x1 << 1;
348}
349static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
350{
351 return 0x005046a4;
352}
353static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
354{
355 return 0x00419ea4;
356}
357static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
358{
359 return 0x1 << 0;
360}
361static inline u32 gr_pri_sked_activity_r(void)
362{
363 return 0x00407054;
364}
365static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
366{
367 return 0x00502c80;
368}
369static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
370{
371 return 0x00502c84;
372}
373static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
374{
375 return 0x00502c88;
376}
377static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
378{
379 return 0x00502c8c;
380}
381static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
382{
383 return 0x00504500;
384}
385static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
386{
387 return 0x00504d00;
388}
389static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
390{
391 return 0x00501d00;
392}
393static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
394{
395 return 0x0041ac80;
396}
397static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
398{
399 return 0x0041ac84;
400}
401static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
402{
403 return 0x0041ac88;
404}
405static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
406{
407 return 0x0041ac8c;
408}
409static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
410{
411 return 0x0041c500;
412}
413static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
414{
415 return 0x0041cd00;
416}
417static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
418{
419 return 0x00419d00;
420}
421static inline u32 gr_pri_be0_becs_be_activity0_r(void)
422{
423 return 0x00410200;
424}
425static inline u32 gr_pri_be1_becs_be_activity0_r(void)
426{
427 return 0x00410600;
428}
429static inline u32 gr_pri_bes_becs_be_activity0_r(void)
430{
431 return 0x00408a00;
432}
433static inline u32 gr_pri_ds_mpipe_status_r(void)
434{
435 return 0x00405858;
436}
437static inline u32 gr_pri_fe_go_idle_on_status_r(void)
438{
439 return 0x00404150;
440}
441static inline u32 gr_pri_fe_go_idle_check_r(void)
442{
443 return 0x00404158;
444}
445static inline u32 gr_pri_fe_go_idle_info_r(void)
446{
447 return 0x00404194;
448}
449static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
450{
451 return 0x00504238;
452}
453static inline u32 gr_pri_be0_crop_status1_r(void)
454{
455 return 0x00410134;
456}
457static inline u32 gr_pri_bes_crop_status1_r(void)
458{
459 return 0x00408934;
460}
461static inline u32 gr_pri_be0_zrop_status_r(void)
462{
463 return 0x00410048;
464}
465static inline u32 gr_pri_be0_zrop_status2_r(void)
466{
467 return 0x0041004c;
468}
469static inline u32 gr_pri_bes_zrop_status_r(void)
470{
471 return 0x00408848;
472}
473static inline u32 gr_pri_bes_zrop_status2_r(void)
474{
475 return 0x0040884c;
476}
477static inline u32 gr_pipe_bundle_address_r(void)
478{
479 return 0x00400200;
480}
481static inline u32 gr_pipe_bundle_address_value_v(u32 r)
482{
483 return (r >> 0) & 0xffff;
484}
485static inline u32 gr_pipe_bundle_data_r(void)
486{
487 return 0x00400204;
488}
489static inline u32 gr_pipe_bundle_config_r(void)
490{
491 return 0x00400208;
492}
493static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
494{
495 return 0x0;
496}
497static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
498{
499 return 0x80000000;
500}
501static inline u32 gr_fe_hww_esr_r(void)
502{
503 return 0x00404000;
504}
505static inline u32 gr_fe_hww_esr_reset_active_f(void)
506{
507 return 0x40000000;
508}
509static inline u32 gr_fe_hww_esr_en_enable_f(void)
510{
511 return 0x80000000;
512}
513static inline u32 gr_fe_go_idle_timeout_r(void)
514{
515 return 0x00404154;
516}
517static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
518{
519 return (v & 0xffffffff) << 0;
520}
521static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
522{
523 return 0x0;
524}
525static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
526{
527 return 0x800;
528}
529static inline u32 gr_fe_object_table_r(u32 i)
530{
531 return 0x00404200 + i*4;
532}
533static inline u32 gr_fe_object_table_nvclass_v(u32 r)
534{
535 return (r >> 0) & 0xffff;
536}
537static inline u32 gr_fe_tpc_fs_r(void)
538{
539 return 0x004041c4;
540}
541static inline u32 gr_pri_mme_shadow_raw_index_r(void)
542{
543 return 0x00404488;
544}
545static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
546{
547 return 0x80000000;
548}
549static inline u32 gr_pri_mme_shadow_raw_data_r(void)
550{
551 return 0x0040448c;
552}
553static inline u32 gr_mme_hww_esr_r(void)
554{
555 return 0x00404490;
556}
557static inline u32 gr_mme_hww_esr_reset_active_f(void)
558{
559 return 0x40000000;
560}
561static inline u32 gr_mme_hww_esr_en_enable_f(void)
562{
563 return 0x80000000;
564}
565static inline u32 gr_memfmt_hww_esr_r(void)
566{
567 return 0x00404600;
568}
569static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
570{
571 return 0x40000000;
572}
573static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
574{
575 return 0x80000000;
576}
577static inline u32 gr_fecs_cpuctl_r(void)
578{
579 return 0x00409100;
580}
581static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
582{
583 return (v & 0x1) << 1;
584}
585static inline u32 gr_fecs_cpuctl_alias_r(void)
586{
587 return 0x00409130;
588}
589static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
590{
591 return (v & 0x1) << 1;
592}
593static inline u32 gr_fecs_dmactl_r(void)
594{
595 return 0x0040910c;
596}
597static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
598{
599 return (v & 0x1) << 0;
600}
601static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
602{
603 return 0x1 << 1;
604}
605static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
606{
607 return 0x1 << 2;
608}
609static inline u32 gr_fecs_os_r(void)
610{
611 return 0x00409080;
612}
613static inline u32 gr_fecs_idlestate_r(void)
614{
615 return 0x0040904c;
616}
617static inline u32 gr_fecs_mailbox0_r(void)
618{
619 return 0x00409040;
620}
621static inline u32 gr_fecs_mailbox1_r(void)
622{
623 return 0x00409044;
624}
625static inline u32 gr_fecs_irqstat_r(void)
626{
627 return 0x00409008;
628}
629static inline u32 gr_fecs_irqmode_r(void)
630{
631 return 0x0040900c;
632}
633static inline u32 gr_fecs_irqmask_r(void)
634{
635 return 0x00409018;
636}
637static inline u32 gr_fecs_irqdest_r(void)
638{
639 return 0x0040901c;
640}
641static inline u32 gr_fecs_curctx_r(void)
642{
643 return 0x00409050;
644}
645static inline u32 gr_fecs_nxtctx_r(void)
646{
647 return 0x00409054;
648}
649static inline u32 gr_fecs_engctl_r(void)
650{
651 return 0x004090a4;
652}
653static inline u32 gr_fecs_debug1_r(void)
654{
655 return 0x00409090;
656}
657static inline u32 gr_fecs_debuginfo_r(void)
658{
659 return 0x00409094;
660}
661static inline u32 gr_fecs_icd_cmd_r(void)
662{
663 return 0x00409200;
664}
665static inline u32 gr_fecs_icd_cmd_opc_s(void)
666{
667 return 4;
668}
669static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
670{
671 return (v & 0xf) << 0;
672}
673static inline u32 gr_fecs_icd_cmd_opc_m(void)
674{
675 return 0xf << 0;
676}
677static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
678{
679 return (r >> 0) & 0xf;
680}
681static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
682{
683 return 0x8;
684}
685static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
686{
687 return 0xe;
688}
689static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
690{
691 return (v & 0x1f) << 8;
692}
693static inline u32 gr_fecs_icd_rdata_r(void)
694{
695 return 0x0040920c;
696}
697static inline u32 gr_fecs_imemc_r(u32 i)
698{
699 return 0x00409180 + i*16;
700}
701static inline u32 gr_fecs_imemc_offs_f(u32 v)
702{
703 return (v & 0x3f) << 2;
704}
705static inline u32 gr_fecs_imemc_blk_f(u32 v)
706{
707 return (v & 0xff) << 8;
708}
709static inline u32 gr_fecs_imemc_aincw_f(u32 v)
710{
711 return (v & 0x1) << 24;
712}
713static inline u32 gr_fecs_imemd_r(u32 i)
714{
715 return 0x00409184 + i*16;
716}
717static inline u32 gr_fecs_imemt_r(u32 i)
718{
719 return 0x00409188 + i*16;
720}
721static inline u32 gr_fecs_imemt_tag_f(u32 v)
722{
723 return (v & 0xffff) << 0;
724}
725static inline u32 gr_fecs_dmemc_r(u32 i)
726{
727 return 0x004091c0 + i*8;
728}
729static inline u32 gr_fecs_dmemc_offs_s(void)
730{
731 return 6;
732}
733static inline u32 gr_fecs_dmemc_offs_f(u32 v)
734{
735 return (v & 0x3f) << 2;
736}
737static inline u32 gr_fecs_dmemc_offs_m(void)
738{
739 return 0x3f << 2;
740}
741static inline u32 gr_fecs_dmemc_offs_v(u32 r)
742{
743 return (r >> 2) & 0x3f;
744}
745static inline u32 gr_fecs_dmemc_blk_f(u32 v)
746{
747 return (v & 0xff) << 8;
748}
749static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
750{
751 return (v & 0x1) << 24;
752}
753static inline u32 gr_fecs_dmemd_r(u32 i)
754{
755 return 0x004091c4 + i*8;
756}
757static inline u32 gr_fecs_dmatrfbase_r(void)
758{
759 return 0x00409110;
760}
761static inline u32 gr_fecs_dmatrfmoffs_r(void)
762{
763 return 0x00409114;
764}
765static inline u32 gr_fecs_dmatrffboffs_r(void)
766{
767 return 0x0040911c;
768}
769static inline u32 gr_fecs_dmatrfcmd_r(void)
770{
771 return 0x00409118;
772}
773static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
774{
775 return (v & 0x1) << 4;
776}
777static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
778{
779 return (v & 0x1) << 5;
780}
781static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
782{
783 return (v & 0x7) << 8;
784}
785static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
786{
787 return (v & 0x7) << 12;
788}
789static inline u32 gr_fecs_bootvec_r(void)
790{
791 return 0x00409104;
792}
793static inline u32 gr_fecs_bootvec_vec_f(u32 v)
794{
795 return (v & 0xffffffff) << 0;
796}
797static inline u32 gr_fecs_falcon_hwcfg_r(void)
798{
799 return 0x00409108;
800}
801static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
802{
803 return 0x0041a108;
804}
805static inline u32 gr_fecs_falcon_rm_r(void)
806{
807 return 0x00409084;
808}
809static inline u32 gr_fecs_current_ctx_r(void)
810{
811 return 0x00409b00;
812}
813static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
814{
815 return (v & 0xfffffff) << 0;
816}
817static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
818{
819 return (r >> 0) & 0xfffffff;
820}
821static inline u32 gr_fecs_current_ctx_target_s(void)
822{
823 return 2;
824}
825static inline u32 gr_fecs_current_ctx_target_f(u32 v)
826{
827 return (v & 0x3) << 28;
828}
829static inline u32 gr_fecs_current_ctx_target_m(void)
830{
831 return 0x3 << 28;
832}
833static inline u32 gr_fecs_current_ctx_target_v(u32 r)
834{
835 return (r >> 28) & 0x3;
836}
837static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
838{
839 return 0x0;
840}
841static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
842{
843 return 0x20000000;
844}
845static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
846{
847 return 0x30000000;
848}
849static inline u32 gr_fecs_current_ctx_valid_s(void)
850{
851 return 1;
852}
853static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
854{
855 return (v & 0x1) << 31;
856}
857static inline u32 gr_fecs_current_ctx_valid_m(void)
858{
859 return 0x1 << 31;
860}
861static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
862{
863 return (r >> 31) & 0x1;
864}
865static inline u32 gr_fecs_current_ctx_valid_false_f(void)
866{
867 return 0x0;
868}
869static inline u32 gr_fecs_method_data_r(void)
870{
871 return 0x00409500;
872}
873static inline u32 gr_fecs_method_push_r(void)
874{
875 return 0x00409504;
876}
877static inline u32 gr_fecs_method_push_adr_f(u32 v)
878{
879 return (v & 0xfff) << 0;
880}
881static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
882{
883 return 0x00000003;
884}
885static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
886{
887 return 0x3;
888}
889static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
890{
891 return 0x00000010;
892}
893static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
894{
895 return 0x00000009;
896}
897static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
898{
899 return 0x00000015;
900}
901static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
902{
903 return 0x00000016;
904}
905static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
906{
907 return 0x00000025;
908}
909static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
910{
911 return 0x00000030;
912}
913static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
914{
915 return 0x00000031;
916}
917static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
918{
919 return 0x00000032;
920}
921static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
922{
923 return 0x00000038;
924}
925static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
926{
927 return 0x00000039;
928}
929static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
930{
931 return 0x21;
932}
933static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
934{
935 return 0x00000004;
936}
937static inline u32 gr_fecs_host_int_status_r(void)
938{
939 return 0x00409c18;
940}
941static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
942{
943 return (v & 0x1) << 16;
944}
945static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
946{
947 return (v & 0x1) << 17;
948}
949static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
950{
951 return (v & 0x1) << 18;
952}
953static inline u32 gr_fecs_host_int_clear_r(void)
954{
955 return 0x00409c20;
956}
957static inline u32 gr_fecs_host_int_enable_r(void)
958{
959 return 0x00409c24;
960}
961static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
962{
963 return 0x10000;
964}
965static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
966{
967 return 0x20000;
968}
969static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
970{
971 return 0x40000;
972}
973static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
974{
975 return 0x80000;
976}
977static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
978{
979 return 0x00409614;
980}
981static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
982{
983 return 0x0;
984}
985static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
986{
987 return 0x0;
988}
989static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
990{
991 return 0x0;
992}
993static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
994{
995 return 0x10;
996}
997static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
998{
999 return 0x20;
1000}
1001static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1002{
1003 return 0x40;
1004}
1005static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1006{
1007 return 0x0;
1008}
1009static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1010{
1011 return 0x100;
1012}
1013static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1014{
1015 return 0x0;
1016}
1017static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1018{
1019 return 0x200;
1020}
1021static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1022{
1023 return 1;
1024}
1025static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1026{
1027 return (v & 0x1) << 10;
1028}
1029static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1030{
1031 return 0x1 << 10;
1032}
1033static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1034{
1035 return (r >> 10) & 0x1;
1036}
1037static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1038{
1039 return 0x0;
1040}
1041static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1042{
1043 return 0x400;
1044}
1045static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1046{
1047 return 0x0040960c;
1048}
1049static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1050{
1051 return 0x00409800 + i*4;
1052}
1053static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1054{
1055 return 0x00000010;
1056}
1057static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1058{
1059 return (v & 0xffffffff) << 0;
1060}
1061static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1062{
1063 return 0x00000001;
1064}
1065static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1066{
1067 return 0x00000002;
1068}
1069static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1070{
1071 return 0x004098c0 + i*4;
1072}
1073static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1074{
1075 return (v & 0xffffffff) << 0;
1076}
1077static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1078{
1079 return 0x00409840 + i*4;
1080}
1081static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1082{
1083 return (v & 0xffffffff) << 0;
1084}
1085static inline u32 gr_fecs_fs_r(void)
1086{
1087 return 0x00409604;
1088}
1089static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1090{
1091 return 5;
1092}
1093static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1094{
1095 return (v & 0x1f) << 0;
1096}
1097static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1098{
1099 return 0x1f << 0;
1100}
1101static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1102{
1103 return (r >> 0) & 0x1f;
1104}
1105static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1106{
1107 return 5;
1108}
1109static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1110{
1111 return (v & 0x1f) << 16;
1112}
1113static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1114{
1115 return 0x1f << 16;
1116}
1117static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1118{
1119 return (r >> 16) & 0x1f;
1120}
1121static inline u32 gr_fecs_cfg_r(void)
1122{
1123 return 0x00409620;
1124}
1125static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1126{
1127 return (r >> 0) & 0xff;
1128}
1129static inline u32 gr_fecs_rc_lanes_r(void)
1130{
1131 return 0x00409880;
1132}
1133static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1134{
1135 return 6;
1136}
1137static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1138{
1139 return (v & 0x3f) << 0;
1140}
1141static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1142{
1143 return 0x3f << 0;
1144}
1145static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1146{
1147 return (r >> 0) & 0x3f;
1148}
1149static inline u32 gr_fecs_ctxsw_status_1_r(void)
1150{
1151 return 0x00409400;
1152}
1153static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1154{
1155 return 1;
1156}
1157static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1158{
1159 return (v & 0x1) << 12;
1160}
1161static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1162{
1163 return 0x1 << 12;
1164}
1165static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1166{
1167 return (r >> 12) & 0x1;
1168}
1169static inline u32 gr_fecs_arb_ctx_adr_r(void)
1170{
1171 return 0x00409a24;
1172}
1173static inline u32 gr_fecs_new_ctx_r(void)
1174{
1175 return 0x00409b04;
1176}
1177static inline u32 gr_fecs_new_ctx_ptr_s(void)
1178{
1179 return 28;
1180}
1181static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1182{
1183 return (v & 0xfffffff) << 0;
1184}
1185static inline u32 gr_fecs_new_ctx_ptr_m(void)
1186{
1187 return 0xfffffff << 0;
1188}
1189static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1190{
1191 return (r >> 0) & 0xfffffff;
1192}
1193static inline u32 gr_fecs_new_ctx_target_s(void)
1194{
1195 return 2;
1196}
1197static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1198{
1199 return (v & 0x3) << 28;
1200}
1201static inline u32 gr_fecs_new_ctx_target_m(void)
1202{
1203 return 0x3 << 28;
1204}
1205static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1206{
1207 return (r >> 28) & 0x3;
1208}
1209static inline u32 gr_fecs_new_ctx_valid_s(void)
1210{
1211 return 1;
1212}
1213static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1214{
1215 return (v & 0x1) << 31;
1216}
1217static inline u32 gr_fecs_new_ctx_valid_m(void)
1218{
1219 return 0x1 << 31;
1220}
1221static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1222{
1223 return (r >> 31) & 0x1;
1224}
1225static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1226{
1227 return 0x00409a0c;
1228}
1229static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1230{
1231 return 28;
1232}
1233static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1234{
1235 return (v & 0xfffffff) << 0;
1236}
1237static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1238{
1239 return 0xfffffff << 0;
1240}
1241static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1242{
1243 return (r >> 0) & 0xfffffff;
1244}
1245static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1246{
1247 return 2;
1248}
1249static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1250{
1251 return (v & 0x3) << 28;
1252}
1253static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1254{
1255 return 0x3 << 28;
1256}
1257static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1258{
1259 return (r >> 28) & 0x3;
1260}
1261static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1262{
1263 return 0x00409a10;
1264}
1265static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1266{
1267 return 5;
1268}
1269static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1270{
1271 return (v & 0x1f) << 0;
1272}
1273static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1274{
1275 return 0x1f << 0;
1276}
1277static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1278{
1279 return (r >> 0) & 0x1f;
1280}
1281static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1282{
1283 return 0x00409c00;
1284}
1285static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1286{
1287 return 0x00502c04;
1288}
1289static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1290{
1291 return 0x00502400;
1292}
1293static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1294{
1295 return 0x00409420;
1296}
1297static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1298{
1299 return 0x00502420;
1300}
1301static inline u32 gr_rstr2d_gpc_map0_r(void)
1302{
1303 return 0x0040780c;
1304}
1305static inline u32 gr_rstr2d_gpc_map1_r(void)
1306{
1307 return 0x00407810;
1308}
1309static inline u32 gr_rstr2d_gpc_map2_r(void)
1310{
1311 return 0x00407814;
1312}
1313static inline u32 gr_rstr2d_gpc_map3_r(void)
1314{
1315 return 0x00407818;
1316}
1317static inline u32 gr_rstr2d_gpc_map4_r(void)
1318{
1319 return 0x0040781c;
1320}
1321static inline u32 gr_rstr2d_gpc_map5_r(void)
1322{
1323 return 0x00407820;
1324}
1325static inline u32 gr_rstr2d_map_table_cfg_r(void)
1326{
1327 return 0x004078bc;
1328}
1329static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1330{
1331 return (v & 0xff) << 0;
1332}
1333static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1334{
1335 return (v & 0xff) << 8;
1336}
1337static inline u32 gr_pd_hww_esr_r(void)
1338{
1339 return 0x00406018;
1340}
1341static inline u32 gr_pd_hww_esr_reset_active_f(void)
1342{
1343 return 0x40000000;
1344}
1345static inline u32 gr_pd_hww_esr_en_enable_f(void)
1346{
1347 return 0x80000000;
1348}
1349static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1350{
1351 return 0x00406028 + i*4;
1352}
1353static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1354{
1355 return 0x00000004;
1356}
1357static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1358{
1359 return (v & 0xf) << 0;
1360}
1361static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1362{
1363 return (v & 0xf) << 4;
1364}
1365static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1366{
1367 return (v & 0xf) << 8;
1368}
1369static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1370{
1371 return (v & 0xf) << 12;
1372}
1373static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1374{
1375 return (v & 0xf) << 16;
1376}
1377static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1378{
1379 return (v & 0xf) << 20;
1380}
1381static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1382{
1383 return (v & 0xf) << 24;
1384}
1385static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1386{
1387 return (v & 0xf) << 28;
1388}
1389static inline u32 gr_pd_ab_dist_cfg0_r(void)
1390{
1391 return 0x004064c0;
1392}
1393static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1394{
1395 return 0x80000000;
1396}
1397static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1398{
1399 return 0x0;
1400}
1401static inline u32 gr_pd_ab_dist_cfg1_r(void)
1402{
1403 return 0x004064c4;
1404}
1405static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1406{
1407 return 0xffff;
1408}
1409static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1410{
1411 return (v & 0xffff) << 16;
1412}
1413static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1414{
1415 return 0x00000080;
1416}
1417static inline u32 gr_pd_ab_dist_cfg2_r(void)
1418{
1419 return 0x004064c8;
1420}
1421static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1422{
1423 return (v & 0xfff) << 0;
1424}
1425static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1426{
1427 return 0x00000780;
1428}
1429static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1430{
1431 return (v & 0xfff) << 16;
1432}
1433static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1434{
1435 return 0x00000020;
1436}
1437static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1438{
1439 return 0x00000780;
1440}
1441static inline u32 gr_pd_pagepool_r(void)
1442{
1443 return 0x004064cc;
1444}
1445static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
1446{
1447 return (v & 0xff) << 0;
1448}
1449static inline u32 gr_pd_pagepool_valid_true_f(void)
1450{
1451 return 0x80000000;
1452}
1453static inline u32 gr_pd_dist_skip_table_r(u32 i)
1454{
1455 return 0x004064d0 + i*4;
1456}
1457static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1458{
1459 return 0x00000008;
1460}
1461static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1462{
1463 return (v & 0xff) << 0;
1464}
1465static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1466{
1467 return (v & 0xff) << 8;
1468}
1469static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1470{
1471 return (v & 0xff) << 16;
1472}
1473static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1474{
1475 return (v & 0xff) << 24;
1476}
1477static inline u32 gr_ds_debug_r(void)
1478{
1479 return 0x00405800;
1480}
1481static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1482{
1483 return 0x0;
1484}
1485static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1486{
1487 return 0x8000000;
1488}
1489static inline u32 gr_ds_zbc_color_r_r(void)
1490{
1491 return 0x00405804;
1492}
1493static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1494{
1495 return (v & 0xffffffff) << 0;
1496}
1497static inline u32 gr_ds_zbc_color_g_r(void)
1498{
1499 return 0x00405808;
1500}
1501static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1502{
1503 return (v & 0xffffffff) << 0;
1504}
1505static inline u32 gr_ds_zbc_color_b_r(void)
1506{
1507 return 0x0040580c;
1508}
1509static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1510{
1511 return (v & 0xffffffff) << 0;
1512}
1513static inline u32 gr_ds_zbc_color_a_r(void)
1514{
1515 return 0x00405810;
1516}
1517static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1518{
1519 return (v & 0xffffffff) << 0;
1520}
1521static inline u32 gr_ds_zbc_color_fmt_r(void)
1522{
1523 return 0x00405814;
1524}
1525static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1526{
1527 return (v & 0x7f) << 0;
1528}
1529static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1530{
1531 return 0x0;
1532}
1533static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1534{
1535 return 0x00000001;
1536}
1537static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1538{
1539 return 0x00000002;
1540}
1541static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1542{
1543 return 0x00000004;
1544}
1545static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1546{
1547 return 0x00000028;
1548}
1549static inline u32 gr_ds_zbc_z_r(void)
1550{
1551 return 0x00405818;
1552}
1553static inline u32 gr_ds_zbc_z_val_s(void)
1554{
1555 return 32;
1556}
1557static inline u32 gr_ds_zbc_z_val_f(u32 v)
1558{
1559 return (v & 0xffffffff) << 0;
1560}
1561static inline u32 gr_ds_zbc_z_val_m(void)
1562{
1563 return 0xffffffff << 0;
1564}
1565static inline u32 gr_ds_zbc_z_val_v(u32 r)
1566{
1567 return (r >> 0) & 0xffffffff;
1568}
1569static inline u32 gr_ds_zbc_z_val__init_v(void)
1570{
1571 return 0x00000000;
1572}
1573static inline u32 gr_ds_zbc_z_val__init_f(void)
1574{
1575 return 0x0;
1576}
1577static inline u32 gr_ds_zbc_z_fmt_r(void)
1578{
1579 return 0x0040581c;
1580}
1581static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1582{
1583 return (v & 0x1) << 0;
1584}
1585static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1586{
1587 return 0x0;
1588}
1589static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1590{
1591 return 0x00000001;
1592}
1593static inline u32 gr_ds_zbc_tbl_index_r(void)
1594{
1595 return 0x00405820;
1596}
1597static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1598{
1599 return (v & 0xf) << 0;
1600}
1601static inline u32 gr_ds_zbc_tbl_ld_r(void)
1602{
1603 return 0x00405824;
1604}
1605static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1606{
1607 return 0x0;
1608}
1609static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1610{
1611 return 0x1;
1612}
1613static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1614{
1615 return 0x0;
1616}
1617static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1618{
1619 return 0x4;
1620}
1621static inline u32 gr_ds_tga_constraintlogic_r(void)
1622{
1623 return 0x00405830;
1624}
1625static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1626{
1627 return (v & 0xffff) << 16;
1628}
1629static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1630{
1631 return (v & 0xffff) << 0;
1632}
1633static inline u32 gr_ds_hww_esr_r(void)
1634{
1635 return 0x00405840;
1636}
1637static inline u32 gr_ds_hww_esr_reset_s(void)
1638{
1639 return 1;
1640}
1641static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1642{
1643 return (v & 0x1) << 30;
1644}
1645static inline u32 gr_ds_hww_esr_reset_m(void)
1646{
1647 return 0x1 << 30;
1648}
1649static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1650{
1651 return (r >> 30) & 0x1;
1652}
1653static inline u32 gr_ds_hww_esr_reset_task_v(void)
1654{
1655 return 0x00000001;
1656}
1657static inline u32 gr_ds_hww_esr_reset_task_f(void)
1658{
1659 return 0x40000000;
1660}
1661static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1662{
1663 return 0x80000000;
1664}
1665static inline u32 gr_ds_hww_esr_2_r(void)
1666{
1667 return 0x00405848;
1668}
1669static inline u32 gr_ds_hww_esr_2_reset_s(void)
1670{
1671 return 1;
1672}
1673static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
1674{
1675 return (v & 0x1) << 30;
1676}
1677static inline u32 gr_ds_hww_esr_2_reset_m(void)
1678{
1679 return 0x1 << 30;
1680}
1681static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
1682{
1683 return (r >> 30) & 0x1;
1684}
1685static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
1686{
1687 return 0x00000001;
1688}
1689static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
1690{
1691 return 0x40000000;
1692}
1693static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
1694{
1695 return 0x80000000;
1696}
1697static inline u32 gr_ds_hww_report_mask_r(void)
1698{
1699 return 0x00405844;
1700}
1701static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1702{
1703 return 0x1;
1704}
1705static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1706{
1707 return 0x2;
1708}
1709static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1710{
1711 return 0x4;
1712}
1713static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1714{
1715 return 0x8;
1716}
1717static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1718{
1719 return 0x10;
1720}
1721static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1722{
1723 return 0x20;
1724}
1725static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1726{
1727 return 0x40;
1728}
1729static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1730{
1731 return 0x80;
1732}
1733static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1734{
1735 return 0x100;
1736}
1737static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1738{
1739 return 0x200;
1740}
1741static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1742{
1743 return 0x400;
1744}
1745static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1746{
1747 return 0x800;
1748}
1749static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
1750{
1751 return 0x1000;
1752}
1753static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
1754{
1755 return 0x2000;
1756}
1757static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
1758{
1759 return 0x4000;
1760}
1761static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
1762{
1763 return 0x8000;
1764}
1765static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
1766{
1767 return 0x10000;
1768}
1769static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
1770{
1771 return 0x20000;
1772}
1773static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
1774{
1775 return 0x40000;
1776}
1777static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
1778{
1779 return 0x80000;
1780}
1781static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
1782{
1783 return 0x100000;
1784}
1785static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
1786{
1787 return 0x200000;
1788}
1789static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
1790{
1791 return 0x400000;
1792}
1793static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
1794{
1795 return 0x800000;
1796}
1797static inline u32 gr_ds_hww_report_mask_2_r(void)
1798{
1799 return 0x0040584c;
1800}
1801static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
1802{
1803 return 0x1;
1804}
1805static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
1806{
1807 return 0x00405870 + i*4;
1808}
1809static inline u32 gr_scc_bundle_cb_base_r(void)
1810{
1811 return 0x00408004;
1812}
1813static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
1814{
1815 return (v & 0xffffffff) << 0;
1816}
1817static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
1818{
1819 return 0x00000008;
1820}
1821static inline u32 gr_scc_bundle_cb_size_r(void)
1822{
1823 return 0x00408008;
1824}
1825static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
1826{
1827 return (v & 0x7ff) << 0;
1828}
1829static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
1830{
1831 return 0x00000030;
1832}
1833static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
1834{
1835 return 0x00000100;
1836}
1837static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
1838{
1839 return 0x00000000;
1840}
1841static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
1842{
1843 return 0x0;
1844}
1845static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
1846{
1847 return 0x80000000;
1848}
1849static inline u32 gr_scc_pagepool_base_r(void)
1850{
1851 return 0x0040800c;
1852}
1853static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
1854{
1855 return (v & 0xffffffff) << 0;
1856}
1857static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
1858{
1859 return 0x00000008;
1860}
1861static inline u32 gr_scc_pagepool_r(void)
1862{
1863 return 0x00408010;
1864}
1865static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
1866{
1867 return (v & 0xff) << 0;
1868}
1869static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
1870{
1871 return 0x00000000;
1872}
1873static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
1874{
1875 return 0x00000080;
1876}
1877static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
1878{
1879 return 0x00000100;
1880}
1881static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
1882{
1883 return 8;
1884}
1885static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
1886{
1887 return (v & 0xff) << 8;
1888}
1889static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
1890{
1891 return 0xff << 8;
1892}
1893static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
1894{
1895 return (r >> 8) & 0xff;
1896}
1897static inline u32 gr_scc_pagepool_valid_true_f(void)
1898{
1899 return 0x80000000;
1900}
1901static inline u32 gr_scc_init_r(void)
1902{
1903 return 0x0040802c;
1904}
1905static inline u32 gr_scc_init_ram_trigger_f(void)
1906{
1907 return 0x1;
1908}
1909static inline u32 gr_scc_hww_esr_r(void)
1910{
1911 return 0x00408030;
1912}
1913static inline u32 gr_scc_hww_esr_reset_active_f(void)
1914{
1915 return 0x40000000;
1916}
1917static inline u32 gr_scc_hww_esr_en_enable_f(void)
1918{
1919 return 0x80000000;
1920}
1921static inline u32 gr_sked_hww_esr_r(void)
1922{
1923 return 0x00407020;
1924}
1925static inline u32 gr_sked_hww_esr_reset_active_f(void)
1926{
1927 return 0x40000000;
1928}
1929static inline u32 gr_cwd_fs_r(void)
1930{
1931 return 0x00405b00;
1932}
1933static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
1934{
1935 return (v & 0xff) << 0;
1936}
1937static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
1938{
1939 return (v & 0xff) << 8;
1940}
1941static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
1942{
1943 return 0x00405b60 + i*4;
1944}
1945static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
1946{
1947 return (v & 0xf) << 0;
1948}
1949static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
1950{
1951 return (v & 0xf) << 8;
1952}
1953static inline u32 gr_cwd_sm_id_r(u32 i)
1954{
1955 return 0x00405ba0 + i*4;
1956}
1957static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
1958{
1959 return (v & 0xff) << 0;
1960}
1961static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
1962{
1963 return (v & 0xff) << 8;
1964}
1965static inline u32 gr_gpc0_fs_gpc_r(void)
1966{
1967 return 0x00502608;
1968}
1969static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
1970{
1971 return (r >> 0) & 0x1f;
1972}
1973static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
1974{
1975 return (r >> 16) & 0x1f;
1976}
1977static inline u32 gr_gpc0_cfg_r(void)
1978{
1979 return 0x00502620;
1980}
1981static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
1982{
1983 return (r >> 0) & 0xff;
1984}
1985static inline u32 gr_gpccs_rc_lanes_r(void)
1986{
1987 return 0x00502880;
1988}
1989static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
1990{
1991 return 6;
1992}
1993static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
1994{
1995 return (v & 0x3f) << 0;
1996}
1997static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
1998{
1999 return 0x3f << 0;
2000}
2001static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2002{
2003 return (r >> 0) & 0x3f;
2004}
2005static inline u32 gr_gpccs_rc_lane_size_r(u32 i)
2006{
2007 return 0x00502910 + i*0;
2008}
2009static inline u32 gr_gpccs_rc_lane_size__size_1_v(void)
2010{
2011 return 0x00000010;
2012}
2013static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2014{
2015 return 24;
2016}
2017static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2018{
2019 return (v & 0xffffff) << 0;
2020}
2021static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2022{
2023 return 0xffffff << 0;
2024}
2025static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2026{
2027 return (r >> 0) & 0xffffff;
2028}
2029static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2030{
2031 return 0x00000000;
2032}
2033static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2034{
2035 return 0x0;
2036}
2037static inline u32 gr_gpc0_zcull_fs_r(void)
2038{
2039 return 0x00500910;
2040}
2041static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2042{
2043 return (v & 0x1ff) << 0;
2044}
2045static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2046{
2047 return (v & 0xf) << 16;
2048}
2049static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2050{
2051 return 0x00500914;
2052}
2053static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2054{
2055 return (v & 0xf) << 0;
2056}
2057static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2058{
2059 return (v & 0xf) << 8;
2060}
2061static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2062{
2063 return 0x00500918;
2064}
2065static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2066{
2067 return (v & 0xffffff) << 0;
2068}
2069static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2070{
2071 return 0x00800000;
2072}
2073static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2074{
2075 return 0x00500920;
2076}
2077static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2078{
2079 return (v & 0xffff) << 0;
2080}
2081static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2082{
2083 return 0x00500a04 + i*32;
2084}
2085static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2086{
2087 return 0x00000040;
2088}
2089static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2090{
2091 return 0x00000010;
2092}
2093static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2094{
2095 return 0x00500c10 + i*4;
2096}
2097static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2098{
2099 return (v & 0xff) << 0;
2100}
2101static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2102{
2103 return 0x00500c30 + i*4;
2104}
2105static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2106{
2107 return (r >> 0) & 0xff;
2108}
2109static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2110{
2111 return 0x00504088;
2112}
2113static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2114{
2115 return (v & 0xffff) << 0;
2116}
2117static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2118{
2119 return 0x00504698;
2120}
2121static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2122{
2123 return (v & 0xffff) << 0;
2124}
2125static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2126{
2127 return 0x0050469c;
2128}
2129static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2130{
2131 return (r >> 0) & 0xff;
2132}
2133static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2134{
2135 return (r >> 8) & 0xfff;
2136}
2137static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2138{
2139 return (r >> 20) & 0xfff;
2140}
2141static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2142{
2143 return 0x00503018;
2144}
2145static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2146{
2147 return 0x1 << 0;
2148}
2149static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2150{
2151 return 0x1;
2152}
2153static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2154{
2155 return 0x005030c0;
2156}
2157static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2158{
2159 return (v & 0xffff) << 0;
2160}
2161static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2162{
2163 return 0xffff << 0;
2164}
2165static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2166{
2167 return 0x00000400;
2168}
2169static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2170{
2171 return 0x00000020;
2172}
2173static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2174{
2175 return 0x005030f4;
2176}
2177static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2178{
2179 return 0x005030e4;
2180}
2181static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2182{
2183 return (v & 0xffff) << 0;
2184}
2185static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2186{
2187 return 0xffff << 0;
2188}
2189static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2190{
2191 return 0x00001000;
2192}
2193static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2194{
2195 return 0x00000020;
2196}
2197static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2198{
2199 return 0x005030f8;
2200}
2201static inline u32 gr_gpccs_falcon_addr_r(void)
2202{
2203 return 0x0041a0ac;
2204}
2205static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2206{
2207 return 6;
2208}
2209static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2210{
2211 return (v & 0x3f) << 0;
2212}
2213static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2214{
2215 return 0x3f << 0;
2216}
2217static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2218{
2219 return (r >> 0) & 0x3f;
2220}
2221static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2222{
2223 return 0x00000000;
2224}
2225static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2226{
2227 return 0x0;
2228}
2229static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2230{
2231 return 6;
2232}
2233static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2234{
2235 return (v & 0x3f) << 6;
2236}
2237static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2238{
2239 return 0x3f << 6;
2240}
2241static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2242{
2243 return (r >> 6) & 0x3f;
2244}
2245static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2246{
2247 return 0x00000000;
2248}
2249static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2250{
2251 return 0x0;
2252}
2253static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2254{
2255 return 12;
2256}
2257static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2258{
2259 return (v & 0xfff) << 0;
2260}
2261static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2262{
2263 return 0xfff << 0;
2264}
2265static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2266{
2267 return (r >> 0) & 0xfff;
2268}
2269static inline u32 gr_gpccs_cpuctl_r(void)
2270{
2271 return 0x0041a100;
2272}
2273static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2274{
2275 return (v & 0x1) << 1;
2276}
2277static inline u32 gr_gpccs_dmactl_r(void)
2278{
2279 return 0x0041a10c;
2280}
2281static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2282{
2283 return (v & 0x1) << 0;
2284}
2285static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2286{
2287 return 0x1 << 1;
2288}
2289static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2290{
2291 return 0x1 << 2;
2292}
2293static inline u32 gr_gpccs_imemc_r(u32 i)
2294{
2295 return 0x0041a180 + i*16;
2296}
2297static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2298{
2299 return (v & 0x3f) << 2;
2300}
2301static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2302{
2303 return (v & 0xff) << 8;
2304}
2305static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2306{
2307 return (v & 0x1) << 24;
2308}
2309static inline u32 gr_gpccs_imemd_r(u32 i)
2310{
2311 return 0x0041a184 + i*16;
2312}
2313static inline u32 gr_gpccs_imemt_r(u32 i)
2314{
2315 return 0x0041a188 + i*16;
2316}
2317static inline u32 gr_gpccs_imemt__size_1_v(void)
2318{
2319 return 0x00000004;
2320}
2321static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2322{
2323 return (v & 0xffff) << 0;
2324}
2325static inline u32 gr_gpccs_dmemc_r(u32 i)
2326{
2327 return 0x0041a1c0 + i*8;
2328}
2329static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2330{
2331 return (v & 0x3f) << 2;
2332}
2333static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2334{
2335 return (v & 0xff) << 8;
2336}
2337static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2338{
2339 return (v & 0x1) << 24;
2340}
2341static inline u32 gr_gpccs_dmemd_r(u32 i)
2342{
2343 return 0x0041a1c4 + i*8;
2344}
2345static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2346{
2347 return 0x0041a800 + i*4;
2348}
2349static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2350{
2351 return (v & 0xffffffff) << 0;
2352}
2353static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
2354{
2355 return 0x00418e24;
2356}
2357static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
2358{
2359 return 32;
2360}
2361static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
2362{
2363 return (v & 0xffffffff) << 0;
2364}
2365static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
2366{
2367 return 0xffffffff << 0;
2368}
2369static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
2370{
2371 return (r >> 0) & 0xffffffff;
2372}
2373static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
2374{
2375 return 0x00000000;
2376}
2377static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
2378{
2379 return 0x0;
2380}
2381static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
2382{
2383 return 0x00418e28;
2384}
2385static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
2386{
2387 return 11;
2388}
2389static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
2390{
2391 return (v & 0x7ff) << 0;
2392}
2393static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
2394{
2395 return 0x7ff << 0;
2396}
2397static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
2398{
2399 return (r >> 0) & 0x7ff;
2400}
2401static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
2402{
2403 return 0x00000030;
2404}
2405static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
2406{
2407 return 0x30;
2408}
2409static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
2410{
2411 return 1;
2412}
2413static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
2414{
2415 return (v & 0x1) << 31;
2416}
2417static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
2418{
2419 return 0x1 << 31;
2420}
2421static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
2422{
2423 return (r >> 31) & 0x1;
2424}
2425static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
2426{
2427 return 0x00000000;
2428}
2429static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
2430{
2431 return 0x0;
2432}
2433static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
2434{
2435 return 0x00000001;
2436}
2437static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
2438{
2439 return 0x80000000;
2440}
2441static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
2442{
2443 return 0x00418ea0 + i*4;
2444}
2445static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
2446{
2447 return (v & 0xffff) << 0;
2448}
2449static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
2450{
2451 return 0xffff << 0;
2452}
2453static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
2454{
2455 return (v & 0xffff) << 16;
2456}
2457static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void)
2458{
2459 return 0xffff << 16;
2460}
2461static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
2462{
2463 return 0x00418e30;
2464}
2465static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v)
2466{
2467 return (v & 0xff) << 0;
2468}
2469static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void)
2470{
2471 return 0x80000000;
2472}
2473static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2474{
2475 return 0x00418810;
2476}
2477static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2478{
2479 return (v & 0xfffffff) << 0;
2480}
2481static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2482{
2483 return 0x0000000c;
2484}
2485static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2486{
2487 return 0x80000000;
2488}
2489static inline u32 gr_crstr_gpc_map0_r(void)
2490{
2491 return 0x00418b08;
2492}
2493static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2494{
2495 return (v & 0x7) << 0;
2496}
2497static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2498{
2499 return (v & 0x7) << 5;
2500}
2501static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2502{
2503 return (v & 0x7) << 10;
2504}
2505static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2506{
2507 return (v & 0x7) << 15;
2508}
2509static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2510{
2511 return (v & 0x7) << 20;
2512}
2513static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2514{
2515 return (v & 0x7) << 25;
2516}
2517static inline u32 gr_crstr_gpc_map1_r(void)
2518{
2519 return 0x00418b0c;
2520}
2521static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2522{
2523 return (v & 0x7) << 0;
2524}
2525static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2526{
2527 return (v & 0x7) << 5;
2528}
2529static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2530{
2531 return (v & 0x7) << 10;
2532}
2533static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2534{
2535 return (v & 0x7) << 15;
2536}
2537static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2538{
2539 return (v & 0x7) << 20;
2540}
2541static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2542{
2543 return (v & 0x7) << 25;
2544}
2545static inline u32 gr_crstr_gpc_map2_r(void)
2546{
2547 return 0x00418b10;
2548}
2549static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2550{
2551 return (v & 0x7) << 0;
2552}
2553static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2554{
2555 return (v & 0x7) << 5;
2556}
2557static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2558{
2559 return (v & 0x7) << 10;
2560}
2561static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2562{
2563 return (v & 0x7) << 15;
2564}
2565static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2566{
2567 return (v & 0x7) << 20;
2568}
2569static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2570{
2571 return (v & 0x7) << 25;
2572}
2573static inline u32 gr_crstr_gpc_map3_r(void)
2574{
2575 return 0x00418b14;
2576}
2577static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2578{
2579 return (v & 0x7) << 0;
2580}
2581static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2582{
2583 return (v & 0x7) << 5;
2584}
2585static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2586{
2587 return (v & 0x7) << 10;
2588}
2589static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
2590{
2591 return (v & 0x7) << 15;
2592}
2593static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
2594{
2595 return (v & 0x7) << 20;
2596}
2597static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
2598{
2599 return (v & 0x7) << 25;
2600}
2601static inline u32 gr_crstr_gpc_map4_r(void)
2602{
2603 return 0x00418b18;
2604}
2605static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
2606{
2607 return (v & 0x7) << 0;
2608}
2609static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
2610{
2611 return (v & 0x7) << 5;
2612}
2613static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
2614{
2615 return (v & 0x7) << 10;
2616}
2617static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
2618{
2619 return (v & 0x7) << 15;
2620}
2621static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
2622{
2623 return (v & 0x7) << 20;
2624}
2625static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
2626{
2627 return (v & 0x7) << 25;
2628}
2629static inline u32 gr_crstr_gpc_map5_r(void)
2630{
2631 return 0x00418b1c;
2632}
2633static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
2634{
2635 return (v & 0x7) << 0;
2636}
2637static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
2638{
2639 return (v & 0x7) << 5;
2640}
2641static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
2642{
2643 return (v & 0x7) << 10;
2644}
2645static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
2646{
2647 return (v & 0x7) << 15;
2648}
2649static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
2650{
2651 return (v & 0x7) << 20;
2652}
2653static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
2654{
2655 return (v & 0x7) << 25;
2656}
2657static inline u32 gr_crstr_map_table_cfg_r(void)
2658{
2659 return 0x00418bb8;
2660}
2661static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
2662{
2663 return (v & 0xff) << 0;
2664}
2665static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
2666{
2667 return (v & 0xff) << 8;
2668}
2669static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
2670{
2671 return 0x00418980;
2672}
2673static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
2674{
2675 return (v & 0x7) << 0;
2676}
2677static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
2678{
2679 return (v & 0x7) << 4;
2680}
2681static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
2682{
2683 return (v & 0x7) << 8;
2684}
2685static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
2686{
2687 return (v & 0x7) << 12;
2688}
2689static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
2690{
2691 return (v & 0x7) << 16;
2692}
2693static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
2694{
2695 return (v & 0x7) << 20;
2696}
2697static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
2698{
2699 return (v & 0x7) << 24;
2700}
2701static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
2702{
2703 return (v & 0x7) << 28;
2704}
2705static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
2706{
2707 return 0x00418984;
2708}
2709static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
2710{
2711 return (v & 0x7) << 0;
2712}
2713static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
2714{
2715 return (v & 0x7) << 4;
2716}
2717static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
2718{
2719 return (v & 0x7) << 8;
2720}
2721static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
2722{
2723 return (v & 0x7) << 12;
2724}
2725static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
2726{
2727 return (v & 0x7) << 16;
2728}
2729static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
2730{
2731 return (v & 0x7) << 20;
2732}
2733static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
2734{
2735 return (v & 0x7) << 24;
2736}
2737static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
2738{
2739 return (v & 0x7) << 28;
2740}
2741static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
2742{
2743 return 0x00418988;
2744}
2745static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
2746{
2747 return (v & 0x7) << 0;
2748}
2749static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
2750{
2751 return (v & 0x7) << 4;
2752}
2753static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
2754{
2755 return (v & 0x7) << 8;
2756}
2757static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
2758{
2759 return (v & 0x7) << 12;
2760}
2761static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
2762{
2763 return (v & 0x7) << 16;
2764}
2765static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
2766{
2767 return (v & 0x7) << 20;
2768}
2769static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
2770{
2771 return (v & 0x7) << 24;
2772}
2773static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
2774{
2775 return 3;
2776}
2777static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
2778{
2779 return (v & 0x7) << 28;
2780}
2781static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
2782{
2783 return 0x7 << 28;
2784}
2785static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
2786{
2787 return (r >> 28) & 0x7;
2788}
2789static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
2790{
2791 return 0x0041898c;
2792}
2793static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
2794{
2795 return (v & 0x7) << 0;
2796}
2797static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
2798{
2799 return (v & 0x7) << 4;
2800}
2801static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
2802{
2803 return (v & 0x7) << 8;
2804}
2805static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
2806{
2807 return (v & 0x7) << 12;
2808}
2809static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
2810{
2811 return (v & 0x7) << 16;
2812}
2813static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
2814{
2815 return (v & 0x7) << 20;
2816}
2817static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
2818{
2819 return (v & 0x7) << 24;
2820}
2821static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
2822{
2823 return (v & 0x7) << 28;
2824}
2825static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
2826{
2827 return 0x00418c6c;
2828}
2829static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
2830{
2831 return 0x0;
2832}
2833static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
2834{
2835 return 0x1;
2836}
2837static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
2838{
2839 return 0x00419004;
2840}
2841static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
2842{
2843 return (v & 0xffffffff) << 0;
2844}
2845static inline u32 gr_gpcs_gcc_pagepool_r(void)
2846{
2847 return 0x00419008;
2848}
2849static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
2850{
2851 return (v & 0xff) << 0;
2852}
2853static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
2854{
2855 return 0x0041980c;
2856}
2857static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
2858{
2859 return 0x10;
2860}
2861static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
2862{
2863 return 0x00419848;
2864}
2865static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
2866{
2867 return (v & 0xfffffff) << 0;
2868}
2869static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
2870{
2871 return (v & 0x1) << 28;
2872}
2873static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
2874{
2875 return 0x10000000;
2876}
2877static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
2878{
2879 return 0x00419c00;
2880}
2881static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
2882{
2883 return 0x0;
2884}
2885static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
2886{
2887 return 0x8;
2888}
2889static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
2890{
2891 return 0x00419c2c;
2892}
2893static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
2894{
2895 return (v & 0xfffffff) << 0;
2896}
2897static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
2898{
2899 return (v & 0x1) << 28;
2900}
2901static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
2902{
2903 return 0x10000000;
2904}
2905static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
2906{
2907 return 0x00419e44;
2908}
2909static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
2910{
2911 return 0x2;
2912}
2913static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
2914{
2915 return 0x4;
2916}
2917static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
2918{
2919 return 0x8;
2920}
2921static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
2922{
2923 return 0x10;
2924}
2925static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
2926{
2927 return 0x20;
2928}
2929static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
2930{
2931 return 0x40;
2932}
2933static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
2934{
2935 return 0x80;
2936}
2937static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
2938{
2939 return 0x100;
2940}
2941static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
2942{
2943 return 0x200;
2944}
2945static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
2946{
2947 return 0x400;
2948}
2949static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
2950{
2951 return 0x800;
2952}
2953static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
2954{
2955 return 0x1000;
2956}
2957static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
2958{
2959 return 0x2000;
2960}
2961static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
2962{
2963 return 0x4000;
2964}
2965static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
2966{
2967 return 0x8000;
2968}
2969static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
2970{
2971 return 0x10000;
2972}
2973static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
2974{
2975 return 0x20000;
2976}
2977static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
2978{
2979 return 0x40000;
2980}
2981static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
2982{
2983 return 0x800000;
2984}
2985static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
2986{
2987 return 0x400000;
2988}
2989static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
2990{
2991 return 0x80000;
2992}
2993static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
2994{
2995 return 0x100000;
2996}
2997static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
2998{
2999 return 0x00419e4c;
3000}
3001static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3002{
3003 return 0x1;
3004}
3005static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3006{
3007 return 0x2;
3008}
3009static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3010{
3011 return 0x4;
3012}
3013static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3014{
3015 return 0x8;
3016}
3017static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3018{
3019 return 0x10;
3020}
3021static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3022{
3023 return 0x20;
3024}
3025static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3026{
3027 return 0x40;
3028}
3029static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3030{
3031 return 0x00419d0c;
3032}
3033static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3034{
3035 return 0x2;
3036}
3037static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3038{
3039 return 0x1;
3040}
3041static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3042{
3043 return 0x0050450c;
3044}
3045static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3046{
3047 return 0x2;
3048}
3049static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3050{
3051 return (r >> 1) & 0x1;
3052}
3053static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3054{
3055 return 0x0041ac94;
3056}
3057static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3058{
3059 return (v & 0xff) << 16;
3060}
3061static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3062{
3063 return 0x00502c90;
3064}
3065static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3066{
3067 return (r >> 16) & 0xff;
3068}
3069static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3070{
3071 return 0x00000001;
3072}
3073static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3074{
3075 return 0x00504508;
3076}
3077static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3078{
3079 return (r >> 0) & 0x1;
3080}
3081static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3082{
3083 return 0x00000001;
3084}
3085static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3086{
3087 return (r >> 1) & 0x1;
3088}
3089static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3090{
3091 return 0x00000001;
3092}
3093static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3094{
3095 return 0x00504610;
3096}
3097static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
3098{
3099 return 0x1 << 0;
3100}
3101static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3102{
3103 return (r >> 0) & 0x1;
3104}
3105static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3106{
3107 return 0x00000001;
3108}
3109static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
3110{
3111 return 0x1;
3112}
3113static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3114{
3115 return 0x00000000;
3116}
3117static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
3118{
3119 return 0x0;
3120}
3121static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3122{
3123 return 0x80000000;
3124}
3125static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3126{
3127 return 0x0;
3128}
3129static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3130{
3131 return 0x40000000;
3132}
3133static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
3134{
3135 return 0x1 << 1;
3136}
3137static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3138{
3139 return (r >> 1) & 0x1;
3140}
3141static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3142{
3143 return 0x0;
3144}
3145static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
3146{
3147 return 0x1 << 2;
3148}
3149static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3150{
3151 return (r >> 2) & 0x1;
3152}
3153static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3154{
3155 return 0x0;
3156}
3157static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3158{
3159 return 0x00504614;
3160}
3161static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3162{
3163 return 0x00504624;
3164}
3165static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3166{
3167 return 0x00504634;
3168}
3169static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3170{
3171 return 0x00419e24;
3172}
3173static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v(void)
3174{
3175 return 0x00000000;
3176}
3177static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v(void)
3178{
3179 return 0x00000000;
3180}
3181static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3182{
3183 return 0x0050460c;
3184}
3185static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3186{
3187 return (r >> 0) & 0x1;
3188}
3189static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3190{
3191 return (r >> 4) & 0x1;
3192}
3193static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3194{
3195 return 0x00000001;
3196}
3197static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3198{
3199 return 0x00419e50;
3200}
3201static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3202{
3203 return 0x10;
3204}
3205static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3206{
3207 return 0x20;
3208}
3209static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3210{
3211 return 0x40;
3212}
3213static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3214{
3215 return 0x00504650;
3216}
3217static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3218{
3219 return 0x10;
3220}
3221static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3222{
3223 return 0x20;
3224}
3225static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3226{
3227 return 0x40;
3228}
3229static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3230{
3231 return 0x00504224;
3232}
3233static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3234{
3235 return 0x1;
3236}
3237static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3238{
3239 return 0x00504648;
3240}
3241static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3242{
3243 return (r >> 0) & 0xffff;
3244}
3245static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3246{
3247 return 0x00000000;
3248}
3249static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3250{
3251 return 0x0;
3252}
3253static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3254{
3255 return 0x00504770;
3256}
3257static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3258{
3259 return 0x00419f70;
3260}
3261static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3262{
3263 return 0x1 << 4;
3264}
3265static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3266{
3267 return (v & 0x1) << 4;
3268}
3269static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3270{
3271 return 0x0050477c;
3272}
3273static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3274{
3275 return 0x00419f7c;
3276}
3277static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3278{
3279 return 0x1 << 0;
3280}
3281static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3282{
3283 return (v & 0x1) << 0;
3284}
3285static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3286{
3287 return 0x0041be08;
3288}
3289static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3290{
3291 return 0x4;
3292}
3293static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3294{
3295 return 0x0041bf00;
3296}
3297static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3298{
3299 return 0x0041bf04;
3300}
3301static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3302{
3303 return 0x0041bf08;
3304}
3305static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3306{
3307 return 0x0041bf0c;
3308}
3309static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3310{
3311 return 0x0041bf10;
3312}
3313static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3314{
3315 return 0x0041bf14;
3316}
3317static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3318{
3319 return 0x0041bfd0;
3320}
3321static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3322{
3323 return (v & 0xff) << 0;
3324}
3325static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3326{
3327 return (v & 0xff) << 8;
3328}
3329static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3330{
3331 return (v & 0x1f) << 16;
3332}
3333static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3334{
3335 return (v & 0x7) << 21;
3336}
3337static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3338{
3339 return (v & 0x1f) << 24;
3340}
3341static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3342{
3343 return 0x0041bfd4;
3344}
3345static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3346{
3347 return (v & 0xffffff) << 0;
3348}
3349static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3350{
3351 return 0x0041bfe4;
3352}
3353static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3354{
3355 return (v & 0x1f) << 0;
3356}
3357static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3358{
3359 return (v & 0x1f) << 5;
3360}
3361static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3362{
3363 return (v & 0x1f) << 10;
3364}
3365static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3366{
3367 return (v & 0x1f) << 15;
3368}
3369static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3370{
3371 return (v & 0x1f) << 20;
3372}
3373static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3374{
3375 return (v & 0x1f) << 25;
3376}
3377static inline u32 gr_bes_zrop_settings_r(void)
3378{
3379 return 0x00408850;
3380}
3381static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3382{
3383 return (v & 0xf) << 0;
3384}
3385static inline u32 gr_be0_crop_debug3_r(void)
3386{
3387 return 0x00410108;
3388}
3389static inline u32 gr_bes_crop_debug3_r(void)
3390{
3391 return 0x00408908;
3392}
3393static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3394{
3395 return 0x1 << 31;
3396}
3397static inline u32 gr_bes_crop_settings_r(void)
3398{
3399 return 0x00408958;
3400}
3401static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3402{
3403 return (v & 0xf) << 0;
3404}
3405static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3406{
3407 return 0x00000020;
3408}
3409static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3410{
3411 return 0x00000020;
3412}
3413static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3414{
3415 return 0x000000c0;
3416}
3417static inline u32 gr_zcull_subregion_qty_v(void)
3418{
3419 return 0x00000010;
3420}
3421static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3422{
3423 return 0x00504604;
3424}
3425static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3426{
3427 return 0x00504608;
3428}
3429static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3430{
3431 return 0x0050465c;
3432}
3433static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3434{
3435 return 0x00504660;
3436}
3437static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3438{
3439 return 0x00504664;
3440}
3441static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3442{
3443 return 0x00504668;
3444}
3445static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3446{
3447 return 0x0050466c;
3448}
3449static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3450{
3451 return 0x00504658;
3452}
3453static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3454{
3455 return 0x00504730;
3456}
3457static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3458{
3459 return 0x00504734;
3460}
3461static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3462{
3463 return 0x00504738;
3464}
3465static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3466{
3467 return 0x0050473c;
3468}
3469static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3470{
3471 return 0x00504740;
3472}
3473static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3474{
3475 return 0x00504744;
3476}
3477static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3478{
3479 return 0x00504748;
3480}
3481static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3482{
3483 return 0x0050474c;
3484}
3485static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
3486{
3487 return 0x00504678;
3488}
3489static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3490{
3491 return 0x00504694;
3492}
3493static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
3494{
3495 return 0x005046f0;
3496}
3497static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
3498{
3499 return 0x00504700;
3500}
3501static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
3502{
3503 return 0x005046f4;
3504}
3505static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
3506{
3507 return 0x00504704;
3508}
3509static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
3510{
3511 return 0x005046f8;
3512}
3513static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
3514{
3515 return 0x00504708;
3516}
3517static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
3518{
3519 return 0x005046fc;
3520}
3521static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
3522{
3523 return 0x0050470c;
3524}
3525static inline u32 gr_fe_pwr_mode_r(void)
3526{
3527 return 0x00404170;
3528}
3529static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3530{
3531 return 0x0;
3532}
3533static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3534{
3535 return 0x2;
3536}
3537static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3538{
3539 return (r >> 4) & 0x1;
3540}
3541static inline u32 gr_fe_pwr_mode_req_send_f(void)
3542{
3543 return 0x10;
3544}
3545static inline u32 gr_fe_pwr_mode_req_done_v(void)
3546{
3547 return 0x00000000;
3548}
3549static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
3550{
3551 return 0x00418880;
3552}
3553static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
3554{
3555 return 0x1 << 0;
3556}
3557static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
3558{
3559 return 0x1 << 11;
3560}
3561static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void)
3562{
3563 return 0x1 << 12;
3564}
3565static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
3566{
3567 return 0x1 << 1;
3568}
3569static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
3570{
3571 return 0x1 << 2;
3572}
3573static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
3574{
3575 return 0x3 << 3;
3576}
3577static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
3578{
3579 return 0x3 << 5;
3580}
3581static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
3582{
3583 return 0x3 << 28;
3584}
3585static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
3586{
3587 return 0x1 << 30;
3588}
3589static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
3590{
3591 return 0x1 << 31;
3592}
3593static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
3594{
3595 return 0x00418890;
3596}
3597static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
3598{
3599 return 0x00418894;
3600}
3601static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
3602{
3603 return 0x004188b0;
3604}
3605static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void)
3606{
3607 return 0x1 << 16;
3608}
3609static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
3610{
3611 return (r >> 16) & 0x1;
3612}
3613static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
3614{
3615 return 0x00000001;
3616}
3617static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void)
3618{
3619 return 0x10000;
3620}
3621static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void)
3622{
3623 return 0x00000000;
3624}
3625static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void)
3626{
3627 return 0x0;
3628}
3629static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
3630{
3631 return 0x004188b4;
3632}
3633static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
3634{
3635 return 0x004188b8;
3636}
3637static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
3638{
3639 return 0x004188ac;
3640}
3641static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
3642{
3643 return 0x00419e10;
3644}
3645static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
3646{
3647 return (v & 0x1) << 0;
3648}
3649static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
3650{
3651 return 0x00000001;
3652}
3653static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
3654{
3655 return 0x1 << 31;
3656}
3657static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
3658{
3659 return (r >> 31) & 0x1;
3660}
3661static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
3662{
3663 return 0x80000000;
3664}
3665static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
3666{
3667 return 0x0;
3668}
3669static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
3670{
3671 return 0x1 << 30;
3672}
3673static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
3674{
3675 return (r >> 30) & 0x1;
3676}
3677static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
3678{
3679 return 0x40000000;
3680}
3681#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_ltc_gm206.h b/drivers/gpu/nvgpu/gm206/hw_ltc_gm206.h
new file mode 100644
index 00000000..66afd80b
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_ltc_gm206.h
@@ -0,0 +1,497 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ltc_gm206_h_
51#define _hw_ltc_gm206_h_
52
53static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
54{
55 return 0x0014046c;
56}
57static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
58{
59 return 0x00140518;
60}
61static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
62{
63 return 0x0017e318;
64}
65static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
66{
67 return 0x1 << 15;
68}
69static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
70{
71 return 0x00140494;
72}
73static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
74{
75 return (r >> 0) & 0xffff;
76}
77static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
78{
79 return (r >> 16) & 0x3;
80}
81static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
82{
83 return 0x00000000;
84}
85static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
86{
87 return 0x00000001;
88}
89static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
90{
91 return 0x00000002;
92}
93static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
94{
95 return 0x0017e26c;
96}
97static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
98{
99 return 0x1;
100}
101static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
102{
103 return 0x2;
104}
105static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
106{
107 return (r >> 2) & 0x1;
108}
109static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
114{
115 return 0x4;
116}
117static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
118{
119 return 0x0014046c;
120}
121static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
122{
123 return 0x0017e270;
124}
125static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
126{
127 return (v & 0x1ffff) << 0;
128}
129static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
130{
131 return 0x0017e274;
132}
133static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
134{
135 return (v & 0x1ffff) << 0;
136}
137static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
138{
139 return 0x0001ffff;
140}
141static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
142{
143 return 0x0017e278;
144}
145static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
146{
147 return 0x0000000b;
148}
149static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
150{
151 return (r >> 0) & 0x3ffffff;
152}
153static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
154{
155 return 0x0017e27c;
156}
157static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
158{
159 return 0x0017e000;
160}
161static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
162{
163 return 0x0017e280;
164}
165static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
166{
167 return (r >> 0) & 0xffff;
168}
169static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
170{
171 return (r >> 24) & 0xf;
172}
173static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
174{
175 return (r >> 28) & 0xf;
176}
177static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
178{
179 return 0x0017e2ac;
180}
181static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
182{
183 return (v & 0x1f) << 16;
184}
185static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
186{
187 return 0x0017e338;
188}
189static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
190{
191 return (v & 0xf) << 0;
192}
193static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
194{
195 return 0x0017e33c + i*4;
196}
197static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
198{
199 return 0x00000004;
200}
201static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
202{
203 return 0x0017e34c;
204}
205static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
206{
207 return 32;
208}
209static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
210{
211 return (v & 0xffffffff) << 0;
212}
213static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
214{
215 return 0xffffffff << 0;
216}
217static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
218{
219 return (r >> 0) & 0xffffffff;
220}
221static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
222{
223 return 0x0017e2b0;
224}
225static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
226{
227 return 0x10000000;
228}
229static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
230{
231 return 0x0017e214;
232}
233static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
234{
235 return (r >> 0) & 0x1;
236}
237static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
238{
239 return 0x00000001;
240}
241static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
242{
243 return 0x1;
244}
245static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
246{
247 return 0x00140214;
248}
249static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
250{
251 return (r >> 0) & 0x1;
252}
253static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
254{
255 return 0x00000001;
256}
257static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
258{
259 return 0x1;
260}
261static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
262{
263 return 0x00142214;
264}
265static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
266{
267 return (r >> 0) & 0x1;
268}
269static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
270{
271 return 0x00000001;
272}
273static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
274{
275 return 0x1;
276}
277static inline u32 ltc_ltcs_ltss_intr_r(void)
278{
279 return 0x0017e20c;
280}
281static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
282{
283 return 0x1 << 20;
284}
285static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
286{
287 return 0x1 << 30;
288}
289static inline u32 ltc_ltc0_lts0_intr_r(void)
290{
291 return 0x0014040c;
292}
293static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
294{
295 return 0x0017e2a0;
296}
297static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
298{
299 return (r >> 0) & 0x1;
300}
301static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
302{
303 return 0x00000001;
304}
305static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
306{
307 return 0x1;
308}
309static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
310{
311 return (r >> 8) & 0xf;
312}
313static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
314{
315 return 0x00000003;
316}
317static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
318{
319 return 0x300;
320}
321static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
322{
323 return (r >> 28) & 0x1;
324}
325static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
326{
327 return 0x00000001;
328}
329static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
330{
331 return 0x10000000;
332}
333static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
334{
335 return (r >> 29) & 0x1;
336}
337static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
338{
339 return 0x00000001;
340}
341static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
342{
343 return 0x20000000;
344}
345static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
346{
347 return (r >> 30) & 0x1;
348}
349static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
350{
351 return 0x00000001;
352}
353static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
354{
355 return 0x40000000;
356}
357static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
358{
359 return 0x0017e2a4;
360}
361static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
362{
363 return (r >> 0) & 0x1;
364}
365static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
366{
367 return 0x00000001;
368}
369static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
370{
371 return 0x1;
372}
373static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
374{
375 return (r >> 8) & 0xf;
376}
377static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
378{
379 return 0x00000003;
380}
381static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
382{
383 return 0x300;
384}
385static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
386{
387 return (r >> 16) & 0x1;
388}
389static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
390{
391 return 0x00000001;
392}
393static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
394{
395 return 0x10000;
396}
397static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
398{
399 return (r >> 28) & 0x1;
400}
401static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
402{
403 return 0x00000001;
404}
405static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
406{
407 return 0x10000000;
408}
409static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
410{
411 return (r >> 29) & 0x1;
412}
413static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
414{
415 return 0x00000001;
416}
417static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
418{
419 return 0x20000000;
420}
421static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
422{
423 return (r >> 30) & 0x1;
424}
425static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
426{
427 return 0x00000001;
428}
429static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
430{
431 return 0x40000000;
432}
433static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
434{
435 return 0x001402a0;
436}
437static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
438{
439 return (r >> 0) & 0x1;
440}
441static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
442{
443 return 0x00000001;
444}
445static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
446{
447 return 0x1;
448}
449static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
450{
451 return 0x001402a4;
452}
453static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
454{
455 return (r >> 0) & 0x1;
456}
457static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
462{
463 return 0x1;
464}
465static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
466{
467 return 0x001422a0;
468}
469static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
470{
471 return (r >> 0) & 0x1;
472}
473static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
474{
475 return 0x00000001;
476}
477static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
478{
479 return 0x1;
480}
481static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
482{
483 return 0x001422a4;
484}
485static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
486{
487 return (r >> 0) & 0x1;
488}
489static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
490{
491 return 0x00000001;
492}
493static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
494{
495 return 0x1;
496}
497#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_mc_gm206.h b/drivers/gpu/nvgpu/gm206/hw_mc_gm206.h
new file mode 100644
index 00000000..afbf556f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_mc_gm206.h
@@ -0,0 +1,281 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_mc_gm206_h_
51#define _hw_mc_gm206_h_
52
53static inline u32 mc_boot_0_r(void)
54{
55 return 0x00000000;
56}
57static inline u32 mc_boot_0_architecture_v(u32 r)
58{
59 return (r >> 24) & 0x1f;
60}
61static inline u32 mc_boot_0_implementation_v(u32 r)
62{
63 return (r >> 20) & 0xf;
64}
65static inline u32 mc_boot_0_major_revision_v(u32 r)
66{
67 return (r >> 4) & 0xf;
68}
69static inline u32 mc_boot_0_minor_revision_v(u32 r)
70{
71 return (r >> 0) & 0xf;
72}
73static inline u32 mc_intr_r(u32 i)
74{
75 return 0x00000100 + i*4;
76}
77static inline u32 mc_intr_pfifo_pending_f(void)
78{
79 return 0x100;
80}
81static inline u32 mc_intr_pmu_pending_f(void)
82{
83 return 0x1000000;
84}
85static inline u32 mc_intr_ltc_pending_f(void)
86{
87 return 0x2000000;
88}
89static inline u32 mc_intr_priv_ring_pending_f(void)
90{
91 return 0x40000000;
92}
93static inline u32 mc_intr_pbus_pending_f(void)
94{
95 return 0x10000000;
96}
97static inline u32 mc_intr_mask_0_r(void)
98{
99 return 0x00000640;
100}
101static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
102{
103 return 0x1000000;
104}
105static inline u32 mc_intr_en_0_r(void)
106{
107 return 0x00000140;
108}
109static inline u32 mc_intr_en_0_inta_disabled_f(void)
110{
111 return 0x0;
112}
113static inline u32 mc_intr_en_0_inta_hardware_f(void)
114{
115 return 0x1;
116}
117static inline u32 mc_intr_mask_1_r(void)
118{
119 return 0x00000644;
120}
121static inline u32 mc_intr_mask_1_pmu_s(void)
122{
123 return 1;
124}
125static inline u32 mc_intr_mask_1_pmu_f(u32 v)
126{
127 return (v & 0x1) << 24;
128}
129static inline u32 mc_intr_mask_1_pmu_m(void)
130{
131 return 0x1 << 24;
132}
133static inline u32 mc_intr_mask_1_pmu_v(u32 r)
134{
135 return (r >> 24) & 0x1;
136}
137static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
138{
139 return 0x1000000;
140}
141static inline u32 mc_intr_en_1_r(void)
142{
143 return 0x00000144;
144}
145static inline u32 mc_intr_en_1_inta_disabled_f(void)
146{
147 return 0x0;
148}
149static inline u32 mc_intr_en_1_inta_hardware_f(void)
150{
151 return 0x1;
152}
153static inline u32 mc_enable_r(void)
154{
155 return 0x00000200;
156}
157static inline u32 mc_enable_xbar_enabled_f(void)
158{
159 return 0x4;
160}
161static inline u32 mc_enable_l2_enabled_f(void)
162{
163 return 0x8;
164}
165static inline u32 mc_enable_pmedia_s(void)
166{
167 return 1;
168}
169static inline u32 mc_enable_pmedia_f(u32 v)
170{
171 return (v & 0x1) << 4;
172}
173static inline u32 mc_enable_pmedia_m(void)
174{
175 return 0x1 << 4;
176}
177static inline u32 mc_enable_pmedia_v(u32 r)
178{
179 return (r >> 4) & 0x1;
180}
181static inline u32 mc_enable_priv_ring_enabled_f(void)
182{
183 return 0x20;
184}
185static inline u32 mc_enable_ce0_m(void)
186{
187 return 0x1 << 6;
188}
189static inline u32 mc_enable_pfifo_enabled_f(void)
190{
191 return 0x100;
192}
193static inline u32 mc_enable_pgraph_enabled_f(void)
194{
195 return 0x1000;
196}
197static inline u32 mc_enable_pwr_v(u32 r)
198{
199 return (r >> 13) & 0x1;
200}
201static inline u32 mc_enable_pwr_disabled_v(void)
202{
203 return 0x00000000;
204}
205static inline u32 mc_enable_pwr_enabled_f(void)
206{
207 return 0x2000;
208}
209static inline u32 mc_enable_pfb_enabled_f(void)
210{
211 return 0x100000;
212}
213static inline u32 mc_enable_ce2_m(void)
214{
215 return 0x1 << 21;
216}
217static inline u32 mc_enable_ce2_enabled_f(void)
218{
219 return 0x200000;
220}
221static inline u32 mc_enable_blg_enabled_f(void)
222{
223 return 0x8000000;
224}
225static inline u32 mc_enable_perfmon_enabled_f(void)
226{
227 return 0x10000000;
228}
229static inline u32 mc_enable_hub_enabled_f(void)
230{
231 return 0x20000000;
232}
233static inline u32 mc_intr_ltc_r(void)
234{
235 return 0x0000017c;
236}
237static inline u32 mc_enable_pb_r(void)
238{
239 return 0x00000204;
240}
241static inline u32 mc_enable_pb_0_s(void)
242{
243 return 1;
244}
245static inline u32 mc_enable_pb_0_f(u32 v)
246{
247 return (v & 0x1) << 0;
248}
249static inline u32 mc_enable_pb_0_m(void)
250{
251 return 0x1 << 0;
252}
253static inline u32 mc_enable_pb_0_v(u32 r)
254{
255 return (r >> 0) & 0x1;
256}
257static inline u32 mc_enable_pb_0_enabled_v(void)
258{
259 return 0x00000001;
260}
261static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
262{
263 return (v & 0x1) << (0 + i*1);
264}
265static inline u32 mc_elpg_enable_r(void)
266{
267 return 0x0000020c;
268}
269static inline u32 mc_elpg_enable_xbar_enabled_f(void)
270{
271 return 0x4;
272}
273static inline u32 mc_elpg_enable_pfb_enabled_f(void)
274{
275 return 0x100000;
276}
277static inline u32 mc_elpg_enable_hub_enabled_f(void)
278{
279 return 0x20000000;
280}
281#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_pbdma_gm206.h b/drivers/gpu/nvgpu/gm206/hw_pbdma_gm206.h
new file mode 100644
index 00000000..ea8dad45
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_pbdma_gm206.h
@@ -0,0 +1,505 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pbdma_gm206_h_
51#define _hw_pbdma_gm206_h_
52
53static inline u32 pbdma_gp_entry1_r(void)
54{
55 return 0x10000004;
56}
57static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
58{
59 return (r >> 0) & 0xff;
60}
61static inline u32 pbdma_gp_entry1_length_f(u32 v)
62{
63 return (v & 0x1fffff) << 10;
64}
65static inline u32 pbdma_gp_entry1_length_v(u32 r)
66{
67 return (r >> 10) & 0x1fffff;
68}
69static inline u32 pbdma_gp_base_r(u32 i)
70{
71 return 0x00040048 + i*8192;
72}
73static inline u32 pbdma_gp_base__size_1_v(void)
74{
75 return 0x00000003;
76}
77static inline u32 pbdma_gp_base_offset_f(u32 v)
78{
79 return (v & 0x1fffffff) << 3;
80}
81static inline u32 pbdma_gp_base_rsvd_s(void)
82{
83 return 3;
84}
85static inline u32 pbdma_gp_base_hi_r(u32 i)
86{
87 return 0x0004004c + i*8192;
88}
89static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
90{
91 return (v & 0xff) << 0;
92}
93static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
94{
95 return (v & 0x1f) << 16;
96}
97static inline u32 pbdma_gp_fetch_r(u32 i)
98{
99 return 0x00040050 + i*8192;
100}
101static inline u32 pbdma_gp_get_r(u32 i)
102{
103 return 0x00040014 + i*8192;
104}
105static inline u32 pbdma_gp_put_r(u32 i)
106{
107 return 0x00040000 + i*8192;
108}
109static inline u32 pbdma_pb_fetch_r(u32 i)
110{
111 return 0x00040054 + i*8192;
112}
113static inline u32 pbdma_pb_fetch_hi_r(u32 i)
114{
115 return 0x00040058 + i*8192;
116}
117static inline u32 pbdma_get_r(u32 i)
118{
119 return 0x00040018 + i*8192;
120}
121static inline u32 pbdma_get_hi_r(u32 i)
122{
123 return 0x0004001c + i*8192;
124}
125static inline u32 pbdma_put_r(u32 i)
126{
127 return 0x0004005c + i*8192;
128}
129static inline u32 pbdma_put_hi_r(u32 i)
130{
131 return 0x00040060 + i*8192;
132}
133static inline u32 pbdma_formats_r(u32 i)
134{
135 return 0x0004009c + i*8192;
136}
137static inline u32 pbdma_formats_gp_fermi0_f(void)
138{
139 return 0x0;
140}
141static inline u32 pbdma_formats_pb_fermi1_f(void)
142{
143 return 0x100;
144}
145static inline u32 pbdma_formats_mp_fermi0_f(void)
146{
147 return 0x0;
148}
149static inline u32 pbdma_pb_header_r(u32 i)
150{
151 return 0x00040084 + i*8192;
152}
153static inline u32 pbdma_pb_header_priv_user_f(void)
154{
155 return 0x0;
156}
157static inline u32 pbdma_pb_header_method_zero_f(void)
158{
159 return 0x0;
160}
161static inline u32 pbdma_pb_header_subchannel_zero_f(void)
162{
163 return 0x0;
164}
165static inline u32 pbdma_pb_header_level_main_f(void)
166{
167 return 0x0;
168}
169static inline u32 pbdma_pb_header_first_true_f(void)
170{
171 return 0x400000;
172}
173static inline u32 pbdma_pb_header_type_inc_f(void)
174{
175 return 0x20000000;
176}
177static inline u32 pbdma_pb_header_type_non_inc_f(void)
178{
179 return 0x60000000;
180}
181static inline u32 pbdma_hdr_shadow_r(u32 i)
182{
183 return 0x00040118 + i*8192;
184}
185static inline u32 pbdma_subdevice_r(u32 i)
186{
187 return 0x00040094 + i*8192;
188}
189static inline u32 pbdma_subdevice_id_f(u32 v)
190{
191 return (v & 0xfff) << 0;
192}
193static inline u32 pbdma_subdevice_status_active_f(void)
194{
195 return 0x10000000;
196}
197static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
198{
199 return 0x20000000;
200}
201static inline u32 pbdma_method0_r(u32 i)
202{
203 return 0x000400c0 + i*8192;
204}
205static inline u32 pbdma_method0_fifo_size_v(void)
206{
207 return 0x00000004;
208}
209static inline u32 pbdma_method0_addr_f(u32 v)
210{
211 return (v & 0xfff) << 2;
212}
213static inline u32 pbdma_method0_addr_v(u32 r)
214{
215 return (r >> 2) & 0xfff;
216}
217static inline u32 pbdma_method0_subch_v(u32 r)
218{
219 return (r >> 16) & 0x7;
220}
221static inline u32 pbdma_method0_first_true_f(void)
222{
223 return 0x400000;
224}
225static inline u32 pbdma_method0_valid_true_f(void)
226{
227 return 0x80000000;
228}
229static inline u32 pbdma_method1_r(u32 i)
230{
231 return 0x000400c8 + i*8192;
232}
233static inline u32 pbdma_method2_r(u32 i)
234{
235 return 0x000400d0 + i*8192;
236}
237static inline u32 pbdma_method3_r(u32 i)
238{
239 return 0x000400d8 + i*8192;
240}
241static inline u32 pbdma_data0_r(u32 i)
242{
243 return 0x000400c4 + i*8192;
244}
245static inline u32 pbdma_target_r(u32 i)
246{
247 return 0x000400ac + i*8192;
248}
249static inline u32 pbdma_target_engine_sw_f(void)
250{
251 return 0x1f;
252}
253static inline u32 pbdma_acquire_r(u32 i)
254{
255 return 0x00040030 + i*8192;
256}
257static inline u32 pbdma_acquire_retry_man_2_f(void)
258{
259 return 0x2;
260}
261static inline u32 pbdma_acquire_retry_exp_2_f(void)
262{
263 return 0x100;
264}
265static inline u32 pbdma_acquire_timeout_exp_max_f(void)
266{
267 return 0x7800;
268}
269static inline u32 pbdma_acquire_timeout_man_max_f(void)
270{
271 return 0x7fff8000;
272}
273static inline u32 pbdma_acquire_timeout_en_disable_f(void)
274{
275 return 0x0;
276}
277static inline u32 pbdma_status_r(u32 i)
278{
279 return 0x00040100 + i*8192;
280}
281static inline u32 pbdma_channel_r(u32 i)
282{
283 return 0x00040120 + i*8192;
284}
285static inline u32 pbdma_signature_r(u32 i)
286{
287 return 0x00040010 + i*8192;
288}
289static inline u32 pbdma_signature_hw_valid_f(void)
290{
291 return 0xface;
292}
293static inline u32 pbdma_signature_sw_zero_f(void)
294{
295 return 0x0;
296}
297static inline u32 pbdma_userd_r(u32 i)
298{
299 return 0x00040008 + i*8192;
300}
301static inline u32 pbdma_userd_target_vid_mem_f(void)
302{
303 return 0x0;
304}
305static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
306{
307 return 0x2;
308}
309static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
310{
311 return 0x3;
312}
313static inline u32 pbdma_userd_addr_f(u32 v)
314{
315 return (v & 0x7fffff) << 9;
316}
317static inline u32 pbdma_userd_hi_r(u32 i)
318{
319 return 0x0004000c + i*8192;
320}
321static inline u32 pbdma_userd_hi_addr_f(u32 v)
322{
323 return (v & 0xff) << 0;
324}
325static inline u32 pbdma_hce_ctrl_r(u32 i)
326{
327 return 0x000400e4 + i*8192;
328}
329static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
330{
331 return 0x20;
332}
333static inline u32 pbdma_intr_0_r(u32 i)
334{
335 return 0x00040108 + i*8192;
336}
337static inline u32 pbdma_intr_0_memreq_v(u32 r)
338{
339 return (r >> 0) & 0x1;
340}
341static inline u32 pbdma_intr_0_memreq_pending_f(void)
342{
343 return 0x1;
344}
345static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
346{
347 return 0x2;
348}
349static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
350{
351 return 0x4;
352}
353static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
354{
355 return 0x8;
356}
357static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
358{
359 return 0x10;
360}
361static inline u32 pbdma_intr_0_memflush_pending_f(void)
362{
363 return 0x20;
364}
365static inline u32 pbdma_intr_0_memop_pending_f(void)
366{
367 return 0x40;
368}
369static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
370{
371 return 0x80;
372}
373static inline u32 pbdma_intr_0_lbreq_pending_f(void)
374{
375 return 0x100;
376}
377static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
378{
379 return 0x200;
380}
381static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
382{
383 return 0x400;
384}
385static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
386{
387 return 0x800;
388}
389static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
390{
391 return 0x1000;
392}
393static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
394{
395 return 0x2000;
396}
397static inline u32 pbdma_intr_0_gpptr_pending_f(void)
398{
399 return 0x4000;
400}
401static inline u32 pbdma_intr_0_gpentry_pending_f(void)
402{
403 return 0x8000;
404}
405static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
406{
407 return 0x10000;
408}
409static inline u32 pbdma_intr_0_pbptr_pending_f(void)
410{
411 return 0x20000;
412}
413static inline u32 pbdma_intr_0_pbentry_pending_f(void)
414{
415 return 0x40000;
416}
417static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
418{
419 return 0x80000;
420}
421static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
422{
423 return 0x100000;
424}
425static inline u32 pbdma_intr_0_method_pending_f(void)
426{
427 return 0x200000;
428}
429static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
430{
431 return 0x400000;
432}
433static inline u32 pbdma_intr_0_device_pending_f(void)
434{
435 return 0x800000;
436}
437static inline u32 pbdma_intr_0_semaphore_pending_f(void)
438{
439 return 0x2000000;
440}
441static inline u32 pbdma_intr_0_acquire_pending_f(void)
442{
443 return 0x4000000;
444}
445static inline u32 pbdma_intr_0_pri_pending_f(void)
446{
447 return 0x8000000;
448}
449static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
450{
451 return 0x20000000;
452}
453static inline u32 pbdma_intr_0_pbseg_pending_f(void)
454{
455 return 0x40000000;
456}
457static inline u32 pbdma_intr_0_signature_pending_f(void)
458{
459 return 0x80000000;
460}
461static inline u32 pbdma_intr_1_r(u32 i)
462{
463 return 0x00040148 + i*8192;
464}
465static inline u32 pbdma_intr_en_0_r(u32 i)
466{
467 return 0x0004010c + i*8192;
468}
469static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
470{
471 return 0x100;
472}
473static inline u32 pbdma_intr_en_1_r(u32 i)
474{
475 return 0x0004014c + i*8192;
476}
477static inline u32 pbdma_intr_stall_r(u32 i)
478{
479 return 0x0004013c + i*8192;
480}
481static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
482{
483 return 0x100;
484}
485static inline u32 pbdma_udma_nop_r(void)
486{
487 return 0x00000008;
488}
489static inline u32 pbdma_runlist_timeslice_r(u32 i)
490{
491 return 0x000400f8 + i*8192;
492}
493static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
494{
495 return 0x80;
496}
497static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
498{
499 return 0x3000;
500}
501static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
502{
503 return 0x10000000;
504}
505#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_perf_gm206.h b/drivers/gpu/nvgpu/gm206/hw_perf_gm206.h
new file mode 100644
index 00000000..5ac573c7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_perf_gm206.h
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_perf_gm206_h_
51#define _hw_perf_gm206_h_
52
53static inline u32 perf_pmasys_control_r(void)
54{
55 return 0x001b4000;
56}
57static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
58{
59 return (r >> 4) & 0x1;
60}
61static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
66{
67 return 0x10;
68}
69static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
70{
71 return (v & 0x1) << 5;
72}
73static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
74{
75 return (r >> 5) & 0x1;
76}
77static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
82{
83 return 0x20;
84}
85static inline u32 perf_pmasys_mem_block_r(void)
86{
87 return 0x001b4070;
88}
89static inline u32 perf_pmasys_mem_block_base_f(u32 v)
90{
91 return (v & 0xfffffff) << 0;
92}
93static inline u32 perf_pmasys_mem_block_target_f(u32 v)
94{
95 return (v & 0x3) << 28;
96}
97static inline u32 perf_pmasys_mem_block_target_v(u32 r)
98{
99 return (r >> 28) & 0x3;
100}
101static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
106{
107 return 0x0;
108}
109static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
118{
119 return 0x00000003;
120}
121static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
122{
123 return 0x30000000;
124}
125static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
126{
127 return (v & 0x1) << 31;
128}
129static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
130{
131 return (r >> 31) & 0x1;
132}
133static inline u32 perf_pmasys_mem_block_valid_true_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 perf_pmasys_mem_block_valid_true_f(void)
138{
139 return 0x80000000;
140}
141static inline u32 perf_pmasys_mem_block_valid_false_v(void)
142{
143 return 0x00000000;
144}
145static inline u32 perf_pmasys_mem_block_valid_false_f(void)
146{
147 return 0x0;
148}
149static inline u32 perf_pmasys_outbase_r(void)
150{
151 return 0x001b4074;
152}
153static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
154{
155 return (v & 0x7ffffff) << 5;
156}
157static inline u32 perf_pmasys_outbaseupper_r(void)
158{
159 return 0x001b4078;
160}
161static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
162{
163 return (v & 0xff) << 0;
164}
165static inline u32 perf_pmasys_outsize_r(void)
166{
167 return 0x001b407c;
168}
169static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
170{
171 return (v & 0x7ffffff) << 5;
172}
173static inline u32 perf_pmasys_mem_bytes_r(void)
174{
175 return 0x001b4084;
176}
177static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
178{
179 return (v & 0xfffffff) << 4;
180}
181static inline u32 perf_pmasys_mem_bump_r(void)
182{
183 return 0x001b4088;
184}
185static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
186{
187 return (v & 0xfffffff) << 4;
188}
189static inline u32 perf_pmasys_enginestatus_r(void)
190{
191 return 0x001b40a4;
192}
193static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
194{
195 return (v & 0x1) << 4;
196}
197static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
198{
199 return 0x00000001;
200}
201static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
202{
203 return 0x10;
204}
205#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_pri_ringmaster_gm206.h b/drivers/gpu/nvgpu/gm206/hw_pri_ringmaster_gm206.h
new file mode 100644
index 00000000..6dcd9434
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_pri_ringmaster_gm206.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringmaster_gm206_h_
51#define _hw_pri_ringmaster_gm206_h_
52
53static inline u32 pri_ringmaster_command_r(void)
54{
55 return 0x0012004c;
56}
57static inline u32 pri_ringmaster_command_cmd_m(void)
58{
59 return 0x3f << 0;
60}
61static inline u32 pri_ringmaster_command_cmd_v(u32 r)
62{
63 return (r >> 0) & 0x3f;
64}
65static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
66{
67 return 0x00000000;
68}
69static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
70{
71 return 0x1;
72}
73static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
74{
75 return 0x2;
76}
77static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
78{
79 return 0x3;
80}
81static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
82{
83 return 0x0;
84}
85static inline u32 pri_ringmaster_command_data_r(void)
86{
87 return 0x00120048;
88}
89static inline u32 pri_ringmaster_start_results_r(void)
90{
91 return 0x00120050;
92}
93static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
98{
99 return 0x00000001;
100}
101static inline u32 pri_ringmaster_intr_status0_r(void)
102{
103 return 0x00120058;
104}
105static inline u32 pri_ringmaster_intr_status1_r(void)
106{
107 return 0x0012005c;
108}
109static inline u32 pri_ringmaster_global_ctl_r(void)
110{
111 return 0x00120060;
112}
113static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
114{
115 return 0x1;
116}
117static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
118{
119 return 0x0;
120}
121static inline u32 pri_ringmaster_enum_fbp_r(void)
122{
123 return 0x00120074;
124}
125static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
126{
127 return (r >> 0) & 0x1f;
128}
129static inline u32 pri_ringmaster_enum_gpc_r(void)
130{
131 return 0x00120078;
132}
133static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
134{
135 return (r >> 0) & 0x1f;
136}
137static inline u32 pri_ringmaster_enum_ltc_r(void)
138{
139 return 0x0012006c;
140}
141static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
142{
143 return (r >> 0) & 0x1f;
144}
145#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_pri_ringstation_sys_gm206.h b/drivers/gpu/nvgpu/gm206/hw_pri_ringstation_sys_gm206.h
new file mode 100644
index 00000000..94efe04f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_pri_ringstation_sys_gm206.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_sys_gm206_h_
51#define _hw_pri_ringstation_sys_gm206_h_
52
53static inline u32 pri_ringstation_sys_master_config_r(u32 i)
54{
55 return 0x00122300 + i*4;
56}
57static inline u32 pri_ringstation_sys_decode_config_r(void)
58{
59 return 0x00122204;
60}
61static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
62{
63 return 0x7 << 0;
64}
65static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
66{
67 return 0x1;
68}
69#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h
new file mode 100644
index 00000000..2f4187d0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_proj_gm206_h_
51#define _hw_proj_gm206_h_
52
53static inline u32 proj_gpc_base_v(void)
54{
55 return 0x00500000;
56}
57static inline u32 proj_gpc_shared_base_v(void)
58{
59 return 0x00418000;
60}
61static inline u32 proj_gpc_stride_v(void)
62{
63 return 0x00008000;
64}
65static inline u32 proj_ltc_stride_v(void)
66{
67 return 0x00002000;
68}
69static inline u32 proj_lts_stride_v(void)
70{
71 return 0x00000200;
72}
73static inline u32 proj_fbpa_stride_v(void)
74{
75 return 0x00004000;
76}
77static inline u32 proj_ppc_in_gpc_base_v(void)
78{
79 return 0x00003000;
80}
81static inline u32 proj_ppc_in_gpc_stride_v(void)
82{
83 return 0x00000200;
84}
85static inline u32 proj_rop_base_v(void)
86{
87 return 0x00410000;
88}
89static inline u32 proj_rop_shared_base_v(void)
90{
91 return 0x00408800;
92}
93static inline u32 proj_rop_stride_v(void)
94{
95 return 0x00000400;
96}
97static inline u32 proj_tpc_in_gpc_base_v(void)
98{
99 return 0x00004000;
100}
101static inline u32 proj_tpc_in_gpc_stride_v(void)
102{
103 return 0x00000800;
104}
105static inline u32 proj_tpc_in_gpc_shared_base_v(void)
106{
107 return 0x00001800;
108}
109static inline u32 proj_host_num_pbdma_v(void)
110{
111 return 0x00000003;
112}
113static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
114{
115 return 0x00000004;
116}
117static inline u32 proj_scal_litter_num_fbps_v(void)
118{
119 return 0x00000006;
120}
121static inline u32 proj_scal_litter_num_fbpas_v(void)
122{
123 return 0x00000006;
124}
125static inline u32 proj_scal_litter_num_gpcs_v(void)
126{
127 return 0x00000006;
128}
129static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
130{
131 return 0x00000002;
132}
133static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
134{
135 return 0x00000002;
136}
137static inline u32 proj_scal_litter_num_zcull_banks_v(void)
138{
139 return 0x00000004;
140}
141static inline u32 proj_scal_max_gpcs_v(void)
142{
143 return 0x00000020;
144}
145static inline u32 proj_scal_max_tpc_per_gpc_v(void)
146{
147 return 0x00000008;
148}
149#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_pwr_gm206.h b/drivers/gpu/nvgpu/gm206/hw_pwr_gm206.h
new file mode 100644
index 00000000..8e755fcf
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_pwr_gm206.h
@@ -0,0 +1,825 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pwr_gm206_h_
51#define _hw_pwr_gm206_h_
52
53static inline u32 pwr_falcon_irqsset_r(void)
54{
55 return 0x0010a000;
56}
57static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
58{
59 return 0x40;
60}
61static inline u32 pwr_falcon_irqsclr_r(void)
62{
63 return 0x0010a004;
64}
65static inline u32 pwr_falcon_irqstat_r(void)
66{
67 return 0x0010a008;
68}
69static inline u32 pwr_falcon_irqstat_halt_true_f(void)
70{
71 return 0x10;
72}
73static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
74{
75 return 0x20;
76}
77static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
78{
79 return 0x40;
80}
81static inline u32 pwr_falcon_irqmode_r(void)
82{
83 return 0x0010a00c;
84}
85static inline u32 pwr_falcon_irqmset_r(void)
86{
87 return 0x0010a010;
88}
89static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
90{
91 return (v & 0x1) << 0;
92}
93static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
94{
95 return (v & 0x1) << 1;
96}
97static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
98{
99 return (v & 0x1) << 2;
100}
101static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
102{
103 return (v & 0x1) << 3;
104}
105static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
106{
107 return (v & 0x1) << 4;
108}
109static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
110{
111 return (v & 0x1) << 5;
112}
113static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
114{
115 return (v & 0x1) << 6;
116}
117static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
118{
119 return (v & 0x1) << 7;
120}
121static inline u32 pwr_falcon_irqmclr_r(void)
122{
123 return 0x0010a014;
124}
125static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
126{
127 return (v & 0x1) << 0;
128}
129static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
130{
131 return (v & 0x1) << 1;
132}
133static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
138{
139 return (v & 0x1) << 3;
140}
141static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
142{
143 return (v & 0x1) << 4;
144}
145static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
146{
147 return (v & 0x1) << 5;
148}
149static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
150{
151 return (v & 0x1) << 6;
152}
153static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
154{
155 return (v & 0x1) << 7;
156}
157static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
158{
159 return (v & 0xff) << 8;
160}
161static inline u32 pwr_falcon_irqmask_r(void)
162{
163 return 0x0010a018;
164}
165static inline u32 pwr_falcon_irqdest_r(void)
166{
167 return 0x0010a01c;
168}
169static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
170{
171 return (v & 0x1) << 0;
172}
173static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
174{
175 return (v & 0x1) << 1;
176}
177static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
178{
179 return (v & 0x1) << 2;
180}
181static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
182{
183 return (v & 0x1) << 3;
184}
185static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
186{
187 return (v & 0x1) << 4;
188}
189static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
190{
191 return (v & 0x1) << 5;
192}
193static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
198{
199 return (v & 0x1) << 7;
200}
201static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
202{
203 return (v & 0xff) << 8;
204}
205static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
206{
207 return (v & 0x1) << 16;
208}
209static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
210{
211 return (v & 0x1) << 17;
212}
213static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
214{
215 return (v & 0x1) << 18;
216}
217static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
218{
219 return (v & 0x1) << 19;
220}
221static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
222{
223 return (v & 0x1) << 20;
224}
225static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
226{
227 return (v & 0x1) << 21;
228}
229static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
230{
231 return (v & 0x1) << 22;
232}
233static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
234{
235 return (v & 0x1) << 23;
236}
237static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
238{
239 return (v & 0xff) << 24;
240}
241static inline u32 pwr_falcon_curctx_r(void)
242{
243 return 0x0010a050;
244}
245static inline u32 pwr_falcon_nxtctx_r(void)
246{
247 return 0x0010a054;
248}
249static inline u32 pwr_falcon_mailbox0_r(void)
250{
251 return 0x0010a040;
252}
253static inline u32 pwr_falcon_mailbox1_r(void)
254{
255 return 0x0010a044;
256}
257static inline u32 pwr_falcon_itfen_r(void)
258{
259 return 0x0010a048;
260}
261static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
262{
263 return 0x1;
264}
265static inline u32 pwr_falcon_idlestate_r(void)
266{
267 return 0x0010a04c;
268}
269static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
270{
271 return (r >> 0) & 0x1;
272}
273static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
274{
275 return (r >> 1) & 0x7fff;
276}
277static inline u32 pwr_falcon_os_r(void)
278{
279 return 0x0010a080;
280}
281static inline u32 pwr_falcon_engctl_r(void)
282{
283 return 0x0010a0a4;
284}
285static inline u32 pwr_falcon_cpuctl_r(void)
286{
287 return 0x0010a100;
288}
289static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
290{
291 return (v & 0x1) << 1;
292}
293static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
294{
295 return (v & 0x1) << 4;
296}
297static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
298{
299 return 0x1 << 4;
300}
301static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
302{
303 return (r >> 4) & 0x1;
304}
305static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
306{
307 return (v & 0x1) << 6;
308}
309static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
310{
311 return 0x1 << 6;
312}
313static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
314{
315 return (r >> 6) & 0x1;
316}
317static inline u32 pwr_falcon_cpuctl_alias_r(void)
318{
319 return 0x0010a130;
320}
321static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
322{
323 return (v & 0x1) << 1;
324}
325static inline u32 pwr_pmu_scpctl_stat_r(void)
326{
327 return 0x0010ac08;
328}
329static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
330{
331 return (v & 0x1) << 20;
332}
333static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
334{
335 return 0x1 << 20;
336}
337static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
338{
339 return (r >> 20) & 0x1;
340}
341static inline u32 pwr_falcon_imemc_r(u32 i)
342{
343 return 0x0010a180 + i*16;
344}
345static inline u32 pwr_falcon_imemc_offs_f(u32 v)
346{
347 return (v & 0x3f) << 2;
348}
349static inline u32 pwr_falcon_imemc_blk_f(u32 v)
350{
351 return (v & 0xff) << 8;
352}
353static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
354{
355 return (v & 0x1) << 24;
356}
357static inline u32 pwr_falcon_imemd_r(u32 i)
358{
359 return 0x0010a184 + i*16;
360}
361static inline u32 pwr_falcon_imemt_r(u32 i)
362{
363 return 0x0010a188 + i*16;
364}
365static inline u32 pwr_falcon_sctl_r(void)
366{
367 return 0x0010a240;
368}
369static inline u32 pwr_falcon_mmu_phys_sec_r(void)
370{
371 return 0x00100ce4;
372}
373static inline u32 pwr_falcon_bootvec_r(void)
374{
375 return 0x0010a104;
376}
377static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
378{
379 return (v & 0xffffffff) << 0;
380}
381static inline u32 pwr_falcon_dmactl_r(void)
382{
383 return 0x0010a10c;
384}
385static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
386{
387 return 0x1 << 1;
388}
389static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
390{
391 return 0x1 << 2;
392}
393static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
394{
395 return (v & 0x1) << 0;
396}
397static inline u32 pwr_falcon_hwcfg_r(void)
398{
399 return 0x0010a108;
400}
401static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
402{
403 return (r >> 0) & 0x1ff;
404}
405static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
406{
407 return (r >> 9) & 0x1ff;
408}
409static inline u32 pwr_falcon_dmatrfbase_r(void)
410{
411 return 0x0010a110;
412}
413static inline u32 pwr_falcon_dmatrfmoffs_r(void)
414{
415 return 0x0010a114;
416}
417static inline u32 pwr_falcon_dmatrfcmd_r(void)
418{
419 return 0x0010a118;
420}
421static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
422{
423 return (v & 0x1) << 4;
424}
425static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
426{
427 return (v & 0x1) << 5;
428}
429static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
430{
431 return (v & 0x7) << 8;
432}
433static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
434{
435 return (v & 0x7) << 12;
436}
437static inline u32 pwr_falcon_dmatrffboffs_r(void)
438{
439 return 0x0010a11c;
440}
441static inline u32 pwr_falcon_exterraddr_r(void)
442{
443 return 0x0010a168;
444}
445static inline u32 pwr_falcon_exterrstat_r(void)
446{
447 return 0x0010a16c;
448}
449static inline u32 pwr_falcon_exterrstat_valid_m(void)
450{
451 return 0x1 << 31;
452}
453static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
454{
455 return (r >> 31) & 0x1;
456}
457static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
462{
463 return 0x0010a200;
464}
465static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
466{
467 return 4;
468}
469static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
470{
471 return (v & 0xf) << 0;
472}
473static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
474{
475 return 0xf << 0;
476}
477static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
478{
479 return (r >> 0) & 0xf;
480}
481static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
482{
483 return 0x8;
484}
485static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
486{
487 return 0xe;
488}
489static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
490{
491 return (v & 0x1f) << 8;
492}
493static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
494{
495 return 0x0010a20c;
496}
497static inline u32 pwr_falcon_dmemc_r(u32 i)
498{
499 return 0x0010a1c0 + i*8;
500}
501static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
502{
503 return (v & 0x3f) << 2;
504}
505static inline u32 pwr_falcon_dmemc_offs_m(void)
506{
507 return 0x3f << 2;
508}
509static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
510{
511 return (v & 0xff) << 8;
512}
513static inline u32 pwr_falcon_dmemc_blk_m(void)
514{
515 return 0xff << 8;
516}
517static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
518{
519 return (v & 0x1) << 24;
520}
521static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
522{
523 return (v & 0x1) << 25;
524}
525static inline u32 pwr_falcon_dmemd_r(u32 i)
526{
527 return 0x0010a1c4 + i*8;
528}
529static inline u32 pwr_pmu_new_instblk_r(void)
530{
531 return 0x0010a480;
532}
533static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
534{
535 return (v & 0xfffffff) << 0;
536}
537static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
538{
539 return 0x0;
540}
541static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
542{
543 return 0x20000000;
544}
545static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
546{
547 return 0x30000000;
548}
549static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
550{
551 return (v & 0x1) << 30;
552}
553static inline u32 pwr_pmu_mutex_id_r(void)
554{
555 return 0x0010a488;
556}
557static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
558{
559 return (r >> 0) & 0xff;
560}
561static inline u32 pwr_pmu_mutex_id_value_init_v(void)
562{
563 return 0x00000000;
564}
565static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
566{
567 return 0x000000ff;
568}
569static inline u32 pwr_pmu_mutex_id_release_r(void)
570{
571 return 0x0010a48c;
572}
573static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
574{
575 return (v & 0xff) << 0;
576}
577static inline u32 pwr_pmu_mutex_id_release_value_m(void)
578{
579 return 0xff << 0;
580}
581static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
582{
583 return 0x00000000;
584}
585static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
586{
587 return 0x0;
588}
589static inline u32 pwr_pmu_mutex_r(u32 i)
590{
591 return 0x0010a580 + i*4;
592}
593static inline u32 pwr_pmu_mutex__size_1_v(void)
594{
595 return 0x00000010;
596}
597static inline u32 pwr_pmu_mutex_value_f(u32 v)
598{
599 return (v & 0xff) << 0;
600}
601static inline u32 pwr_pmu_mutex_value_v(u32 r)
602{
603 return (r >> 0) & 0xff;
604}
605static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
606{
607 return 0x0;
608}
609static inline u32 pwr_pmu_queue_head_r(u32 i)
610{
611 return 0x0010a4a0 + i*4;
612}
613static inline u32 pwr_pmu_queue_head__size_1_v(void)
614{
615 return 0x00000004;
616}
617static inline u32 pwr_pmu_queue_head_address_f(u32 v)
618{
619 return (v & 0xffffffff) << 0;
620}
621static inline u32 pwr_pmu_queue_head_address_v(u32 r)
622{
623 return (r >> 0) & 0xffffffff;
624}
625static inline u32 pwr_pmu_queue_tail_r(u32 i)
626{
627 return 0x0010a4b0 + i*4;
628}
629static inline u32 pwr_pmu_queue_tail__size_1_v(void)
630{
631 return 0x00000004;
632}
633static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
634{
635 return (v & 0xffffffff) << 0;
636}
637static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
638{
639 return (r >> 0) & 0xffffffff;
640}
641static inline u32 pwr_pmu_msgq_head_r(void)
642{
643 return 0x0010a4c8;
644}
645static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
646{
647 return (v & 0xffffffff) << 0;
648}
649static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
650{
651 return (r >> 0) & 0xffffffff;
652}
653static inline u32 pwr_pmu_msgq_tail_r(void)
654{
655 return 0x0010a4cc;
656}
657static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
658{
659 return (v & 0xffffffff) << 0;
660}
661static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
662{
663 return (r >> 0) & 0xffffffff;
664}
665static inline u32 pwr_pmu_idle_mask_r(u32 i)
666{
667 return 0x0010a504 + i*16;
668}
669static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
670{
671 return 0x1;
672}
673static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
674{
675 return 0x200000;
676}
677static inline u32 pwr_pmu_idle_count_r(u32 i)
678{
679 return 0x0010a508 + i*16;
680}
681static inline u32 pwr_pmu_idle_count_value_f(u32 v)
682{
683 return (v & 0x7fffffff) << 0;
684}
685static inline u32 pwr_pmu_idle_count_value_v(u32 r)
686{
687 return (r >> 0) & 0x7fffffff;
688}
689static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
690{
691 return (v & 0x1) << 31;
692}
693static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
694{
695 return 0x0010a50c + i*16;
696}
697static inline u32 pwr_pmu_idle_ctrl_value_m(void)
698{
699 return 0x3 << 0;
700}
701static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
702{
703 return 0x2;
704}
705static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
706{
707 return 0x3;
708}
709static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
710{
711 return 0x1 << 2;
712}
713static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
714{
715 return 0x0;
716}
717static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
718{
719 return 0x0010a9f0 + i*8;
720}
721static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
722{
723 return 0x0010a9f4 + i*8;
724}
725static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
726{
727 return 0x0010aa30 + i*8;
728}
729static inline u32 pwr_pmu_debug_r(u32 i)
730{
731 return 0x0010a5c0 + i*4;
732}
733static inline u32 pwr_pmu_debug__size_1_v(void)
734{
735 return 0x00000004;
736}
737static inline u32 pwr_pmu_mailbox_r(u32 i)
738{
739 return 0x0010a450 + i*4;
740}
741static inline u32 pwr_pmu_mailbox__size_1_v(void)
742{
743 return 0x0000000c;
744}
745static inline u32 pwr_pmu_bar0_addr_r(void)
746{
747 return 0x0010a7a0;
748}
749static inline u32 pwr_pmu_bar0_data_r(void)
750{
751 return 0x0010a7a4;
752}
753static inline u32 pwr_pmu_bar0_ctl_r(void)
754{
755 return 0x0010a7ac;
756}
757static inline u32 pwr_pmu_bar0_timeout_r(void)
758{
759 return 0x0010a7a8;
760}
761static inline u32 pwr_pmu_bar0_fecs_error_r(void)
762{
763 return 0x0010a988;
764}
765static inline u32 pwr_pmu_bar0_error_status_r(void)
766{
767 return 0x0010a7b0;
768}
769static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
770{
771 return 0x0010a6c0 + i*4;
772}
773static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
774{
775 return 0x0010a6e8 + i*4;
776}
777static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
778{
779 return 0x0010a710 + i*4;
780}
781static inline u32 pwr_pmu_pg_intren_r(u32 i)
782{
783 return 0x0010a760 + i*4;
784}
785static inline u32 pwr_fbif_transcfg_r(u32 i)
786{
787 return 0x0010ae00 + i*4;
788}
789static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
790{
791 return 0x0;
792}
793static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
794{
795 return 0x1;
796}
797static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
798{
799 return 0x2;
800}
801static inline u32 pwr_fbif_transcfg_mem_type_s(void)
802{
803 return 1;
804}
805static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
806{
807 return (v & 0x1) << 2;
808}
809static inline u32 pwr_fbif_transcfg_mem_type_m(void)
810{
811 return 0x1 << 2;
812}
813static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
814{
815 return (r >> 2) & 0x1;
816}
817static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
818{
819 return 0x0;
820}
821static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
822{
823 return 0x4;
824}
825#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_ram_gm206.h b/drivers/gpu/nvgpu/gm206/hw_ram_gm206.h
new file mode 100644
index 00000000..8007d8c2
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_ram_gm206.h
@@ -0,0 +1,445 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ram_gm206_h_
51#define _hw_ram_gm206_h_
52
53static inline u32 ram_in_ramfc_s(void)
54{
55 return 4096;
56}
57static inline u32 ram_in_ramfc_w(void)
58{
59 return 0;
60}
61static inline u32 ram_in_page_dir_base_target_f(u32 v)
62{
63 return (v & 0x3) << 0;
64}
65static inline u32 ram_in_page_dir_base_target_w(void)
66{
67 return 128;
68}
69static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
70{
71 return 0x0;
72}
73static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
74{
75 return 0x2;
76}
77static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
78{
79 return 0x3;
80}
81static inline u32 ram_in_page_dir_base_vol_w(void)
82{
83 return 128;
84}
85static inline u32 ram_in_page_dir_base_vol_true_f(void)
86{
87 return 0x4;
88}
89static inline u32 ram_in_big_page_size_f(u32 v)
90{
91 return (v & 0x1) << 11;
92}
93static inline u32 ram_in_big_page_size_m(void)
94{
95 return 0x1 << 11;
96}
97static inline u32 ram_in_big_page_size_w(void)
98{
99 return 128;
100}
101static inline u32 ram_in_big_page_size_128kb_f(void)
102{
103 return 0x0;
104}
105static inline u32 ram_in_big_page_size_64kb_f(void)
106{
107 return 0x800;
108}
109static inline u32 ram_in_page_dir_base_lo_f(u32 v)
110{
111 return (v & 0xfffff) << 12;
112}
113static inline u32 ram_in_page_dir_base_lo_w(void)
114{
115 return 128;
116}
117static inline u32 ram_in_page_dir_base_hi_f(u32 v)
118{
119 return (v & 0xff) << 0;
120}
121static inline u32 ram_in_page_dir_base_hi_w(void)
122{
123 return 129;
124}
125static inline u32 ram_in_adr_limit_lo_f(u32 v)
126{
127 return (v & 0xfffff) << 12;
128}
129static inline u32 ram_in_adr_limit_lo_w(void)
130{
131 return 130;
132}
133static inline u32 ram_in_adr_limit_hi_f(u32 v)
134{
135 return (v & 0xff) << 0;
136}
137static inline u32 ram_in_adr_limit_hi_w(void)
138{
139 return 131;
140}
141static inline u32 ram_in_engine_cs_w(void)
142{
143 return 132;
144}
145static inline u32 ram_in_engine_cs_wfi_v(void)
146{
147 return 0x00000000;
148}
149static inline u32 ram_in_engine_cs_wfi_f(void)
150{
151 return 0x0;
152}
153static inline u32 ram_in_engine_cs_fg_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 ram_in_engine_cs_fg_f(void)
158{
159 return 0x8;
160}
161static inline u32 ram_in_gr_cs_w(void)
162{
163 return 132;
164}
165static inline u32 ram_in_gr_cs_wfi_f(void)
166{
167 return 0x0;
168}
169static inline u32 ram_in_gr_wfi_target_w(void)
170{
171 return 132;
172}
173static inline u32 ram_in_gr_wfi_mode_w(void)
174{
175 return 132;
176}
177static inline u32 ram_in_gr_wfi_mode_physical_v(void)
178{
179 return 0x00000000;
180}
181static inline u32 ram_in_gr_wfi_mode_physical_f(void)
182{
183 return 0x0;
184}
185static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
186{
187 return 0x00000001;
188}
189static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
190{
191 return 0x4;
192}
193static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
194{
195 return (v & 0xfffff) << 12;
196}
197static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
198{
199 return 132;
200}
201static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
202{
203 return (v & 0xff) << 0;
204}
205static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
206{
207 return 133;
208}
209static inline u32 ram_in_base_shift_v(void)
210{
211 return 0x0000000c;
212}
213static inline u32 ram_in_alloc_size_v(void)
214{
215 return 0x00001000;
216}
217static inline u32 ram_fc_size_val_v(void)
218{
219 return 0x00000200;
220}
221static inline u32 ram_fc_gp_put_w(void)
222{
223 return 0;
224}
225static inline u32 ram_fc_userd_w(void)
226{
227 return 2;
228}
229static inline u32 ram_fc_userd_hi_w(void)
230{
231 return 3;
232}
233static inline u32 ram_fc_signature_w(void)
234{
235 return 4;
236}
237static inline u32 ram_fc_gp_get_w(void)
238{
239 return 5;
240}
241static inline u32 ram_fc_pb_get_w(void)
242{
243 return 6;
244}
245static inline u32 ram_fc_pb_get_hi_w(void)
246{
247 return 7;
248}
249static inline u32 ram_fc_pb_top_level_get_w(void)
250{
251 return 8;
252}
253static inline u32 ram_fc_pb_top_level_get_hi_w(void)
254{
255 return 9;
256}
257static inline u32 ram_fc_acquire_w(void)
258{
259 return 12;
260}
261static inline u32 ram_fc_semaphorea_w(void)
262{
263 return 14;
264}
265static inline u32 ram_fc_semaphoreb_w(void)
266{
267 return 15;
268}
269static inline u32 ram_fc_semaphorec_w(void)
270{
271 return 16;
272}
273static inline u32 ram_fc_semaphored_w(void)
274{
275 return 17;
276}
277static inline u32 ram_fc_gp_base_w(void)
278{
279 return 18;
280}
281static inline u32 ram_fc_gp_base_hi_w(void)
282{
283 return 19;
284}
285static inline u32 ram_fc_gp_fetch_w(void)
286{
287 return 20;
288}
289static inline u32 ram_fc_pb_fetch_w(void)
290{
291 return 21;
292}
293static inline u32 ram_fc_pb_fetch_hi_w(void)
294{
295 return 22;
296}
297static inline u32 ram_fc_pb_put_w(void)
298{
299 return 23;
300}
301static inline u32 ram_fc_pb_put_hi_w(void)
302{
303 return 24;
304}
305static inline u32 ram_fc_pb_header_w(void)
306{
307 return 33;
308}
309static inline u32 ram_fc_pb_count_w(void)
310{
311 return 34;
312}
313static inline u32 ram_fc_subdevice_w(void)
314{
315 return 37;
316}
317static inline u32 ram_fc_formats_w(void)
318{
319 return 39;
320}
321static inline u32 ram_fc_target_w(void)
322{
323 return 43;
324}
325static inline u32 ram_fc_hce_ctrl_w(void)
326{
327 return 57;
328}
329static inline u32 ram_fc_chid_w(void)
330{
331 return 58;
332}
333static inline u32 ram_fc_chid_id_f(u32 v)
334{
335 return (v & 0xfff) << 0;
336}
337static inline u32 ram_fc_chid_id_w(void)
338{
339 return 0;
340}
341static inline u32 ram_fc_runlist_timeslice_w(void)
342{
343 return 62;
344}
345static inline u32 ram_userd_base_shift_v(void)
346{
347 return 0x00000009;
348}
349static inline u32 ram_userd_chan_size_v(void)
350{
351 return 0x00000200;
352}
353static inline u32 ram_userd_put_w(void)
354{
355 return 16;
356}
357static inline u32 ram_userd_get_w(void)
358{
359 return 17;
360}
361static inline u32 ram_userd_ref_w(void)
362{
363 return 18;
364}
365static inline u32 ram_userd_put_hi_w(void)
366{
367 return 19;
368}
369static inline u32 ram_userd_ref_threshold_w(void)
370{
371 return 20;
372}
373static inline u32 ram_userd_top_level_get_w(void)
374{
375 return 22;
376}
377static inline u32 ram_userd_top_level_get_hi_w(void)
378{
379 return 23;
380}
381static inline u32 ram_userd_get_hi_w(void)
382{
383 return 24;
384}
385static inline u32 ram_userd_gp_get_w(void)
386{
387 return 34;
388}
389static inline u32 ram_userd_gp_put_w(void)
390{
391 return 35;
392}
393static inline u32 ram_userd_gp_top_level_get_w(void)
394{
395 return 22;
396}
397static inline u32 ram_userd_gp_top_level_get_hi_w(void)
398{
399 return 23;
400}
401static inline u32 ram_rl_entry_size_v(void)
402{
403 return 0x00000008;
404}
405static inline u32 ram_rl_entry_chid_f(u32 v)
406{
407 return (v & 0xfff) << 0;
408}
409static inline u32 ram_rl_entry_id_f(u32 v)
410{
411 return (v & 0xfff) << 0;
412}
413static inline u32 ram_rl_entry_type_f(u32 v)
414{
415 return (v & 0x1) << 13;
416}
417static inline u32 ram_rl_entry_type_chid_f(void)
418{
419 return 0x0;
420}
421static inline u32 ram_rl_entry_type_tsg_f(void)
422{
423 return 0x2000;
424}
425static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
426{
427 return (v & 0xf) << 14;
428}
429static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
430{
431 return 0xc000;
432}
433static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
434{
435 return (v & 0xff) << 18;
436}
437static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
438{
439 return 0x2000000;
440}
441static inline u32 ram_rl_entry_tsg_length_f(u32 v)
442{
443 return (v & 0x3f) << 26;
444}
445#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_timer_gm206.h b/drivers/gpu/nvgpu/gm206/hw_timer_gm206.h
new file mode 100644
index 00000000..68c32507
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_timer_gm206.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_timer_gm206_h_
51#define _hw_timer_gm206_h_
52
53static inline u32 timer_pri_timeout_r(void)
54{
55 return 0x00009080;
56}
57static inline u32 timer_pri_timeout_period_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 timer_pri_timeout_period_m(void)
62{
63 return 0xffffff << 0;
64}
65static inline u32 timer_pri_timeout_period_v(u32 r)
66{
67 return (r >> 0) & 0xffffff;
68}
69static inline u32 timer_pri_timeout_en_f(u32 v)
70{
71 return (v & 0x1) << 31;
72}
73static inline u32 timer_pri_timeout_en_m(void)
74{
75 return 0x1 << 31;
76}
77static inline u32 timer_pri_timeout_en_v(u32 r)
78{
79 return (r >> 31) & 0x1;
80}
81static inline u32 timer_pri_timeout_en_en_enabled_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 timer_pri_timeout_en_en_disabled_f(void)
86{
87 return 0x0;
88}
89static inline u32 timer_pri_timeout_save_0_r(void)
90{
91 return 0x00009084;
92}
93static inline u32 timer_pri_timeout_save_1_r(void)
94{
95 return 0x00009088;
96}
97static inline u32 timer_pri_timeout_fecs_errcode_r(void)
98{
99 return 0x0000908c;
100}
101static inline u32 timer_time_0_r(void)
102{
103 return 0x00009400;
104}
105static inline u32 timer_time_1_r(void)
106{
107 return 0x00009410;
108}
109#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_top_gm206.h b/drivers/gpu/nvgpu/gm206/hw_top_gm206.h
new file mode 100644
index 00000000..289f4411
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_top_gm206.h
@@ -0,0 +1,169 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_top_gm206_h_
51#define _hw_top_gm206_h_
52
53static inline u32 top_num_gpcs_r(void)
54{
55 return 0x00022430;
56}
57static inline u32 top_num_gpcs_value_v(u32 r)
58{
59 return (r >> 0) & 0x1f;
60}
61static inline u32 top_tpc_per_gpc_r(void)
62{
63 return 0x00022434;
64}
65static inline u32 top_tpc_per_gpc_value_v(u32 r)
66{
67 return (r >> 0) & 0x1f;
68}
69static inline u32 top_num_fbps_r(void)
70{
71 return 0x00022438;
72}
73static inline u32 top_num_fbps_value_v(u32 r)
74{
75 return (r >> 0) & 0x1f;
76}
77static inline u32 top_ltc_per_fbp_r(void)
78{
79 return 0x00022450;
80}
81static inline u32 top_ltc_per_fbp_value_v(u32 r)
82{
83 return (r >> 0) & 0x1f;
84}
85static inline u32 top_slices_per_ltc_r(void)
86{
87 return 0x0002245c;
88}
89static inline u32 top_slices_per_ltc_value_v(u32 r)
90{
91 return (r >> 0) & 0x1f;
92}
93static inline u32 top_num_ltcs_r(void)
94{
95 return 0x00022454;
96}
97static inline u32 top_device_info_r(u32 i)
98{
99 return 0x00022700 + i*4;
100}
101static inline u32 top_device_info__size_1_v(void)
102{
103 return 0x00000040;
104}
105static inline u32 top_device_info_chain_v(u32 r)
106{
107 return (r >> 31) & 0x1;
108}
109static inline u32 top_device_info_chain_enable_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 top_device_info_engine_enum_v(u32 r)
114{
115 return (r >> 26) & 0xf;
116}
117static inline u32 top_device_info_runlist_enum_v(u32 r)
118{
119 return (r >> 21) & 0xf;
120}
121static inline u32 top_device_info_intr_enum_v(u32 r)
122{
123 return (r >> 15) & 0x1f;
124}
125static inline u32 top_device_info_reset_enum_v(u32 r)
126{
127 return (r >> 9) & 0x1f;
128}
129static inline u32 top_device_info_type_enum_v(u32 r)
130{
131 return (r >> 2) & 0x1fffffff;
132}
133static inline u32 top_device_info_type_enum_graphics_v(void)
134{
135 return 0x00000000;
136}
137static inline u32 top_device_info_type_enum_graphics_f(void)
138{
139 return 0x0;
140}
141static inline u32 top_device_info_type_enum_copy0_v(void)
142{
143 return 0x00000001;
144}
145static inline u32 top_device_info_type_enum_copy0_f(void)
146{
147 return 0x4;
148}
149static inline u32 top_device_info_entry_v(u32 r)
150{
151 return (r >> 0) & 0x3;
152}
153static inline u32 top_device_info_entry_not_valid_v(void)
154{
155 return 0x00000000;
156}
157static inline u32 top_device_info_entry_enum_v(void)
158{
159 return 0x00000002;
160}
161static inline u32 top_scratch1_r(void)
162{
163 return 0x0002240c;
164}
165static inline u32 top_scratch1_devinit_completed_v(u32 r)
166{
167 return (r >> 1) & 0x1;
168}
169#endif
diff --git a/drivers/gpu/nvgpu/gm206/hw_xve_gm206.h b/drivers/gpu/nvgpu/gm206/hw_xve_gm206.h
new file mode 100644
index 00000000..e113dbeb
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hw_xve_gm206.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_xve_gm206_h_
51#define _hw_xve_gm206_h_
52
53static inline u32 xve_rom_ctrl_r(void)
54{
55 return 0x00000050;
56}
57static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
58{
59 return (v & 0x1) << 0;
60}
61static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
62{
63 return 0x0;
64}
65static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
66{
67 return 0x1;
68}
69#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 00:59:19 -0400