diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-07-05 16:55:46 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-07-07 07:11:57 -0400 |
commit | f4035d17a39ac356f3cbf8aecc2ba4c679dd6fb3 (patch) | |
tree | 757feb9a88caea9c6aa6b7853acbce6645f4edf1 /drivers | |
parent | ca9cb9715407d5e86228cf1b26e83b8dd6115385 (diff) |
gpu: nvgpu: gv11b: update code to HW CL 36758735
Update headers and corresponding code to work with
HW CL # 36758735
Bug 1735760
Change-Id: Ie26bfaa6377ab797c5ad978e4796a55334761b5d
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1175882
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 43 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 76 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | 164 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 802 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 74 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | 124 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 36 |
18 files changed, 1097 insertions, 416 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a23c5e8c..c5d2aa56 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -911,17 +911,6 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, | |||
911 | ctxsw_prog_main_image_magic_value_o()), | 911 | ctxsw_prog_main_image_magic_value_o()), |
912 | ctxsw_prog_main_image_magic_value_v_value_v()); | 912 | ctxsw_prog_main_image_magic_value_v_value_v()); |
913 | 913 | ||
914 | gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", | ||
915 | gk20a_mem_rd(g, mem, | ||
916 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o())); | ||
917 | |||
918 | gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", | ||
919 | gk20a_mem_rd(g, mem, | ||
920 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_o())); | ||
921 | |||
922 | gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", | ||
923 | gk20a_mem_rd(g, mem, | ||
924 | ctxsw_prog_main_image_context_timestamp_buffer_control_o())); | ||
925 | 914 | ||
926 | gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", | 915 | gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", |
927 | gk20a_mem_rd(g, mem, | 916 | gk20a_mem_rd(g, mem, |
@@ -1144,8 +1133,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1144 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", | 1133 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", |
1145 | gk20a_readl(g, gr_cwd_fs_r())); | 1134 | gk20a_readl(g, gr_cwd_fs_r())); |
1146 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", | 1135 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", |
1147 | gk20a_readl(g, gr_fe_tpc_fs_r(0))); | 1136 | gk20a_readl(g, gr_fe_tpc_fs_r())); |
1148 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n", | 1137 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n", |
1149 | gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); | 1138 | gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); |
1150 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", | 1139 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", |
1151 | gk20a_readl(g, gr_cwd_sm_id_r(0))); | 1140 | gk20a_readl(g, gr_cwd_sm_id_r(0))); |
@@ -1552,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1552 | gpc, tpc, global_esr); | 1541 | gpc, tpc, global_esr); |
1553 | 1542 | ||
1554 | if (cilp_enabled && sm_debugger_attached) { | 1543 | if (cilp_enabled && sm_debugger_attached) { |
1555 | if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f()) | 1544 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) |
1556 | gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset, | 1545 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
1557 | gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f()); | 1546 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); |
1558 | 1547 | ||
1559 | if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f()) | 1548 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) |
1560 | gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset, | 1549 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
1561 | gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f()); | 1550 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); |
1562 | 1551 | ||
1563 | global_mask = gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f() | | 1552 | global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() | |
1564 | gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(); | 1553 | gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(); |
1565 | 1554 | ||
1566 | if (warp_esr != 0 || (global_esr & global_mask) != 0) { | 1555 | if (warp_esr != 0 || (global_esr & global_mask) != 0) { |
1567 | *ignore_debugger = true; | 1556 | *ignore_debugger = true; |
@@ -1585,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1585 | } | 1574 | } |
1586 | 1575 | ||
1587 | /* reset the HWW errors after locking down */ | 1576 | /* reset the HWW errors after locking down */ |
1588 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset); | 1577 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); |
1589 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1578 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); |
1590 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1579 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1591 | "CILP: HWWs cleared for gpc %d tpc %d\n", | 1580 | "CILP: HWWs cleared for gpc %d tpc %d\n", |
@@ -1598,7 +1587,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1598 | return ret; | 1587 | return ret; |
1599 | } | 1588 | } |
1600 | 1589 | ||
1601 | dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset); | 1590 | dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); |
1602 | if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { | 1591 | if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { |
1603 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1592 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1604 | "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", | 1593 | "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", |
@@ -1606,7 +1595,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1606 | dbgr_control0 = set_field(dbgr_control0, | 1595 | dbgr_control0 = set_field(dbgr_control0, |
1607 | gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), | 1596 | gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), |
1608 | gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); | 1597 | gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); |
1609 | gk20a_writel(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset, dbgr_control0); | 1598 | gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); |
1610 | } | 1599 | } |
1611 | 1600 | ||
1612 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1601 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
@@ -1720,10 +1709,10 @@ clean_up: | |||
1720 | 1709 | ||
1721 | static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) | 1710 | static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) |
1722 | { | 1711 | { |
1723 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m())) | 1712 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) |
1724 | hww_warp_esr = set_field(hww_warp_esr, | 1713 | hww_warp_esr = set_field(hww_warp_esr, |
1725 | gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(), | 1714 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), |
1726 | gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f()); | 1715 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); |
1727 | 1716 | ||
1728 | return hww_warp_esr; | 1717 | return hww_warp_esr; |
1729 | } | 1718 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h index b6efacf3..c06a106a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | |||
@@ -50,30 +50,6 @@ | |||
50 | #ifndef _hw_bus_gv11b_h_ | 50 | #ifndef _hw_bus_gv11b_h_ |
51 | #define _hw_bus_gv11b_h_ | 51 | #define _hw_bus_gv11b_h_ |
52 | 52 | ||
53 | static inline u32 bus_bar0_window_r(void) | ||
54 | { | ||
55 | return 0x00001700; | ||
56 | } | ||
57 | static inline u32 bus_bar0_window_base_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xffffff) << 0; | ||
60 | } | ||
61 | static inline u32 bus_bar0_window_target_vid_mem_f(void) | ||
62 | { | ||
63 | return 0x0; | ||
64 | } | ||
65 | static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) | ||
66 | { | ||
67 | return 0x2000000; | ||
68 | } | ||
69 | static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) | ||
70 | { | ||
71 | return 0x3000000; | ||
72 | } | ||
73 | static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) | ||
74 | { | ||
75 | return 0x00000010; | ||
76 | } | ||
77 | static inline u32 bus_bar1_block_r(void) | 53 | static inline u32 bus_bar1_block_r(void) |
78 | { | 54 | { |
79 | return 0x00001704; | 55 | return 0x00001704; |
@@ -130,6 +106,58 @@ static inline u32 bus_bar2_block_ptr_shift_v(void) | |||
130 | { | 106 | { |
131 | return 0x0000000c; | 107 | return 0x0000000c; |
132 | } | 108 | } |
109 | static inline u32 bus_bind_status_r(void) | ||
110 | { | ||
111 | return 0x00001710; | ||
112 | } | ||
113 | static inline u32 bus_bind_status_bar1_pending_v(u32 r) | ||
114 | { | ||
115 | return (r >> 0) & 0x1; | ||
116 | } | ||
117 | static inline u32 bus_bind_status_bar1_pending_empty_f(void) | ||
118 | { | ||
119 | return 0x0; | ||
120 | } | ||
121 | static inline u32 bus_bind_status_bar1_pending_busy_f(void) | ||
122 | { | ||
123 | return 0x1; | ||
124 | } | ||
125 | static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) | ||
126 | { | ||
127 | return (r >> 1) & 0x1; | ||
128 | } | ||
129 | static inline u32 bus_bind_status_bar1_outstanding_false_f(void) | ||
130 | { | ||
131 | return 0x0; | ||
132 | } | ||
133 | static inline u32 bus_bind_status_bar1_outstanding_true_f(void) | ||
134 | { | ||
135 | return 0x2; | ||
136 | } | ||
137 | static inline u32 bus_bind_status_bar2_pending_v(u32 r) | ||
138 | { | ||
139 | return (r >> 2) & 0x1; | ||
140 | } | ||
141 | static inline u32 bus_bind_status_bar2_pending_empty_f(void) | ||
142 | { | ||
143 | return 0x0; | ||
144 | } | ||
145 | static inline u32 bus_bind_status_bar2_pending_busy_f(void) | ||
146 | { | ||
147 | return 0x4; | ||
148 | } | ||
149 | static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) | ||
150 | { | ||
151 | return (r >> 3) & 0x1; | ||
152 | } | ||
153 | static inline u32 bus_bind_status_bar2_outstanding_false_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 bus_bind_status_bar2_outstanding_true_f(void) | ||
158 | { | ||
159 | return 0x8; | ||
160 | } | ||
133 | static inline u32 bus_intr_0_r(void) | 161 | static inline u32 bus_intr_0_r(void) |
134 | { | 162 | { |
135 | return 0x00001100; | 163 | return 0x00001100; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h index 04055b8c..ed1e657c 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | |||
@@ -56,7 +56,7 @@ static inline u32 ccsr_channel_inst_r(u32 i) | |||
56 | } | 56 | } |
57 | static inline u32 ccsr_channel_inst__size_1_v(void) | 57 | static inline u32 ccsr_channel_inst__size_1_v(void) |
58 | { | 58 | { |
59 | return 0x00001000; | 59 | return 0x00000200; |
60 | } | 60 | } |
61 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) | 61 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) |
62 | { | 62 | { |
@@ -88,7 +88,7 @@ static inline u32 ccsr_channel_r(u32 i) | |||
88 | } | 88 | } |
89 | static inline u32 ccsr_channel__size_1_v(void) | 89 | static inline u32 ccsr_channel__size_1_v(void) |
90 | { | 90 | { |
91 | return 0x00001000; | 91 | return 0x00000200; |
92 | } | 92 | } |
93 | static inline u32 ccsr_channel_enable_v(u32 r) | 93 | static inline u32 ccsr_channel_enable_v(u32 r) |
94 | { | 94 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h index 5c60c30c..57a6b28d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | |||
@@ -290,168 +290,4 @@ static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_ | |||
290 | { | 290 | { |
291 | return 0x2; | 291 | return 0x2; |
292 | } | 292 | } |
293 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) | ||
294 | { | ||
295 | return 0x000000ac; | ||
296 | } | ||
297 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) | ||
298 | { | ||
299 | return (v & 0xffff) << 0; | ||
300 | } | ||
301 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) | ||
302 | { | ||
303 | return 0x000000b0; | ||
304 | } | ||
305 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) | ||
306 | { | ||
307 | return 0x1ffff << 0; | ||
308 | } | ||
309 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) | ||
310 | { | ||
311 | return 0x000000b4; | ||
312 | } | ||
313 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) | ||
314 | { | ||
315 | return (v & 0xffffffff) << 0; | ||
316 | } | ||
317 | static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) | ||
318 | { | ||
319 | return 0x00000080; | ||
320 | } | ||
321 | static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) | ||
322 | { | ||
323 | return 0x00000020; | ||
324 | } | ||
325 | static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) | ||
326 | { | ||
327 | return 0x00000000; | ||
328 | } | ||
329 | static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) | ||
330 | { | ||
331 | return 0x00000000; | ||
332 | } | ||
333 | static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) | ||
334 | { | ||
335 | return 0x00000004; | ||
336 | } | ||
337 | static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) | ||
338 | { | ||
339 | return 0x600dbeef; | ||
340 | } | ||
341 | static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) | ||
342 | { | ||
343 | return 0x00000008; | ||
344 | } | ||
345 | static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) | ||
346 | { | ||
347 | return 0x0000000c; | ||
348 | } | ||
349 | static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) | ||
350 | { | ||
351 | return 0x00000018; | ||
352 | } | ||
353 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) | ||
354 | { | ||
355 | return 0x0000001c; | ||
356 | } | ||
357 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) | ||
358 | { | ||
359 | return (v & 0xffffff) << 0; | ||
360 | } | ||
361 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) | ||
362 | { | ||
363 | return (r >> 0) & 0xffffff; | ||
364 | } | ||
365 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) | ||
366 | { | ||
367 | return (v & 0xff) << 24; | ||
368 | } | ||
369 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) | ||
370 | { | ||
371 | return 0xff << 24; | ||
372 | } | ||
373 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) | ||
374 | { | ||
375 | return (r >> 24) & 0xff; | ||
376 | } | ||
377 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) | ||
378 | { | ||
379 | return 0x00000001; | ||
380 | } | ||
381 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) | ||
382 | { | ||
383 | return 0x1000000; | ||
384 | } | ||
385 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) | ||
386 | { | ||
387 | return 0x00000002; | ||
388 | } | ||
389 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) | ||
390 | { | ||
391 | return 0x2000000; | ||
392 | } | ||
393 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) | ||
394 | { | ||
395 | return 0x0000000a; | ||
396 | } | ||
397 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) | ||
398 | { | ||
399 | return 0xa000000; | ||
400 | } | ||
401 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) | ||
402 | { | ||
403 | return 0x0000000b; | ||
404 | } | ||
405 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) | ||
406 | { | ||
407 | return 0xb000000; | ||
408 | } | ||
409 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) | ||
410 | { | ||
411 | return 0x0000000c; | ||
412 | } | ||
413 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) | ||
414 | { | ||
415 | return 0xc000000; | ||
416 | } | ||
417 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) | ||
418 | { | ||
419 | return 0x0000000d; | ||
420 | } | ||
421 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) | ||
422 | { | ||
423 | return 0xd000000; | ||
424 | } | ||
425 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) | ||
426 | { | ||
427 | return 0x00000003; | ||
428 | } | ||
429 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) | ||
430 | { | ||
431 | return 0x3000000; | ||
432 | } | ||
433 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) | ||
434 | { | ||
435 | return 0x00000004; | ||
436 | } | ||
437 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) | ||
438 | { | ||
439 | return 0x4000000; | ||
440 | } | ||
441 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) | ||
442 | { | ||
443 | return 0x00000005; | ||
444 | } | ||
445 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) | ||
446 | { | ||
447 | return 0x5000000; | ||
448 | } | ||
449 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) | ||
450 | { | ||
451 | return 0x000000ff; | ||
452 | } | ||
453 | static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) | ||
454 | { | ||
455 | return 0xff000000; | ||
456 | } | ||
457 | #endif | 293 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 0a5622b4..900054aa 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | |||
@@ -182,6 +182,10 @@ static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) | |||
182 | { | 182 | { |
183 | return 0x20; | 183 | return 0x20; |
184 | } | 184 | } |
185 | static inline u32 fb_mmu_invalidate_replay_cancel_f(void) | ||
186 | { | ||
187 | return 0x20; | ||
188 | } | ||
185 | static inline u32 fb_mmu_invalidate_sys_membar_s(void) | 189 | static inline u32 fb_mmu_invalidate_sys_membar_s(void) |
186 | { | 190 | { |
187 | return 1; | 191 | return 1; |
@@ -470,4 +474,8 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void) | |||
470 | { | 474 | { |
471 | return 0x00000001; | 475 | return 0x00000001; |
472 | } | 476 | } |
477 | static inline u32 fb_niso_flush_sysmem_addr_r(void) | ||
478 | { | ||
479 | return 0x00100c10; | ||
480 | } | ||
473 | #endif | 481 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 55960a4d..9c0f2483 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | |||
@@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i) | |||
104 | } | 104 | } |
105 | static inline u32 fifo_eng_runlist_base__size_1_v(void) | 105 | static inline u32 fifo_eng_runlist_base__size_1_v(void) |
106 | { | 106 | { |
107 | return 0x0000000d; | 107 | return 0x00000001; |
108 | } | 108 | } |
109 | static inline u32 fifo_eng_runlist_r(u32 i) | 109 | static inline u32 fifo_eng_runlist_r(u32 i) |
110 | { | 110 | { |
@@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i) | |||
112 | } | 112 | } |
113 | static inline u32 fifo_eng_runlist__size_1_v(void) | 113 | static inline u32 fifo_eng_runlist__size_1_v(void) |
114 | { | 114 | { |
115 | return 0x0000000d; | 115 | return 0x00000001; |
116 | } | 116 | } |
117 | static inline u32 fifo_eng_runlist_length_f(u32 v) | 117 | static inline u32 fifo_eng_runlist_length_f(u32 v) |
118 | { | 118 | { |
@@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void) | |||
268 | } | 268 | } |
269 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) | 269 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) |
270 | { | 270 | { |
271 | return 0x00000040; | 271 | return 0x00000000; |
272 | } | 272 | } |
273 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) | 273 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) |
274 | { | 274 | { |
@@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) | |||
332 | } | 332 | } |
333 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | 333 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) |
334 | { | 334 | { |
335 | return 0x0000000e; | 335 | return 0x00000001; |
336 | } | 336 | } |
337 | static inline u32 fifo_intr_runlist_r(void) | 337 | static inline u32 fifo_intr_runlist_r(void) |
338 | { | 338 | { |
@@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i) | |||
412 | } | 412 | } |
413 | static inline u32 fifo_engine_status__size_1_v(void) | 413 | static inline u32 fifo_engine_status__size_1_v(void) |
414 | { | 414 | { |
415 | return 0x0000000f; | 415 | return 0x00000002; |
416 | } | 416 | } |
417 | static inline u32 fifo_engine_status_id_v(u32 r) | 417 | static inline u32 fifo_engine_status_id_v(u32 r) |
418 | { | 418 | { |
@@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i) | |||
500 | } | 500 | } |
501 | static inline u32 fifo_pbdma_status__size_1_v(void) | 501 | static inline u32 fifo_pbdma_status__size_1_v(void) |
502 | { | 502 | { |
503 | return 0x0000000e; | 503 | return 0x00000001; |
504 | } | 504 | } |
505 | static inline u32 fifo_pbdma_status_id_v(u32 r) | 505 | static inline u32 fifo_pbdma_status_id_v(u32 r) |
506 | { | 506 | { |
@@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void) | |||
600 | } | 600 | } |
601 | static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) | 601 | static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) |
602 | { | 602 | { |
603 | return (v & 0x3fff) << 0; | 603 | return (v & 0x1ff) << 0; |
604 | } | 604 | } |
605 | static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) | 605 | static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) |
606 | { | 606 | { |
607 | return 0x00002000; | 607 | return 0x000000c0; |
608 | } | 608 | } |
609 | static inline u32 fifo_replay_fault_buffer_get_r(void) | 609 | static inline u32 fifo_replay_fault_buffer_get_r(void) |
610 | { | 610 | { |
@@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void) | |||
612 | } | 612 | } |
613 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) | 613 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) |
614 | { | 614 | { |
615 | return (v & 0x3fff) << 0; | 615 | return (v & 0x1ff) << 0; |
616 | } | 616 | } |
617 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) | 617 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) |
618 | { | 618 | { |
@@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void) | |||
624 | } | 624 | } |
625 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) | 625 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) |
626 | { | 626 | { |
627 | return (v & 0x3fff) << 0; | 627 | return (v & 0x1ff) << 0; |
628 | } | 628 | } |
629 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) | 629 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) |
630 | { | 630 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h index 75617e6e..280a048a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h | |||
@@ -124,7 +124,7 @@ static inline u32 fuse_status_opt_fbp_r(void) | |||
124 | } | 124 | } |
125 | static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) | 125 | static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) |
126 | { | 126 | { |
127 | return (r >> (0 + i*0)) & 0x1; | 127 | return (r >> (0 + i*1)) & 0x1; |
128 | } | 128 | } |
129 | static inline u32 fuse_opt_ecc_en_r(void) | 129 | static inline u32 fuse_opt_ecc_en_r(void) |
130 | { | 130 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index d54957eb..955626a6 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | |||
@@ -70,9 +70,17 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void) | |||
70 | { | 70 | { |
71 | return 0x2; | 71 | return 0x2; |
72 | } | 72 | } |
73 | static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) | ||
74 | { | ||
75 | return 0x4; | ||
76 | } | ||
77 | static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) | ||
78 | { | ||
79 | return 0x6; | ||
80 | } | ||
73 | static inline u32 gmmu_new_pde_address_sys_f(u32 v) | 81 | static inline u32 gmmu_new_pde_address_sys_f(u32 v) |
74 | { | 82 | { |
75 | return (v & 0xfffffff) << 8; | 83 | return (v & 0xffffff) << 8; |
76 | } | 84 | } |
77 | static inline u32 gmmu_new_pde_address_sys_w(void) | 85 | static inline u32 gmmu_new_pde_address_sys_w(void) |
78 | { | 86 | { |
@@ -118,6 +126,14 @@ static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) | |||
118 | { | 126 | { |
119 | return 0x2; | 127 | return 0x2; |
120 | } | 128 | } |
129 | static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) | ||
130 | { | ||
131 | return 0x4; | ||
132 | } | ||
133 | static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) | ||
134 | { | ||
135 | return 0x6; | ||
136 | } | ||
121 | static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) | 137 | static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) |
122 | { | 138 | { |
123 | return (v & 0xfffffff) << 4; | 139 | return (v & 0xfffffff) << 4; |
@@ -138,6 +154,14 @@ static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) | |||
138 | { | 154 | { |
139 | return 0x2; | 155 | return 0x2; |
140 | } | 156 | } |
157 | static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) | ||
158 | { | ||
159 | return 0x4; | ||
160 | } | ||
161 | static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) | ||
162 | { | ||
163 | return 0x6; | ||
164 | } | ||
141 | static inline u32 gmmu_new_dual_pde_vol_small_w(void) | 165 | static inline u32 gmmu_new_dual_pde_vol_small_w(void) |
142 | { | 166 | { |
143 | return 2; | 167 | return 2; |
@@ -164,7 +188,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) | |||
164 | } | 188 | } |
165 | static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) | 189 | static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) |
166 | { | 190 | { |
167 | return (v & 0xfffffff) << 8; | 191 | return (v & 0xffffff) << 8; |
168 | } | 192 | } |
169 | static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) | 193 | static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) |
170 | { | 194 | { |
@@ -212,7 +236,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void) | |||
212 | } | 236 | } |
213 | static inline u32 gmmu_new_pte_address_sys_f(u32 v) | 237 | static inline u32 gmmu_new_pte_address_sys_f(u32 v) |
214 | { | 238 | { |
215 | return (v & 0xfffffff) << 8; | 239 | return (v & 0xffffff) << 8; |
216 | } | 240 | } |
217 | static inline u32 gmmu_new_pte_address_sys_w(void) | 241 | static inline u32 gmmu_new_pte_address_sys_w(void) |
218 | { | 242 | { |
@@ -238,6 +262,14 @@ static inline u32 gmmu_new_pte_aperture_video_memory_f(void) | |||
238 | { | 262 | { |
239 | return 0x0; | 263 | return 0x0; |
240 | } | 264 | } |
265 | static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) | ||
266 | { | ||
267 | return 0x4; | ||
268 | } | ||
269 | static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) | ||
270 | { | ||
271 | return 0x6; | ||
272 | } | ||
241 | static inline u32 gmmu_new_pte_read_only_w(void) | 273 | static inline u32 gmmu_new_pte_read_only_w(void) |
242 | { | 274 | { |
243 | return 0; | 275 | return 0; |
@@ -1078,7 +1110,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) | |||
1078 | { | 1110 | { |
1079 | return 0x000000de; | 1111 | return 0x000000de; |
1080 | } | 1112 | } |
1081 | static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) | 1113 | static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) |
1082 | { | 1114 | { |
1083 | return 0x000000cc; | 1115 | return 0x000000cc; |
1084 | } | 1116 | } |
@@ -1142,7 +1174,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) | |||
1142 | { | 1174 | { |
1143 | return 0x000000ec; | 1175 | return 0x000000ec; |
1144 | } | 1176 | } |
1145 | static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) | 1177 | static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) |
1146 | { | 1178 | { |
1147 | return 0x000000cd; | 1179 | return 0x000000cd; |
1148 | } | 1180 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 39b7074f..a37ce6e7 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | |||
@@ -372,11 +372,11 @@ static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | |||
372 | } | 372 | } |
373 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | 373 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) |
374 | { | 374 | { |
375 | return 0x0050433c; | 375 | return 0x005046a4; |
376 | } | 376 | } |
377 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | 377 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) |
378 | { | 378 | { |
379 | return 0x00419b3c; | 379 | return 0x00419ea4; |
380 | } | 380 | } |
381 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | 381 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) |
382 | { | 382 | { |
@@ -468,7 +468,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) | |||
468 | } | 468 | } |
469 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) | 469 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) |
470 | { | 470 | { |
471 | return 0x00504358; | 471 | return 0x005046b8; |
472 | } | 472 | } |
473 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) | 473 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) |
474 | { | 474 | { |
@@ -504,7 +504,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_ | |||
504 | } | 504 | } |
505 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) | 505 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) |
506 | { | 506 | { |
507 | return 0x0050436c; | 507 | return 0x005044a0; |
508 | } | 508 | } |
509 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) | 509 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) |
510 | { | 510 | { |
@@ -532,15 +532,15 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe | |||
532 | } | 532 | } |
533 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) | 533 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) |
534 | { | 534 | { |
535 | return 0x0050435c; | 535 | return 0x005046bc; |
536 | } | 536 | } |
537 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) | 537 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) |
538 | { | 538 | { |
539 | return 0x00504360; | 539 | return 0x005046c0; |
540 | } | 540 | } |
541 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) | 541 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) |
542 | { | 542 | { |
543 | return 0x00504370; | 543 | return 0x005044a4; |
544 | } | 544 | } |
545 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) | 545 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) |
546 | { | 546 | { |
@@ -696,7 +696,7 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) | |||
696 | } | 696 | } |
697 | static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) | 697 | static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) |
698 | { | 698 | { |
699 | return 0x1800; | 699 | return 0x7fffffff; |
700 | } | 700 | } |
701 | static inline u32 gr_fe_object_table_r(u32 i) | 701 | static inline u32 gr_fe_object_table_r(u32 i) |
702 | { | 702 | { |
@@ -706,9 +706,9 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r) | |||
706 | { | 706 | { |
707 | return (r >> 0) & 0xffff; | 707 | return (r >> 0) & 0xffff; |
708 | } | 708 | } |
709 | static inline u32 gr_fe_tpc_fs_r(u32 i) | 709 | static inline u32 gr_fe_tpc_fs_r(void) |
710 | { | 710 | { |
711 | return 0x0040a200 + i*4; | 711 | return 0x004041c4; |
712 | } | 712 | } |
713 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) | 713 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) |
714 | { | 714 | { |
@@ -1530,9 +1530,29 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | |||
1530 | { | 1530 | { |
1531 | return 0x00502420; | 1531 | return 0x00502420; |
1532 | } | 1532 | } |
1533 | static inline u32 gr_rstr2d_gpc_map_r(u32 i) | 1533 | static inline u32 gr_rstr2d_gpc_map0_r(void) |
1534 | { | 1534 | { |
1535 | return 0x0040780c + i*4; | 1535 | return 0x0040780c; |
1536 | } | ||
1537 | static inline u32 gr_rstr2d_gpc_map1_r(void) | ||
1538 | { | ||
1539 | return 0x00407810; | ||
1540 | } | ||
1541 | static inline u32 gr_rstr2d_gpc_map2_r(void) | ||
1542 | { | ||
1543 | return 0x00407814; | ||
1544 | } | ||
1545 | static inline u32 gr_rstr2d_gpc_map3_r(void) | ||
1546 | { | ||
1547 | return 0x00407818; | ||
1548 | } | ||
1549 | static inline u32 gr_rstr2d_gpc_map4_r(void) | ||
1550 | { | ||
1551 | return 0x0040781c; | ||
1552 | } | ||
1553 | static inline u32 gr_rstr2d_gpc_map5_r(void) | ||
1554 | { | ||
1555 | return 0x00407820; | ||
1536 | } | 1556 | } |
1537 | static inline u32 gr_rstr2d_map_table_cfg_r(void) | 1557 | static inline u32 gr_rstr2d_map_table_cfg_r(void) |
1538 | { | 1558 | { |
@@ -1636,7 +1656,7 @@ static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) | |||
1636 | } | 1656 | } |
1637 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) | 1657 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) |
1638 | { | 1658 | { |
1639 | return 0x00001d80; | 1659 | return 0x000001c0; |
1640 | } | 1660 | } |
1641 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) | 1661 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) |
1642 | { | 1662 | { |
@@ -1648,7 +1668,7 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) | |||
1648 | } | 1668 | } |
1649 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) | 1669 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) |
1650 | { | 1670 | { |
1651 | return 0x00001d80; | 1671 | return 0x00000182; |
1652 | } | 1672 | } |
1653 | static inline u32 gr_pd_dist_skip_table_r(u32 i) | 1673 | static inline u32 gr_pd_dist_skip_table_r(u32 i) |
1654 | { | 1674 | { |
@@ -2032,7 +2052,7 @@ static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) | |||
2032 | } | 2052 | } |
2033 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) | 2053 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) |
2034 | { | 2054 | { |
2035 | return 0x00000030; | 2055 | return 0x00000018; |
2036 | } | 2056 | } |
2037 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) | 2057 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) |
2038 | { | 2058 | { |
@@ -2146,10 +2166,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) | |||
2146 | { | 2166 | { |
2147 | return 0x00405b60 + i*4; | 2167 | return 0x00405b60 + i*4; |
2148 | } | 2168 | } |
2169 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) | ||
2170 | { | ||
2171 | return 4; | ||
2172 | } | ||
2149 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) | 2173 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) |
2150 | { | 2174 | { |
2151 | return (v & 0xf) << 0; | 2175 | return (v & 0xf) << 0; |
2152 | } | 2176 | } |
2177 | static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) | ||
2178 | { | ||
2179 | return 4; | ||
2180 | } | ||
2181 | static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) | ||
2182 | { | ||
2183 | return (v & 0xf) << 4; | ||
2184 | } | ||
2153 | static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) | 2185 | static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) |
2154 | { | 2186 | { |
2155 | return (v & 0xf) << 8; | 2187 | return (v & 0xf) << 8; |
@@ -2158,6 +2190,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i) | |||
2158 | { | 2190 | { |
2159 | return 0x00405ba0 + i*4; | 2191 | return 0x00405ba0 + i*4; |
2160 | } | 2192 | } |
2193 | static inline u32 gr_cwd_sm_id__size_1_v(void) | ||
2194 | { | ||
2195 | return 0x00000010; | ||
2196 | } | ||
2161 | static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) | 2197 | static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) |
2162 | { | 2198 | { |
2163 | return (v & 0xff) << 0; | 2199 | return (v & 0xff) << 0; |
@@ -2316,7 +2352,7 @@ static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) | |||
2316 | } | 2352 | } |
2317 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) | 2353 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) |
2318 | { | 2354 | { |
2319 | return 0x00504608; | 2355 | return 0x00504698; |
2320 | } | 2356 | } |
2321 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | 2357 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) |
2322 | { | 2358 | { |
@@ -2328,7 +2364,7 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) | |||
2328 | } | 2364 | } |
2329 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | 2365 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) |
2330 | { | 2366 | { |
2331 | return 0x00504330; | 2367 | return 0x0050469c; |
2332 | } | 2368 | } |
2333 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) | 2369 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) |
2334 | { | 2370 | { |
@@ -2368,11 +2404,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) | |||
2368 | } | 2404 | } |
2369 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) | 2405 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) |
2370 | { | 2406 | { |
2371 | return 0x00000480; | 2407 | return 0x00030000; |
2372 | } | 2408 | } |
2373 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) | 2409 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) |
2374 | { | 2410 | { |
2375 | return 0x00000d10; | 2411 | return 0x00030a00; |
2376 | } | 2412 | } |
2377 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) | 2413 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) |
2378 | { | 2414 | { |
@@ -2416,11 +2452,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) | |||
2416 | } | 2452 | } |
2417 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) | 2453 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) |
2418 | { | 2454 | { |
2419 | return 0x00000480; | 2455 | return 0x00030000; |
2420 | } | 2456 | } |
2421 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) | 2457 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) |
2422 | { | 2458 | { |
2423 | return 0x00419e00; | 2459 | return 0x00419b00; |
2424 | } | 2460 | } |
2425 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) | 2461 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) |
2426 | { | 2462 | { |
@@ -2428,7 +2464,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) | |||
2428 | } | 2464 | } |
2429 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) | 2465 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) |
2430 | { | 2466 | { |
2431 | return 0x00419e04; | 2467 | return 0x00419b04; |
2432 | } | 2468 | } |
2433 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) | 2469 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) |
2434 | { | 2470 | { |
@@ -2672,11 +2708,11 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) | |||
2672 | } | 2708 | } |
2673 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) | 2709 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) |
2674 | { | 2710 | { |
2675 | return 0x00000030; | 2711 | return 0x00000018; |
2676 | } | 2712 | } |
2677 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) | 2713 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) |
2678 | { | 2714 | { |
2679 | return 0x30; | 2715 | return 0x18; |
2680 | } | 2716 | } |
2681 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) | 2717 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) |
2682 | { | 2718 | { |
@@ -2712,7 +2748,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) | |||
2712 | } | 2748 | } |
2713 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) | 2749 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) |
2714 | { | 2750 | { |
2715 | return 0x005001dc; | 2751 | return 0x00500ee4; |
2716 | } | 2752 | } |
2717 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) | 2753 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) |
2718 | { | 2754 | { |
@@ -2720,7 +2756,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) | |||
2720 | } | 2756 | } |
2721 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) | 2757 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) |
2722 | { | 2758 | { |
2723 | return 0x00000de0; | 2759 | return 0x00000250; |
2724 | } | 2760 | } |
2725 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) | 2761 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) |
2726 | { | 2762 | { |
@@ -2728,7 +2764,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void | |||
2728 | } | 2764 | } |
2729 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) | 2765 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) |
2730 | { | 2766 | { |
2731 | return 0x005001d8; | 2767 | return 0x00500ee0; |
2732 | } | 2768 | } |
2733 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) | 2769 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) |
2734 | { | 2770 | { |
@@ -2740,7 +2776,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) | |||
2740 | } | 2776 | } |
2741 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) | 2777 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) |
2742 | { | 2778 | { |
2743 | return 0x004181e4; | 2779 | return 0x00418eec; |
2744 | } | 2780 | } |
2745 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) | 2781 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) |
2746 | { | 2782 | { |
@@ -2834,33 +2870,173 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) | |||
2834 | { | 2870 | { |
2835 | return 0x80000000; | 2871 | return 0x80000000; |
2836 | } | 2872 | } |
2837 | static inline u32 gr_crstr_gpc_map_r(u32 i) | 2873 | static inline u32 gr_crstr_gpc_map0_r(void) |
2838 | { | 2874 | { |
2839 | return 0x00418b08 + i*4; | 2875 | return 0x00418b08; |
2840 | } | 2876 | } |
2841 | static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) | 2877 | static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) |
2842 | { | 2878 | { |
2843 | return (v & 0x1f) << 0; | 2879 | return (v & 0x7) << 0; |
2844 | } | 2880 | } |
2845 | static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) | 2881 | static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) |
2846 | { | 2882 | { |
2847 | return (v & 0x1f) << 5; | 2883 | return (v & 0x7) << 5; |
2848 | } | 2884 | } |
2849 | static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) | 2885 | static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) |
2850 | { | 2886 | { |
2851 | return (v & 0x1f) << 10; | 2887 | return (v & 0x7) << 10; |
2852 | } | 2888 | } |
2853 | static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) | 2889 | static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) |
2854 | { | 2890 | { |
2855 | return (v & 0x1f) << 15; | 2891 | return (v & 0x7) << 15; |
2856 | } | 2892 | } |
2857 | static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) | 2893 | static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) |
2858 | { | 2894 | { |
2859 | return (v & 0x1f) << 20; | 2895 | return (v & 0x7) << 20; |
2860 | } | 2896 | } |
2861 | static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) | 2897 | static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) |
2862 | { | 2898 | { |
2863 | return (v & 0x1f) << 25; | 2899 | return (v & 0x7) << 25; |
2900 | } | ||
2901 | static inline u32 gr_crstr_gpc_map1_r(void) | ||
2902 | { | ||
2903 | return 0x00418b0c; | ||
2904 | } | ||
2905 | static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) | ||
2906 | { | ||
2907 | return (v & 0x7) << 0; | ||
2908 | } | ||
2909 | static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) | ||
2910 | { | ||
2911 | return (v & 0x7) << 5; | ||
2912 | } | ||
2913 | static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) | ||
2914 | { | ||
2915 | return (v & 0x7) << 10; | ||
2916 | } | ||
2917 | static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) | ||
2918 | { | ||
2919 | return (v & 0x7) << 15; | ||
2920 | } | ||
2921 | static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) | ||
2922 | { | ||
2923 | return (v & 0x7) << 20; | ||
2924 | } | ||
2925 | static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) | ||
2926 | { | ||
2927 | return (v & 0x7) << 25; | ||
2928 | } | ||
2929 | static inline u32 gr_crstr_gpc_map2_r(void) | ||
2930 | { | ||
2931 | return 0x00418b10; | ||
2932 | } | ||
2933 | static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) | ||
2934 | { | ||
2935 | return (v & 0x7) << 0; | ||
2936 | } | ||
2937 | static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) | ||
2938 | { | ||
2939 | return (v & 0x7) << 5; | ||
2940 | } | ||
2941 | static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) | ||
2942 | { | ||
2943 | return (v & 0x7) << 10; | ||
2944 | } | ||
2945 | static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) | ||
2946 | { | ||
2947 | return (v & 0x7) << 15; | ||
2948 | } | ||
2949 | static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) | ||
2950 | { | ||
2951 | return (v & 0x7) << 20; | ||
2952 | } | ||
2953 | static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) | ||
2954 | { | ||
2955 | return (v & 0x7) << 25; | ||
2956 | } | ||
2957 | static inline u32 gr_crstr_gpc_map3_r(void) | ||
2958 | { | ||
2959 | return 0x00418b14; | ||
2960 | } | ||
2961 | static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) | ||
2962 | { | ||
2963 | return (v & 0x7) << 0; | ||
2964 | } | ||
2965 | static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) | ||
2966 | { | ||
2967 | return (v & 0x7) << 5; | ||
2968 | } | ||
2969 | static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) | ||
2970 | { | ||
2971 | return (v & 0x7) << 10; | ||
2972 | } | ||
2973 | static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) | ||
2974 | { | ||
2975 | return (v & 0x7) << 15; | ||
2976 | } | ||
2977 | static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) | ||
2978 | { | ||
2979 | return (v & 0x7) << 20; | ||
2980 | } | ||
2981 | static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) | ||
2982 | { | ||
2983 | return (v & 0x7) << 25; | ||
2984 | } | ||
2985 | static inline u32 gr_crstr_gpc_map4_r(void) | ||
2986 | { | ||
2987 | return 0x00418b18; | ||
2988 | } | ||
2989 | static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) | ||
2990 | { | ||
2991 | return (v & 0x7) << 0; | ||
2992 | } | ||
2993 | static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) | ||
2994 | { | ||
2995 | return (v & 0x7) << 5; | ||
2996 | } | ||
2997 | static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) | ||
2998 | { | ||
2999 | return (v & 0x7) << 10; | ||
3000 | } | ||
3001 | static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) | ||
3002 | { | ||
3003 | return (v & 0x7) << 15; | ||
3004 | } | ||
3005 | static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) | ||
3006 | { | ||
3007 | return (v & 0x7) << 20; | ||
3008 | } | ||
3009 | static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) | ||
3010 | { | ||
3011 | return (v & 0x7) << 25; | ||
3012 | } | ||
3013 | static inline u32 gr_crstr_gpc_map5_r(void) | ||
3014 | { | ||
3015 | return 0x00418b1c; | ||
3016 | } | ||
3017 | static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) | ||
3018 | { | ||
3019 | return (v & 0x7) << 0; | ||
3020 | } | ||
3021 | static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) | ||
3022 | { | ||
3023 | return (v & 0x7) << 5; | ||
3024 | } | ||
3025 | static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) | ||
3026 | { | ||
3027 | return (v & 0x7) << 10; | ||
3028 | } | ||
3029 | static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) | ||
3030 | { | ||
3031 | return (v & 0x7) << 15; | ||
3032 | } | ||
3033 | static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) | ||
3034 | { | ||
3035 | return (v & 0x7) << 20; | ||
3036 | } | ||
3037 | static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) | ||
3038 | { | ||
3039 | return (v & 0x7) << 25; | ||
2864 | } | 3040 | } |
2865 | static inline u32 gr_crstr_map_table_cfg_r(void) | 3041 | static inline u32 gr_crstr_map_table_cfg_r(void) |
2866 | { | 3042 | { |
@@ -2874,39 +3050,159 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) | |||
2874 | { | 3050 | { |
2875 | return (v & 0xff) << 8; | 3051 | return (v & 0xff) << 8; |
2876 | } | 3052 | } |
2877 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) | 3053 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) |
3054 | { | ||
3055 | return 0x00418980; | ||
3056 | } | ||
3057 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) | ||
3058 | { | ||
3059 | return (v & 0x7) << 0; | ||
3060 | } | ||
3061 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) | ||
3062 | { | ||
3063 | return (v & 0x7) << 4; | ||
3064 | } | ||
3065 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) | ||
3066 | { | ||
3067 | return (v & 0x7) << 8; | ||
3068 | } | ||
3069 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) | ||
3070 | { | ||
3071 | return (v & 0x7) << 12; | ||
3072 | } | ||
3073 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) | ||
3074 | { | ||
3075 | return (v & 0x7) << 16; | ||
3076 | } | ||
3077 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) | ||
3078 | { | ||
3079 | return (v & 0x7) << 20; | ||
3080 | } | ||
3081 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) | ||
3082 | { | ||
3083 | return (v & 0x7) << 24; | ||
3084 | } | ||
3085 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) | ||
3086 | { | ||
3087 | return (v & 0x7) << 28; | ||
3088 | } | ||
3089 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) | ||
3090 | { | ||
3091 | return 0x00418984; | ||
3092 | } | ||
3093 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) | ||
3094 | { | ||
3095 | return (v & 0x7) << 0; | ||
3096 | } | ||
3097 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) | ||
3098 | { | ||
3099 | return (v & 0x7) << 4; | ||
3100 | } | ||
3101 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) | ||
3102 | { | ||
3103 | return (v & 0x7) << 8; | ||
3104 | } | ||
3105 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) | ||
3106 | { | ||
3107 | return (v & 0x7) << 12; | ||
3108 | } | ||
3109 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) | ||
3110 | { | ||
3111 | return (v & 0x7) << 16; | ||
3112 | } | ||
3113 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) | ||
3114 | { | ||
3115 | return (v & 0x7) << 20; | ||
3116 | } | ||
3117 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) | ||
3118 | { | ||
3119 | return (v & 0x7) << 24; | ||
3120 | } | ||
3121 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) | ||
3122 | { | ||
3123 | return (v & 0x7) << 28; | ||
3124 | } | ||
3125 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) | ||
3126 | { | ||
3127 | return 0x00418988; | ||
3128 | } | ||
3129 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) | ||
3130 | { | ||
3131 | return (v & 0x7) << 0; | ||
3132 | } | ||
3133 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) | ||
2878 | { | 3134 | { |
2879 | return 0x00418980 + i*4; | 3135 | return (v & 0x7) << 4; |
3136 | } | ||
3137 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) | ||
3138 | { | ||
3139 | return (v & 0x7) << 8; | ||
3140 | } | ||
3141 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) | ||
3142 | { | ||
3143 | return (v & 0x7) << 12; | ||
3144 | } | ||
3145 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) | ||
3146 | { | ||
3147 | return (v & 0x7) << 16; | ||
3148 | } | ||
3149 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) | ||
3150 | { | ||
3151 | return (v & 0x7) << 20; | ||
3152 | } | ||
3153 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) | ||
3154 | { | ||
3155 | return (v & 0x7) << 24; | ||
3156 | } | ||
3157 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) | ||
3158 | { | ||
3159 | return 3; | ||
3160 | } | ||
3161 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) | ||
3162 | { | ||
3163 | return (v & 0x7) << 28; | ||
2880 | } | 3164 | } |
2881 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) | 3165 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) |
3166 | { | ||
3167 | return 0x7 << 28; | ||
3168 | } | ||
3169 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) | ||
3170 | { | ||
3171 | return (r >> 28) & 0x7; | ||
3172 | } | ||
3173 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) | ||
3174 | { | ||
3175 | return 0x0041898c; | ||
3176 | } | ||
3177 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) | ||
2882 | { | 3178 | { |
2883 | return (v & 0x7) << 0; | 3179 | return (v & 0x7) << 0; |
2884 | } | 3180 | } |
2885 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) | 3181 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) |
2886 | { | 3182 | { |
2887 | return (v & 0x7) << 4; | 3183 | return (v & 0x7) << 4; |
2888 | } | 3184 | } |
2889 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) | 3185 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) |
2890 | { | 3186 | { |
2891 | return (v & 0x7) << 8; | 3187 | return (v & 0x7) << 8; |
2892 | } | 3188 | } |
2893 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) | 3189 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) |
2894 | { | 3190 | { |
2895 | return (v & 0x7) << 12; | 3191 | return (v & 0x7) << 12; |
2896 | } | 3192 | } |
2897 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) | 3193 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) |
2898 | { | 3194 | { |
2899 | return (v & 0x7) << 16; | 3195 | return (v & 0x7) << 16; |
2900 | } | 3196 | } |
2901 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) | 3197 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) |
2902 | { | 3198 | { |
2903 | return (v & 0x7) << 20; | 3199 | return (v & 0x7) << 20; |
2904 | } | 3200 | } |
2905 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) | 3201 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) |
2906 | { | 3202 | { |
2907 | return (v & 0x7) << 24; | 3203 | return (v & 0x7) << 24; |
2908 | } | 3204 | } |
2909 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) | 3205 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) |
2910 | { | 3206 | { |
2911 | return (v & 0x7) << 28; | 3207 | return (v & 0x7) << 28; |
2912 | } | 3208 | } |
@@ -2990,87 +3286,135 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | |||
2990 | { | 3286 | { |
2991 | return 0x10000000; | 3287 | return 0x10000000; |
2992 | } | 3288 | } |
2993 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_r(void) | 3289 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) |
2994 | { | 3290 | { |
2995 | return 0x00419fa8; | 3291 | return 0x00419e44; |
2996 | } | 3292 | } |
2997 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_error_report_f(void) | 3293 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) |
2998 | { | 3294 | { |
2999 | return 0x2; | 3295 | return 0x2; |
3000 | } | 3296 | } |
3001 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_api_stack_error_report_f(void) | 3297 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) |
3002 | { | 3298 | { |
3003 | return 0x4; | 3299 | return 0x4; |
3004 | } | 3300 | } |
3005 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_wrap_report_f(void) | 3301 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) |
3302 | { | ||
3303 | return 0x8; | ||
3304 | } | ||
3305 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) | ||
3006 | { | 3306 | { |
3007 | return 0x10; | 3307 | return 0x10; |
3008 | } | 3308 | } |
3009 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_pc_report_f(void) | 3309 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) |
3010 | { | 3310 | { |
3011 | return 0x20; | 3311 | return 0x20; |
3012 | } | 3312 | } |
3013 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_overflow_report_f(void) | 3313 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) |
3014 | { | 3314 | { |
3015 | return 0x40; | 3315 | return 0x40; |
3016 | } | 3316 | } |
3017 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | 3317 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) |
3318 | { | ||
3319 | return 0x80; | ||
3320 | } | ||
3321 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | ||
3018 | { | 3322 | { |
3019 | return 0x100; | 3323 | return 0x100; |
3020 | } | 3324 | } |
3021 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) | 3325 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) |
3022 | { | 3326 | { |
3023 | return 0x200; | 3327 | return 0x200; |
3024 | } | 3328 | } |
3025 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | 3329 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) |
3330 | { | ||
3331 | return 0x400; | ||
3332 | } | ||
3333 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | ||
3026 | { | 3334 | { |
3027 | return 0x800; | 3335 | return 0x800; |
3028 | } | 3336 | } |
3029 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_reg_report_f(void) | 3337 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) |
3338 | { | ||
3339 | return 0x1000; | ||
3340 | } | ||
3341 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) | ||
3030 | { | 3342 | { |
3031 | return 0x2000; | 3343 | return 0x2000; |
3032 | } | 3344 | } |
3033 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_addr_report_f(void) | 3345 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) |
3034 | { | 3346 | { |
3035 | return 0x4000; | 3347 | return 0x4000; |
3036 | } | 3348 | } |
3037 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_addr_report_f(void) | 3349 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) |
3038 | { | 3350 | { |
3039 | return 0x8000; | 3351 | return 0x8000; |
3040 | } | 3352 | } |
3041 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) | 3353 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) |
3042 | { | 3354 | { |
3043 | return 0x10000; | 3355 | return 0x10000; |
3044 | } | 3356 | } |
3045 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | 3357 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) |
3358 | { | ||
3359 | return 0x20000; | ||
3360 | } | ||
3361 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | ||
3046 | { | 3362 | { |
3047 | return 0x40000; | 3363 | return 0x40000; |
3048 | } | 3364 | } |
3049 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_mmu_fault_report_f(void) | 3365 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) |
3050 | { | 3366 | { |
3051 | return 0x800000; | 3367 | return 0x800000; |
3052 | } | 3368 | } |
3053 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_overflow_report_f(void) | 3369 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) |
3054 | { | 3370 | { |
3055 | return 0x400000; | 3371 | return 0x400000; |
3056 | } | 3372 | } |
3057 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_r(void) | 3373 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) |
3058 | { | 3374 | { |
3059 | return 0x00419fac; | 3375 | return 0x80000; |
3376 | } | ||
3377 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) | ||
3378 | { | ||
3379 | return 0x100000; | ||
3380 | } | ||
3381 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) | ||
3382 | { | ||
3383 | return 0x00419e4c; | ||
3060 | } | 3384 | } |
3061 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | 3385 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) |
3386 | { | ||
3387 | return 0x1; | ||
3388 | } | ||
3389 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) | ||
3390 | { | ||
3391 | return 0x2; | ||
3392 | } | ||
3393 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | ||
3062 | { | 3394 | { |
3063 | return 0x4; | 3395 | return 0x4; |
3064 | } | 3396 | } |
3065 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_int_report_f(void) | 3397 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) |
3398 | { | ||
3399 | return 0x8; | ||
3400 | } | ||
3401 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) | ||
3066 | { | 3402 | { |
3067 | return 0x10; | 3403 | return 0x10; |
3068 | } | 3404 | } |
3069 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_pause_report_f(void) | 3405 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) |
3406 | { | ||
3407 | return 0x20000000; | ||
3408 | } | ||
3409 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) | ||
3410 | { | ||
3411 | return 0x40000000; | ||
3412 | } | ||
3413 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) | ||
3070 | { | 3414 | { |
3071 | return 0x20; | 3415 | return 0x20; |
3072 | } | 3416 | } |
3073 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_single_step_complete_report_f(void) | 3417 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) |
3074 | { | 3418 | { |
3075 | return 0x40; | 3419 | return 0x40; |
3076 | } | 3420 | } |
@@ -3138,118 +3482,190 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) | |||
3138 | { | 3482 | { |
3139 | return 0x00000001; | 3483 | return 0x00000001; |
3140 | } | 3484 | } |
3141 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_r(void) | 3485 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) |
3142 | { | 3486 | { |
3143 | return 0x00504784; | 3487 | return 0x00504610; |
3144 | } | 3488 | } |
3145 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_m(void) | 3489 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) |
3146 | { | 3490 | { |
3147 | return 0x1 << 0; | 3491 | return 0x1 << 0; |
3148 | } | 3492 | } |
3149 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_v(u32 r) | 3493 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) |
3150 | { | 3494 | { |
3151 | return (r >> 0) & 0x1; | 3495 | return (r >> 0) & 0x1; |
3152 | } | 3496 | } |
3153 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_on_v(void) | 3497 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) |
3154 | { | 3498 | { |
3155 | return 0x00000001; | 3499 | return 0x00000001; |
3156 | } | 3500 | } |
3157 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_off_v(void) | 3501 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) |
3158 | { | 3502 | { |
3159 | return 0x00000000; | 3503 | return 0x00000000; |
3160 | } | 3504 | } |
3161 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_enable_f(void) | 3505 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) |
3162 | { | 3506 | { |
3163 | return 0x80000000; | 3507 | return 0x80000000; |
3164 | } | 3508 | } |
3165 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_disable_f(void) | 3509 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) |
3166 | { | 3510 | { |
3167 | return 0x0; | 3511 | return 0x0; |
3168 | } | 3512 | } |
3169 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_enable_f(void) | 3513 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) |
3170 | { | 3514 | { |
3171 | return 0x8; | 3515 | return 0x8; |
3172 | } | 3516 | } |
3173 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_disable_f(void) | 3517 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) |
3174 | { | 3518 | { |
3175 | return 0x0; | 3519 | return 0x0; |
3176 | } | 3520 | } |
3177 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_run_trigger_task_f(void) | 3521 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
3178 | { | 3522 | { |
3179 | return 0x40000000; | 3523 | return 0x40000000; |
3180 | } | 3524 | } |
3181 | static inline u32 gr_gpc0_tpc0_sm1_warp_valid_mask_r(void) | 3525 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) |
3526 | { | ||
3527 | return 0x1 << 1; | ||
3528 | } | ||
3529 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) | ||
3530 | { | ||
3531 | return (r >> 1) & 0x1; | ||
3532 | } | ||
3533 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) | ||
3534 | { | ||
3535 | return 0x0; | ||
3536 | } | ||
3537 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) | ||
3538 | { | ||
3539 | return 0x1 << 2; | ||
3540 | } | ||
3541 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) | ||
3542 | { | ||
3543 | return (r >> 2) & 0x1; | ||
3544 | } | ||
3545 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | ||
3546 | { | ||
3547 | return 0x0; | ||
3548 | } | ||
3549 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) | ||
3550 | { | ||
3551 | return 0x00000000; | ||
3552 | } | ||
3553 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) | ||
3182 | { | 3554 | { |
3183 | return 0x00504788; | 3555 | return 0x00000000; |
3556 | } | ||
3557 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | ||
3558 | { | ||
3559 | return 0x00504614; | ||
3184 | } | 3560 | } |
3185 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_pause_mask_r(void) | 3561 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) |
3186 | { | 3562 | { |
3187 | return 0x00504790; | 3563 | return 0x00504624; |
3188 | } | 3564 | } |
3189 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_trap_mask_r(void) | 3565 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) |
3190 | { | 3566 | { |
3191 | return 0x00504798; | 3567 | return 0x00504634; |
3192 | } | 3568 | } |
3193 | static inline u32 gr_gpcs_tpcs_sm1_dbgr_bpt_pause_mask_r(void) | 3569 | static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) |
3194 | { | 3570 | { |
3195 | return 0x00419f90; | 3571 | return 0x00419e24; |
3196 | } | 3572 | } |
3197 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_r(void) | 3573 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3198 | { | 3574 | { |
3199 | return 0x00504780; | 3575 | return 0x0050460c; |
3200 | } | 3576 | } |
3201 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_sm_in_trap_mode_v(u32 r) | 3577 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) |
3202 | { | 3578 | { |
3203 | return (r >> 0) & 0x1; | 3579 | return (r >> 0) & 0x1; |
3204 | } | 3580 | } |
3205 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_v(u32 r) | 3581 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) |
3206 | { | 3582 | { |
3207 | return (r >> 4) & 0x1; | 3583 | return (r >> 4) & 0x1; |
3208 | } | 3584 | } |
3209 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_true_v(void) | 3585 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) |
3210 | { | 3586 | { |
3211 | return 0x00000001; | 3587 | return 0x00000001; |
3212 | } | 3588 | } |
3213 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_r(void) | 3589 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) |
3214 | { | 3590 | { |
3215 | return 0x00419fb4; | 3591 | return 0x00419e50; |
3216 | } | 3592 | } |
3217 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_int_pending_f(void) | 3593 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) |
3218 | { | 3594 | { |
3219 | return 0x10; | 3595 | return 0x10; |
3220 | } | 3596 | } |
3221 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(void) | 3597 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) |
3222 | { | 3598 | { |
3223 | return 0x20; | 3599 | return 0x20; |
3224 | } | 3600 | } |
3225 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_single_step_complete_pending_f(void) | 3601 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) |
3226 | { | 3602 | { |
3227 | return 0x40; | 3603 | return 0x40; |
3228 | } | 3604 | } |
3229 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) | 3605 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) |
3606 | { | ||
3607 | return 0x1; | ||
3608 | } | ||
3609 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) | ||
3610 | { | ||
3611 | return 0x2; | ||
3612 | } | ||
3613 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3230 | { | 3614 | { |
3231 | return 0x4; | 3615 | return 0x4; |
3232 | } | 3616 | } |
3233 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_r(void) | 3617 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) |
3618 | { | ||
3619 | return 0x8; | ||
3620 | } | ||
3621 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3622 | { | ||
3623 | return 0x80000000; | ||
3624 | } | ||
3625 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | ||
3234 | { | 3626 | { |
3235 | return 0x005047b4; | 3627 | return 0x00504650; |
3236 | } | 3628 | } |
3237 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f(void) | 3629 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) |
3238 | { | 3630 | { |
3239 | return 0x10; | 3631 | return 0x10; |
3240 | } | 3632 | } |
3241 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_pause_pending_f(void) | 3633 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) |
3634 | { | ||
3635 | return 0x20000000; | ||
3636 | } | ||
3637 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) | ||
3638 | { | ||
3639 | return 0x40000000; | ||
3640 | } | ||
3641 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) | ||
3242 | { | 3642 | { |
3243 | return 0x20; | 3643 | return 0x20; |
3244 | } | 3644 | } |
3245 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f(void) | 3645 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) |
3246 | { | 3646 | { |
3247 | return 0x40; | 3647 | return 0x40; |
3248 | } | 3648 | } |
3249 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) | 3649 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) |
3650 | { | ||
3651 | return 0x1; | ||
3652 | } | ||
3653 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) | ||
3654 | { | ||
3655 | return 0x2; | ||
3656 | } | ||
3657 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3250 | { | 3658 | { |
3251 | return 0x4; | 3659 | return 0x4; |
3252 | } | 3660 | } |
3661 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3662 | { | ||
3663 | return 0x8; | ||
3664 | } | ||
3665 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3666 | { | ||
3667 | return 0x80000000; | ||
3668 | } | ||
3253 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3669 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
3254 | { | 3670 | { |
3255 | return 0x00504224; | 3671 | return 0x00504224; |
@@ -3266,45 +3682,45 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) | |||
3266 | { | 3682 | { |
3267 | return 0x100; | 3683 | return 0x100; |
3268 | } | 3684 | } |
3269 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_r(void) | 3685 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) |
3270 | { | 3686 | { |
3271 | return 0x005047b0; | 3687 | return 0x00504648; |
3272 | } | 3688 | } |
3273 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_v(u32 r) | 3689 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) |
3274 | { | 3690 | { |
3275 | return (r >> 0) & 0xffff; | 3691 | return (r >> 0) & 0xffff; |
3276 | } | 3692 | } |
3277 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_v(void) | 3693 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) |
3278 | { | 3694 | { |
3279 | return 0x00000000; | 3695 | return 0x00000000; |
3280 | } | 3696 | } |
3281 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_f(void) | 3697 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) |
3282 | { | 3698 | { |
3283 | return 0x0; | 3699 | return 0x0; |
3284 | } | 3700 | } |
3285 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m(void) | 3701 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) |
3286 | { | 3702 | { |
3287 | return 0x1 << 24; | 3703 | return 0x1 << 24; |
3288 | } | 3704 | } |
3289 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(void) | 3705 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) |
3290 | { | 3706 | { |
3291 | return 0x7 << 25; | 3707 | return 0x7 << 25; |
3292 | } | 3708 | } |
3293 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f(void) | 3709 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) |
3294 | { | 3710 | { |
3295 | return 0x0; | 3711 | return 0x0; |
3296 | } | 3712 | } |
3297 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) | 3713 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) |
3298 | { | 3714 | { |
3299 | return 0x005047b8; | 3715 | return 0x00504654; |
3300 | } | 3716 | } |
3301 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | 3717 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) |
3302 | { | 3718 | { |
3303 | return 0x005043a0; | 3719 | return 0x00504770; |
3304 | } | 3720 | } |
3305 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) | 3721 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) |
3306 | { | 3722 | { |
3307 | return 0x00419ba0; | 3723 | return 0x00419f70; |
3308 | } | 3724 | } |
3309 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) | 3725 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) |
3310 | { | 3726 | { |
@@ -3316,11 +3732,11 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) | |||
3316 | } | 3732 | } |
3317 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) | 3733 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) |
3318 | { | 3734 | { |
3319 | return 0x005043b0; | 3735 | return 0x0050477c; |
3320 | } | 3736 | } |
3321 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) | 3737 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) |
3322 | { | 3738 | { |
3323 | return 0x00419bb0; | 3739 | return 0x00419f7c; |
3324 | } | 3740 | } |
3325 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) | 3741 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) |
3326 | { | 3742 | { |
@@ -3338,9 +3754,29 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) | |||
3338 | { | 3754 | { |
3339 | return 0x4; | 3755 | return 0x4; |
3340 | } | 3756 | } |
3341 | static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) | 3757 | static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) |
3758 | { | ||
3759 | return 0x0041bf00; | ||
3760 | } | ||
3761 | static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) | ||
3762 | { | ||
3763 | return 0x0041bf04; | ||
3764 | } | ||
3765 | static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) | ||
3766 | { | ||
3767 | return 0x0041bf08; | ||
3768 | } | ||
3769 | static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) | ||
3770 | { | ||
3771 | return 0x0041bf0c; | ||
3772 | } | ||
3773 | static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) | ||
3774 | { | ||
3775 | return 0x0041bf10; | ||
3776 | } | ||
3777 | static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) | ||
3342 | { | 3778 | { |
3343 | return 0x0041bf00 + i*4; | 3779 | return 0x0041bf14; |
3344 | } | 3780 | } |
3345 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) | 3781 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) |
3346 | { | 3782 | { |
@@ -3362,6 +3798,10 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) | |||
3362 | { | 3798 | { |
3363 | return (v & 0x7) << 21; | 3799 | return (v & 0x7) << 21; |
3364 | } | 3800 | } |
3801 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) | ||
3802 | { | ||
3803 | return (v & 0x1f) << 24; | ||
3804 | } | ||
3365 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) | 3805 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) |
3366 | { | 3806 | { |
3367 | return 0x0041bfd4; | 3807 | return 0x0041bfd4; |
@@ -3370,6 +3810,34 @@ static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) | |||
3370 | { | 3810 | { |
3371 | return (v & 0xffffff) << 0; | 3811 | return (v & 0xffffff) << 0; |
3372 | } | 3812 | } |
3813 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) | ||
3814 | { | ||
3815 | return 0x0041bfe4; | ||
3816 | } | ||
3817 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) | ||
3818 | { | ||
3819 | return (v & 0x1f) << 0; | ||
3820 | } | ||
3821 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) | ||
3822 | { | ||
3823 | return (v & 0x1f) << 5; | ||
3824 | } | ||
3825 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) | ||
3826 | { | ||
3827 | return (v & 0x1f) << 10; | ||
3828 | } | ||
3829 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) | ||
3830 | { | ||
3831 | return (v & 0x1f) << 15; | ||
3832 | } | ||
3833 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) | ||
3834 | { | ||
3835 | return (v & 0x1f) << 20; | ||
3836 | } | ||
3837 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) | ||
3838 | { | ||
3839 | return (v & 0x1f) << 25; | ||
3840 | } | ||
3373 | static inline u32 gr_bes_zrop_settings_r(void) | 3841 | static inline u32 gr_bes_zrop_settings_r(void) |
3374 | { | 3842 | { |
3375 | return 0x00408850; | 3843 | return 0x00408850; |
@@ -3416,75 +3884,107 @@ static inline u32 gr_zcull_subregion_qty_v(void) | |||
3416 | } | 3884 | } |
3417 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) | 3885 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) |
3418 | { | 3886 | { |
3419 | return 0x00504308; | 3887 | return 0x00504604; |
3420 | } | 3888 | } |
3421 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) | 3889 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) |
3422 | { | 3890 | { |
3423 | return 0x0050430c; | 3891 | return 0x00504608; |
3424 | } | 3892 | } |
3425 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) | 3893 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) |
3426 | { | 3894 | { |
3427 | return 0x00504318; | 3895 | return 0x0050465c; |
3428 | } | 3896 | } |
3429 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) | 3897 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) |
3430 | { | 3898 | { |
3431 | return 0x00504320; | 3899 | return 0x00504660; |
3432 | } | 3900 | } |
3433 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) | 3901 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) |
3434 | { | 3902 | { |
3435 | return 0x00504324; | 3903 | return 0x00504664; |
3436 | } | 3904 | } |
3437 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) | 3905 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) |
3438 | { | 3906 | { |
3439 | return 0x00504328; | 3907 | return 0x00504668; |
3440 | } | 3908 | } |
3441 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) | 3909 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) |
3442 | { | 3910 | { |
3443 | return 0x0050432c; | 3911 | return 0x0050466c; |
3444 | } | 3912 | } |
3445 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) | 3913 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) |
3446 | { | 3914 | { |
3447 | return 0x0050431c; | 3915 | return 0x00504658; |
3448 | } | 3916 | } |
3449 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) | 3917 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) |
3450 | { | 3918 | { |
3451 | return 0x00504378; | 3919 | return 0x00504730; |
3452 | } | 3920 | } |
3453 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) | 3921 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) |
3454 | { | 3922 | { |
3455 | return 0x0050437c; | 3923 | return 0x00504734; |
3456 | } | 3924 | } |
3457 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) | 3925 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) |
3458 | { | 3926 | { |
3459 | return 0x00504380; | 3927 | return 0x00504738; |
3460 | } | 3928 | } |
3461 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) | 3929 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) |
3462 | { | 3930 | { |
3463 | return 0x00504384; | 3931 | return 0x0050473c; |
3464 | } | 3932 | } |
3465 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) | 3933 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) |
3466 | { | 3934 | { |
3467 | return 0x00504388; | 3935 | return 0x00504740; |
3468 | } | 3936 | } |
3469 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) | 3937 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) |
3470 | { | 3938 | { |
3471 | return 0x0050438c; | 3939 | return 0x00504744; |
3472 | } | 3940 | } |
3473 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) | 3941 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) |
3474 | { | 3942 | { |
3475 | return 0x00504390; | 3943 | return 0x00504748; |
3476 | } | 3944 | } |
3477 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) | 3945 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) |
3478 | { | 3946 | { |
3479 | return 0x00504394; | 3947 | return 0x0050474c; |
3948 | } | ||
3949 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) | ||
3950 | { | ||
3951 | return 0x00504678; | ||
3952 | } | ||
3953 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) | ||
3954 | { | ||
3955 | return 0x00504694; | ||
3480 | } | 3956 | } |
3481 | static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status_s1_r(void) | 3957 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) |
3482 | { | 3958 | { |
3483 | return 0x005047c4; | 3959 | return 0x005046f0; |
3484 | } | 3960 | } |
3485 | static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status1_r(void) | 3961 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) |
3486 | { | 3962 | { |
3487 | return 0x005047d0; | 3963 | return 0x00504700; |
3964 | } | ||
3965 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) | ||
3966 | { | ||
3967 | return 0x005046f4; | ||
3968 | } | ||
3969 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) | ||
3970 | { | ||
3971 | return 0x00504704; | ||
3972 | } | ||
3973 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) | ||
3974 | { | ||
3975 | return 0x005046f8; | ||
3976 | } | ||
3977 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) | ||
3978 | { | ||
3979 | return 0x00504708; | ||
3980 | } | ||
3981 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) | ||
3982 | { | ||
3983 | return 0x005046fc; | ||
3984 | } | ||
3985 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) | ||
3986 | { | ||
3987 | return 0x0050470c; | ||
3488 | } | 3988 | } |
3489 | static inline u32 gr_fe_pwr_mode_r(void) | 3989 | static inline u32 gr_fe_pwr_mode_r(void) |
3490 | { | 3990 | { |
@@ -3584,7 +4084,7 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | |||
3584 | } | 4084 | } |
3585 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | 4085 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) |
3586 | { | 4086 | { |
3587 | return 0x00419f84; | 4087 | return 0x00419e10; |
3588 | } | 4088 | } |
3589 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | 4089 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) |
3590 | { | 4090 | { |
@@ -3648,7 +4148,7 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) | |||
3648 | } | 4148 | } |
3649 | static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) | 4149 | static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) |
3650 | { | 4150 | { |
3651 | return 0x00419bd8; | 4151 | return 0x00419c84; |
3652 | } | 4152 | } |
3653 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) | 4153 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) |
3654 | { | 4154 | { |
@@ -3664,7 +4164,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_ma | |||
3664 | } | 4164 | } |
3665 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) | 4165 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) |
3666 | { | 4166 | { |
3667 | return 0x00419ba4; | 4167 | return 0x00419f78; |
3668 | } | 4168 | } |
3669 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) | 4169 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) |
3670 | { | 4170 | { |
@@ -3680,10 +4180,10 @@ static inline u32 gr_gpcs_tc_debug0_r(void) | |||
3680 | } | 4180 | } |
3681 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) | 4181 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) |
3682 | { | 4182 | { |
3683 | return (v & 0x1ff) << 0; | 4183 | return (v & 0xff) << 0; |
3684 | } | 4184 | } |
3685 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) | 4185 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) |
3686 | { | 4186 | { |
3687 | return 0x1ff << 0; | 4187 | return 0xff << 0; |
3688 | } | 4188 | } |
3689 | #endif | 4189 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h index 02db6af6..2dbd759f 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | |||
@@ -50,6 +50,26 @@ | |||
50 | #ifndef _hw_ltc_gv11b_h_ | 50 | #ifndef _hw_ltc_gv11b_h_ |
51 | #define _hw_ltc_gv11b_h_ | 51 | #define _hw_ltc_gv11b_h_ |
52 | 52 | ||
53 | static inline u32 ltc_pltcg_base_v(void) | ||
54 | { | ||
55 | return 0x00140000; | ||
56 | } | ||
57 | static inline u32 ltc_pltcg_extent_v(void) | ||
58 | { | ||
59 | return 0x0017ffff; | ||
60 | } | ||
61 | static inline u32 ltc_ltc0_ltss_v(void) | ||
62 | { | ||
63 | return 0x00140200; | ||
64 | } | ||
65 | static inline u32 ltc_ltc0_lts0_v(void) | ||
66 | { | ||
67 | return 0x00140400; | ||
68 | } | ||
69 | static inline u32 ltc_ltcs_ltss_v(void) | ||
70 | { | ||
71 | return 0x0017e200; | ||
72 | } | ||
53 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | 73 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) |
54 | { | 74 | { |
55 | return 0x0014046c; | 75 | return 0x0014046c; |
@@ -550,4 +570,12 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) | |||
550 | { | 570 | { |
551 | return (r >> 16) & 0x1f; | 571 | return (r >> 16) & 0x1f; |
552 | } | 572 | } |
573 | static inline u32 ltc_ltca_g_axi_pctrl_r(void) | ||
574 | { | ||
575 | return 0x00160000; | ||
576 | } | ||
577 | static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) | ||
578 | { | ||
579 | return (v & 0xff) << 2; | ||
580 | } | ||
553 | #endif | 581 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h index 98bec43a..7fe4d158 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | |||
@@ -78,10 +78,6 @@ static inline u32 mc_intr_pfifo_pending_f(void) | |||
78 | { | 78 | { |
79 | return 0x100; | 79 | return 0x100; |
80 | } | 80 | } |
81 | static inline u32 mc_intr_hub_pending_f(void) | ||
82 | { | ||
83 | return 0x200; | ||
84 | } | ||
85 | static inline u32 mc_intr_pgraph_pending_f(void) | 81 | static inline u32 mc_intr_pgraph_pending_f(void) |
86 | { | 82 | { |
87 | return 0x1000; | 83 | return 0x1000; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index 3863c6d6..b3aaa7e6 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | |||
@@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i) | |||
72 | } | 72 | } |
73 | static inline u32 pbdma_gp_base__size_1_v(void) | 73 | static inline u32 pbdma_gp_base__size_1_v(void) |
74 | { | 74 | { |
75 | return 0x0000000e; | 75 | return 0x00000001; |
76 | } | 76 | } |
77 | static inline u32 pbdma_gp_base_offset_f(u32 v) | 77 | static inline u32 pbdma_gp_base_offset_f(u32 v) |
78 | { | 78 | { |
@@ -334,6 +334,38 @@ static inline u32 pbdma_userd_addr_f(u32 v) | |||
334 | { | 334 | { |
335 | return (v & 0x7fffff) << 9; | 335 | return (v & 0x7fffff) << 9; |
336 | } | 336 | } |
337 | static inline u32 pbdma_config_r(u32 i) | ||
338 | { | ||
339 | return 0x000400f4 + i*8192; | ||
340 | } | ||
341 | static inline u32 pbdma_config_l2_evict_first_f(void) | ||
342 | { | ||
343 | return 0x0; | ||
344 | } | ||
345 | static inline u32 pbdma_config_l2_evict_normal_f(void) | ||
346 | { | ||
347 | return 0x1; | ||
348 | } | ||
349 | static inline u32 pbdma_config_l2_evict_last_f(void) | ||
350 | { | ||
351 | return 0x2; | ||
352 | } | ||
353 | static inline u32 pbdma_config_ce_split_enable_f(void) | ||
354 | { | ||
355 | return 0x0; | ||
356 | } | ||
357 | static inline u32 pbdma_config_ce_split_disable_f(void) | ||
358 | { | ||
359 | return 0x10; | ||
360 | } | ||
361 | static inline u32 pbdma_config_auth_level_non_privileged_f(void) | ||
362 | { | ||
363 | return 0x0; | ||
364 | } | ||
365 | static inline u32 pbdma_config_auth_level_privileged_f(void) | ||
366 | { | ||
367 | return 0x100; | ||
368 | } | ||
337 | static inline u32 pbdma_userd_hi_r(u32 i) | 369 | static inline u32 pbdma_userd_hi_r(u32 i) |
338 | { | 370 | { |
339 | return 0x0004000c + i*8192; | 371 | return 0x0004000c + i*8192; |
@@ -478,6 +510,14 @@ static inline u32 pbdma_intr_0_signature_pending_f(void) | |||
478 | { | 510 | { |
479 | return 0x80000000; | 511 | return 0x80000000; |
480 | } | 512 | } |
513 | static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) | ||
514 | { | ||
515 | return 0x10000000; | ||
516 | } | ||
517 | static inline u32 pbdma_intr_1_r(u32 i) | ||
518 | { | ||
519 | return 0x00040148 + i*8192; | ||
520 | } | ||
481 | static inline u32 pbdma_intr_en_0_r(u32 i) | 521 | static inline u32 pbdma_intr_en_0_r(u32 i) |
482 | { | 522 | { |
483 | return 0x0004010c + i*8192; | 523 | return 0x0004010c + i*8192; |
@@ -526,6 +566,38 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) | |||
526 | { | 566 | { |
527 | return (v & 0x7fff) << 0; | 567 | return (v & 0x7fff) << 0; |
528 | } | 568 | } |
569 | static inline u32 pbdma_syncpointa_r(u32 i) | ||
570 | { | ||
571 | return 0x000400a4 + i*8192; | ||
572 | } | ||
573 | static inline u32 pbdma_syncpointa_payload_v(u32 r) | ||
574 | { | ||
575 | return (r >> 0) & 0xffffffff; | ||
576 | } | ||
577 | static inline u32 pbdma_syncpointb_r(u32 i) | ||
578 | { | ||
579 | return 0x000400a8 + i*8192; | ||
580 | } | ||
581 | static inline u32 pbdma_syncpointb_op_v(u32 r) | ||
582 | { | ||
583 | return (r >> 0) & 0x1; | ||
584 | } | ||
585 | static inline u32 pbdma_syncpointb_op_wait_v(void) | ||
586 | { | ||
587 | return 0x00000000; | ||
588 | } | ||
589 | static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) | ||
590 | { | ||
591 | return (r >> 4) & 0x1; | ||
592 | } | ||
593 | static inline u32 pbdma_syncpointb_wait_switch_en_v(void) | ||
594 | { | ||
595 | return 0x00000001; | ||
596 | } | ||
597 | static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) | ||
598 | { | ||
599 | return (r >> 8) & 0xfff; | ||
600 | } | ||
529 | static inline u32 pbdma_runlist_timeslice_r(u32 i) | 601 | static inline u32 pbdma_runlist_timeslice_r(u32 i) |
530 | { | 602 | { |
531 | return 0x000400f8 + i*8192; | 603 | return 0x000400f8 + i*8192; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h index 836c014b..4d11fef4 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | |||
@@ -52,7 +52,7 @@ | |||
52 | 52 | ||
53 | static inline u32 perf_pmasys_control_r(void) | 53 | static inline u32 perf_pmasys_control_r(void) |
54 | { | 54 | { |
55 | return 0x0024a000; | 55 | return 0x001b4000; |
56 | } | 56 | } |
57 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) | 57 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) |
58 | { | 58 | { |
@@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) | |||
84 | } | 84 | } |
85 | static inline u32 perf_pmasys_mem_block_r(void) | 85 | static inline u32 perf_pmasys_mem_block_r(void) |
86 | { | 86 | { |
87 | return 0x0024a070; | 87 | return 0x001b4070; |
88 | } | 88 | } |
89 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) | 89 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) |
90 | { | 90 | { |
@@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void) | |||
148 | } | 148 | } |
149 | static inline u32 perf_pmasys_outbase_r(void) | 149 | static inline u32 perf_pmasys_outbase_r(void) |
150 | { | 150 | { |
151 | return 0x0024a074; | 151 | return 0x001b4074; |
152 | } | 152 | } |
153 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | 153 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) |
154 | { | 154 | { |
@@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | |||
156 | } | 156 | } |
157 | static inline u32 perf_pmasys_outbaseupper_r(void) | 157 | static inline u32 perf_pmasys_outbaseupper_r(void) |
158 | { | 158 | { |
159 | return 0x0024a078; | 159 | return 0x001b4078; |
160 | } | 160 | } |
161 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | 161 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) |
162 | { | 162 | { |
@@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | |||
164 | } | 164 | } |
165 | static inline u32 perf_pmasys_outsize_r(void) | 165 | static inline u32 perf_pmasys_outsize_r(void) |
166 | { | 166 | { |
167 | return 0x0024a07c; | 167 | return 0x001b407c; |
168 | } | 168 | } |
169 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | 169 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) |
170 | { | 170 | { |
@@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | |||
172 | } | 172 | } |
173 | static inline u32 perf_pmasys_mem_bytes_r(void) | 173 | static inline u32 perf_pmasys_mem_bytes_r(void) |
174 | { | 174 | { |
175 | return 0x0024a084; | 175 | return 0x001b4084; |
176 | } | 176 | } |
177 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | 177 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) |
178 | { | 178 | { |
@@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | |||
180 | } | 180 | } |
181 | static inline u32 perf_pmasys_mem_bump_r(void) | 181 | static inline u32 perf_pmasys_mem_bump_r(void) |
182 | { | 182 | { |
183 | return 0x0024a088; | 183 | return 0x001b4088; |
184 | } | 184 | } |
185 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | 185 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) |
186 | { | 186 | { |
@@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | |||
188 | } | 188 | } |
189 | static inline u32 perf_pmasys_enginestatus_r(void) | 189 | static inline u32 perf_pmasys_enginestatus_r(void) |
190 | { | 190 | { |
191 | return 0x0024a0a4; | 191 | return 0x001b40a4; |
192 | } | 192 | } |
193 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) | 193 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) |
194 | { | 194 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index f107300e..e08c6854 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | |||
@@ -70,6 +70,10 @@ static inline u32 proj_lts_stride_v(void) | |||
70 | { | 70 | { |
71 | return 0x00000200; | 71 | return 0x00000200; |
72 | } | 72 | } |
73 | static inline u32 proj_fbpa_stride_v(void) | ||
74 | { | ||
75 | return 0x00004000; | ||
76 | } | ||
73 | static inline u32 proj_ppc_in_gpc_base_v(void) | 77 | static inline u32 proj_ppc_in_gpc_base_v(void) |
74 | { | 78 | { |
75 | return 0x00003000; | 79 | return 0x00003000; |
@@ -102,29 +106,37 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) | |||
102 | { | 106 | { |
103 | return 0x00001800; | 107 | return 0x00001800; |
104 | } | 108 | } |
109 | static inline u32 proj_host_num_engines_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
105 | static inline u32 proj_host_num_pbdma_v(void) | 113 | static inline u32 proj_host_num_pbdma_v(void) |
106 | { | 114 | { |
107 | return 0x0000000e; | 115 | return 0x00000001; |
108 | } | 116 | } |
109 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) | 117 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) |
110 | { | 118 | { |
111 | return 0x00000007; | 119 | return 0x00000002; |
112 | } | 120 | } |
113 | static inline u32 proj_scal_litter_num_fbps_v(void) | 121 | static inline u32 proj_scal_litter_num_fbps_v(void) |
114 | { | 122 | { |
115 | return 0x00000008; | 123 | return 0x00000001; |
124 | } | ||
125 | static inline u32 proj_scal_litter_num_fbpas_v(void) | ||
126 | { | ||
127 | return 0x00000001; | ||
116 | } | 128 | } |
117 | static inline u32 proj_scal_litter_num_gpcs_v(void) | 129 | static inline u32 proj_scal_litter_num_gpcs_v(void) |
118 | { | 130 | { |
119 | return 0x00000008; | 131 | return 0x00000001; |
120 | } | 132 | } |
121 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) | 133 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) |
122 | { | 134 | { |
123 | return 0x00000003; | 135 | return 0x00000001; |
124 | } | 136 | } |
125 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) | 137 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) |
126 | { | 138 | { |
127 | return 0x00000003; | 139 | return 0x00000002; |
128 | } | 140 | } |
129 | static inline u32 proj_scal_litter_num_zcull_banks_v(void) | 141 | static inline u32 proj_scal_litter_num_zcull_banks_v(void) |
130 | { | 142 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h index bb8b5dea..27ea4246 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | |||
@@ -542,6 +542,10 @@ static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) | |||
542 | { | 542 | { |
543 | return 0x20000000; | 543 | return 0x20000000; |
544 | } | 544 | } |
545 | static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) | ||
546 | { | ||
547 | return 0x30000000; | ||
548 | } | ||
545 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) | 549 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) |
546 | { | 550 | { |
547 | return (v & 0x1) << 30; | 551 | return (v & 0x1) << 30; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index a19e5251..6ccbc266 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | |||
@@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void) | |||
148 | } | 148 | } |
149 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) | 149 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) |
150 | { | 150 | { |
151 | return (v & 0xffffffff) << 0; | 151 | return (v & 0xff) << 0; |
152 | } | 152 | } |
153 | static inline u32 ram_in_page_dir_base_hi_w(void) | 153 | static inline u32 ram_in_page_dir_base_hi_w(void) |
154 | { | 154 | { |
@@ -354,6 +354,14 @@ static inline u32 ram_fc_allowed_syncpoints_w(void) | |||
354 | { | 354 | { |
355 | return 58; | 355 | return 58; |
356 | } | 356 | } |
357 | static inline u32 ram_fc_syncpointa_w(void) | ||
358 | { | ||
359 | return 41; | ||
360 | } | ||
361 | static inline u32 ram_fc_syncpointb_w(void) | ||
362 | { | ||
363 | return 42; | ||
364 | } | ||
357 | static inline u32 ram_fc_target_w(void) | 365 | static inline u32 ram_fc_target_w(void) |
358 | { | 366 | { |
359 | return 43; | 367 | return 43; |
@@ -436,7 +444,11 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void) | |||
436 | } | 444 | } |
437 | static inline u32 ram_rl_entry_size_v(void) | 445 | static inline u32 ram_rl_entry_size_v(void) |
438 | { | 446 | { |
439 | return 0x00000010; | 447 | return 0x00000008; |
448 | } | ||
449 | static inline u32 ram_rl_entry_chid_f(u32 v) | ||
450 | { | ||
451 | return (v & 0xfff) << 0; | ||
440 | } | 452 | } |
441 | static inline u32 ram_rl_entry_id_f(u32 v) | 453 | static inline u32 ram_rl_entry_id_f(u32 v) |
442 | { | 454 | { |
@@ -444,14 +456,34 @@ static inline u32 ram_rl_entry_id_f(u32 v) | |||
444 | } | 456 | } |
445 | static inline u32 ram_rl_entry_type_f(u32 v) | 457 | static inline u32 ram_rl_entry_type_f(u32 v) |
446 | { | 458 | { |
447 | return (v & 0x1) << 0; | 459 | return (v & 0x1) << 13; |
460 | } | ||
461 | static inline u32 ram_rl_entry_type_chid_f(void) | ||
462 | { | ||
463 | return 0x0; | ||
448 | } | 464 | } |
449 | static inline u32 ram_rl_entry_type_tsg_f(void) | 465 | static inline u32 ram_rl_entry_type_tsg_f(void) |
450 | { | 466 | { |
451 | return 0x1; | 467 | return 0x2000; |
468 | } | ||
469 | static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) | ||
470 | { | ||
471 | return (v & 0xf) << 14; | ||
472 | } | ||
473 | static inline u32 ram_rl_entry_timeslice_scale_3_f(void) | ||
474 | { | ||
475 | return 0xc000; | ||
476 | } | ||
477 | static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) | ||
478 | { | ||
479 | return (v & 0xff) << 18; | ||
480 | } | ||
481 | static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) | ||
482 | { | ||
483 | return 0x2000000; | ||
452 | } | 484 | } |
453 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) | 485 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) |
454 | { | 486 | { |
455 | return (v & 0xff) << 0; | 487 | return (v & 0x3f) << 26; |
456 | } | 488 | } |
457 | #endif | 489 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h index ee3dbc0e..2c464d2c 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | |||
@@ -54,6 +54,114 @@ static inline u32 therm_use_a_r(void) | |||
54 | { | 54 | { |
55 | return 0x00020798; | 55 | return 0x00020798; |
56 | } | 56 | } |
57 | static inline u32 therm_use_a_ext_therm_0_enable_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 therm_use_a_ext_therm_1_enable_f(void) | ||
62 | { | ||
63 | return 0x2; | ||
64 | } | ||
65 | static inline u32 therm_use_a_ext_therm_2_enable_f(void) | ||
66 | { | ||
67 | return 0x4; | ||
68 | } | ||
69 | static inline u32 therm_evt_ext_therm_0_r(void) | ||
70 | { | ||
71 | return 0x00020700; | ||
72 | } | ||
73 | static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) | ||
74 | { | ||
75 | return (v & 0x3f) << 24; | ||
76 | } | ||
77 | static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) | ||
78 | { | ||
79 | return 0x00000001; | ||
80 | } | ||
81 | static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) | ||
82 | { | ||
83 | return (v & 0x3) << 30; | ||
84 | } | ||
85 | static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) | ||
86 | { | ||
87 | return 0x00000000; | ||
88 | } | ||
89 | static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) | ||
90 | { | ||
91 | return 0x00000001; | ||
92 | } | ||
93 | static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) | ||
94 | { | ||
95 | return 0x00000002; | ||
96 | } | ||
97 | static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) | ||
98 | { | ||
99 | return 0x00000003; | ||
100 | } | ||
101 | static inline u32 therm_evt_ext_therm_1_r(void) | ||
102 | { | ||
103 | return 0x00020704; | ||
104 | } | ||
105 | static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) | ||
106 | { | ||
107 | return (v & 0x3f) << 24; | ||
108 | } | ||
109 | static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
113 | static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) | ||
114 | { | ||
115 | return (v & 0x3) << 30; | ||
116 | } | ||
117 | static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) | ||
118 | { | ||
119 | return 0x00000000; | ||
120 | } | ||
121 | static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) | ||
122 | { | ||
123 | return 0x00000001; | ||
124 | } | ||
125 | static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) | ||
126 | { | ||
127 | return 0x00000002; | ||
128 | } | ||
129 | static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) | ||
130 | { | ||
131 | return 0x00000003; | ||
132 | } | ||
133 | static inline u32 therm_evt_ext_therm_2_r(void) | ||
134 | { | ||
135 | return 0x00020708; | ||
136 | } | ||
137 | static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x3f) << 24; | ||
140 | } | ||
141 | static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) | ||
142 | { | ||
143 | return 0x00000003; | ||
144 | } | ||
145 | static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) | ||
146 | { | ||
147 | return (v & 0x3) << 30; | ||
148 | } | ||
149 | static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) | ||
150 | { | ||
151 | return 0x00000000; | ||
152 | } | ||
153 | static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) | ||
154 | { | ||
155 | return 0x00000001; | ||
156 | } | ||
157 | static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) | ||
158 | { | ||
159 | return 0x00000002; | ||
160 | } | ||
161 | static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) | ||
162 | { | ||
163 | return 0x00000003; | ||
164 | } | ||
57 | static inline u32 therm_weight_1_r(void) | 165 | static inline u32 therm_weight_1_r(void) |
58 | { | 166 | { |
59 | return 0x00020024; | 167 | return 0x00020024; |
@@ -106,6 +214,22 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | |||
106 | { | 214 | { |
107 | return 0x4; | 215 | return 0x4; |
108 | } | 216 | } |
217 | static inline u32 therm_gate_ctrl_eng_pwr_m(void) | ||
218 | { | ||
219 | return 0x3 << 4; | ||
220 | } | ||
221 | static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) | ||
222 | { | ||
223 | return 0x10; | ||
224 | } | ||
225 | static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) | ||
226 | { | ||
227 | return 0x00000002; | ||
228 | } | ||
229 | static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) | ||
230 | { | ||
231 | return 0x20; | ||
232 | } | ||
109 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | 233 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) |
110 | { | 234 | { |
111 | return (v & 0x1f) << 8; | 235 | return (v & 0x1f) << 8; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h index 65ffebb0..cb65cad8 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | |||
@@ -138,13 +138,37 @@ static inline u32 top_device_info_type_enum_graphics_f(void) | |||
138 | { | 138 | { |
139 | return 0x0; | 139 | return 0x0; |
140 | } | 140 | } |
141 | static inline u32 top_device_info_type_enum_copy0_v(void) | 141 | static inline u32 top_device_info_type_enum_copy2_v(void) |
142 | { | 142 | { |
143 | return 0x00000001; | 143 | return 0x00000003; |
144 | } | ||
145 | static inline u32 top_device_info_type_enum_copy2_f(void) | ||
146 | { | ||
147 | return 0xc; | ||
148 | } | ||
149 | static inline u32 top_device_info_type_enum_lce_v(void) | ||
150 | { | ||
151 | return 0x00000013; | ||
152 | } | ||
153 | static inline u32 top_device_info_type_enum_lce_f(void) | ||
154 | { | ||
155 | return 0x4c; | ||
156 | } | ||
157 | static inline u32 top_device_info_engine_v(u32 r) | ||
158 | { | ||
159 | return (r >> 5) & 0x1; | ||
144 | } | 160 | } |
145 | static inline u32 top_device_info_type_enum_copy0_f(void) | 161 | static inline u32 top_device_info_runlist_v(u32 r) |
146 | { | 162 | { |
147 | return 0x4; | 163 | return (r >> 4) & 0x1; |
164 | } | ||
165 | static inline u32 top_device_info_intr_v(u32 r) | ||
166 | { | ||
167 | return (r >> 3) & 0x1; | ||
168 | } | ||
169 | static inline u32 top_device_info_reset_v(u32 r) | ||
170 | { | ||
171 | return (r >> 2) & 0x1; | ||
148 | } | 172 | } |
149 | static inline u32 top_device_info_entry_v(u32 r) | 173 | static inline u32 top_device_info_entry_v(u32 r) |
150 | { | 174 | { |
@@ -158,10 +182,6 @@ static inline u32 top_device_info_entry_enum_v(void) | |||
158 | { | 182 | { |
159 | return 0x00000002; | 183 | return 0x00000002; |
160 | } | 184 | } |
161 | static inline u32 top_device_info_entry_engine_type_v(void) | ||
162 | { | ||
163 | return 0x00000002; | ||
164 | } | ||
165 | static inline u32 top_device_info_entry_data_v(void) | 185 | static inline u32 top_device_info_entry_data_v(void) |
166 | { | 186 | { |
167 | return 0x00000001; | 187 | return 0x00000001; |