diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-21 14:03:14 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 03:05:04 -0400 |
commit | f28efb987a13e87d10cc1c6d6e39fcbe9383934f (patch) | |
tree | cfe79197c4c13095540e07895657cc801b45f305 /drivers | |
parent | f2235085d136c50c63d4f66d4baa00f1b46bf22a (diff) |
gpu: nvgpu: gv11b: init update_sm_error_state gr ops
Support multiple SM and take care of SM hardware reg address changes
JIRA GPUT19X-75
Change-Id: I866011a85da06ca22bc10fda5ab59f84d0782902
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477686
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index eab78119..28284b45 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2534,6 +2534,85 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | |||
2534 | } | 2534 | } |
2535 | } | 2535 | } |
2536 | 2536 | ||
2537 | static int gv11b_gr_update_sm_error_state(struct gk20a *g, | ||
2538 | struct channel_gk20a *ch, u32 sm_id, | ||
2539 | struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) | ||
2540 | { | ||
2541 | u32 gpc, tpc, sm, offset; | ||
2542 | struct gr_gk20a *gr = &g->gr; | ||
2543 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | ||
2544 | int err = 0; | ||
2545 | |||
2546 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
2547 | |||
2548 | gr->sm_error_states[sm_id].hww_global_esr = | ||
2549 | sm_error_state->hww_global_esr; | ||
2550 | gr->sm_error_states[sm_id].hww_warp_esr = | ||
2551 | sm_error_state->hww_warp_esr; | ||
2552 | gr->sm_error_states[sm_id].hww_warp_esr_pc = | ||
2553 | sm_error_state->hww_warp_esr_pc; | ||
2554 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = | ||
2555 | sm_error_state->hww_global_esr_report_mask; | ||
2556 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = | ||
2557 | sm_error_state->hww_warp_esr_report_mask; | ||
2558 | |||
2559 | err = gr_gk20a_disable_ctxsw(g); | ||
2560 | if (err) { | ||
2561 | nvgpu_err(g, "unable to stop gr ctxsw"); | ||
2562 | goto fail; | ||
2563 | } | ||
2564 | |||
2565 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | ||
2566 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | ||
2567 | sm = g->gr.sm_to_cluster[sm_id].sm_index; | ||
2568 | |||
2569 | offset = gk20a_gr_gpc_offset(g, gpc) + | ||
2570 | gk20a_gr_tpc_offset(g, tpc) + | ||
2571 | gv11b_gr_sm_offset(g, sm); | ||
2572 | |||
2573 | if (gk20a_is_channel_ctx_resident(ch)) { | ||
2574 | gk20a_writel(g, | ||
2575 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | ||
2576 | gr->sm_error_states[sm_id].hww_global_esr); | ||
2577 | gk20a_writel(g, | ||
2578 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, | ||
2579 | gr->sm_error_states[sm_id].hww_warp_esr); | ||
2580 | gk20a_writel(g, | ||
2581 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset, | ||
2582 | gr->sm_error_states[sm_id].hww_warp_esr_pc); | ||
2583 | gk20a_writel(g, | ||
2584 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset, | ||
2585 | gr->sm_error_states[sm_id].hww_global_esr_report_mask); | ||
2586 | gk20a_writel(g, | ||
2587 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, | ||
2588 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask); | ||
2589 | } else { | ||
2590 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
2591 | if (err) | ||
2592 | goto enable_ctxsw; | ||
2593 | |||
2594 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
2595 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + | ||
2596 | offset, | ||
2597 | gr->sm_error_states[sm_id].hww_global_esr_report_mask, | ||
2598 | true); | ||
2599 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
2600 | gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() + | ||
2601 | offset, | ||
2602 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask, | ||
2603 | true); | ||
2604 | |||
2605 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
2606 | } | ||
2607 | |||
2608 | enable_ctxsw: | ||
2609 | err = gr_gk20a_enable_ctxsw(g); | ||
2610 | |||
2611 | fail: | ||
2612 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
2613 | return err; | ||
2614 | } | ||
2615 | |||
2537 | void gv11b_init_gr(struct gpu_ops *gops) | 2616 | void gv11b_init_gr(struct gpu_ops *gops) |
2538 | { | 2617 | { |
2539 | gp10b_init_gr(gops); | 2618 | gp10b_init_gr(gops); |
@@ -2598,4 +2677,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2598 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; | 2677 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; |
2599 | gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; | 2678 | gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; |
2600 | gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; | 2679 | gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; |
2680 | gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; | ||
2601 | } | 2681 | } |