diff options
author | Sam Payne <spayne@nvidia.com> | 2015-01-12 17:24:55 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:02:35 -0400 |
commit | edaf6188d54683bd955f1dc6673b3bb3ba18367e (patch) | |
tree | 68e95507fb3fed06da3d8a381d113a822d329ed6 /drivers | |
parent | 3764ce3de36d9b01948a78ec1ecf4ac4371b8e4d (diff) |
gpu: nvgpu: enable ce2 interrupts
enables non-blocking interrupts in ce2 all other
ce2 interrupts are cleared and not handled.
bug 200036089
Change-Id: I9f47b06c677c72ac523019e6a3f70fedd07830a2
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/671783
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 95 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | 2 |
11 files changed, 302 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4e2ce497..6632a43a 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -19,6 +19,7 @@ nvgpu-y := \ | |||
19 | gk20a/gk20a.o \ | 19 | gk20a/gk20a.o \ |
20 | gk20a/as_gk20a.o \ | 20 | gk20a/as_gk20a.o \ |
21 | gk20a/ctrl_gk20a.o \ | 21 | gk20a/ctrl_gk20a.o \ |
22 | gk20a/ce2_gk20a.o \ | ||
22 | gk20a/fifo_gk20a.o \ | 23 | gk20a/fifo_gk20a.o \ |
23 | gk20a/channel_gk20a.o \ | 24 | gk20a/channel_gk20a.o \ |
24 | gk20a/channel_sync_gk20a.o \ | 25 | gk20a/channel_sync_gk20a.o \ |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c new file mode 100644 index 00000000..75df4ce5 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -0,0 +1,95 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Copy Engine (gr host) | ||
3 | * | ||
4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | */ | ||
19 | |||
20 | /*TODO: remove uncecessary */ | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/slab.h> | ||
23 | #include <linux/scatterlist.h> | ||
24 | #include <trace/events/gk20a.h> | ||
25 | #include <linux/dma-mapping.h> | ||
26 | #include <linux/nvhost.h> | ||
27 | |||
28 | #include "gk20a.h" | ||
29 | #include "debug_gk20a.h" | ||
30 | #include "semaphore_gk20a.h" | ||
31 | #include "hw_ce2_gk20a.h" | ||
32 | #include "hw_pbdma_gk20a.h" | ||
33 | #include "hw_ccsr_gk20a.h" | ||
34 | #include "hw_ram_gk20a.h" | ||
35 | #include "hw_proj_gk20a.h" | ||
36 | #include "hw_top_gk20a.h" | ||
37 | #include "hw_mc_gk20a.h" | ||
38 | #include "hw_gr_gk20a.h" | ||
39 | |||
40 | static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
41 | { | ||
42 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); | ||
43 | |||
44 | /* wake theads waiting in this channel */ | ||
45 | gk20a_channel_semaphore_wakeup(g); | ||
46 | return ce2_intr_status_nonblockpipe_pending_f(); | ||
47 | } | ||
48 | |||
49 | static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
50 | { | ||
51 | gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); | ||
52 | |||
53 | return ce2_intr_status_blockpipe_pending_f(); | ||
54 | } | ||
55 | |||
56 | static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) | ||
57 | { | ||
58 | gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); | ||
59 | |||
60 | return ce2_intr_status_launcherr_pending_f(); | ||
61 | } | ||
62 | |||
63 | void gk20a_ce2_isr(struct gk20a *g) | ||
64 | { | ||
65 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | ||
66 | u32 clear_intr = 0; | ||
67 | |||
68 | gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); | ||
69 | |||
70 | /* clear blocking interrupts: they exibit broken behavior */ | ||
71 | if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) | ||
72 | clear_intr |= ce2_blockpipe_isr(g, ce2_intr); | ||
73 | |||
74 | if (ce2_intr & ce2_intr_status_launcherr_pending_f()) | ||
75 | clear_intr |= ce2_launcherr_isr(g, ce2_intr); | ||
76 | |||
77 | gk20a_writel(g, ce2_intr_status_r(), clear_intr); | ||
78 | return; | ||
79 | } | ||
80 | |||
81 | void gk20a_ce2_nonstall_isr(struct gk20a *g) | ||
82 | { | ||
83 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | ||
84 | u32 clear_intr = 0; | ||
85 | |||
86 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | ||
87 | |||
88 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) | ||
89 | clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); | ||
90 | |||
91 | gk20a_writel(g, ce2_intr_status_r(), clear_intr); | ||
92 | |||
93 | return; | ||
94 | } | ||
95 | |||
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h new file mode 100644 index 00000000..0a9ec62a --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gk20a/fifo_gk20a.h | ||
3 | * | ||
4 | * GK20A graphics copy engine (gr host) | ||
5 | * | ||
6 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms and conditions of the GNU General Public License, | ||
10 | * version 2, as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., | ||
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
20 | */ | ||
21 | #ifndef __CE2_GK20A_H__ | ||
22 | #define __CE2_GK20A_H__ | ||
23 | |||
24 | #include "channel_gk20a.h" | ||
25 | #include "tsg_gk20a.h" | ||
26 | |||
27 | void gk20a_ce2_isr(struct gk20a *g); | ||
28 | void gk20a_ce2_nonstall_isr(struct gk20a *g); | ||
29 | |||
30 | #endif /*__CE2_GK20A_H__*/ | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 184ef168..3c1186ed 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -37,6 +37,7 @@ struct acr_gm20b; | |||
37 | 37 | ||
38 | #include "as_gk20a.h" | 38 | #include "as_gk20a.h" |
39 | #include "clk_gk20a.h" | 39 | #include "clk_gk20a.h" |
40 | #include "ce2_gk20a.h" | ||
40 | #include "fifo_gk20a.h" | 41 | #include "fifo_gk20a.h" |
41 | #include "tsg_gk20a.h" | 42 | #include "tsg_gk20a.h" |
42 | #include "gr_gk20a.h" | 43 | #include "gr_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h new file mode 100644 index 00000000..df1fa836 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ce2_gk20a_h_ | ||
51 | #define _hw_ce2_gk20a_h_ | ||
52 | |||
53 | static inline u32 ce2_intr_status_r(void) | ||
54 | { | ||
55 | return 0x00106908; | ||
56 | } | ||
57 | static inline u32 ce2_intr_status_blockpipe_pending_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 ce2_intr_status_blockpipe_reset_f(void) | ||
62 | { | ||
63 | return 0x1; | ||
64 | } | ||
65 | static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) | ||
66 | { | ||
67 | return 0x2; | ||
68 | } | ||
69 | static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) | ||
70 | { | ||
71 | return 0x2; | ||
72 | } | ||
73 | static inline u32 ce2_intr_status_launcherr_pending_f(void) | ||
74 | { | ||
75 | return 0x4; | ||
76 | } | ||
77 | static inline u32 ce2_intr_status_launcherr_reset_f(void) | ||
78 | { | ||
79 | return 0x4; | ||
80 | } | ||
81 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 1de9e794..38ffd524 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -1302,6 +1302,10 @@ static inline u32 gr_ds_zbc_color_r_val_f(u32 v) | |||
1302 | { | 1302 | { |
1303 | return (v & 0xffffffff) << 0; | 1303 | return (v & 0xffffffff) << 0; |
1304 | } | 1304 | } |
1305 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1306 | { | ||
1307 | return 0x00000028; | ||
1308 | } | ||
1305 | static inline u32 gr_ds_zbc_color_g_r(void) | 1309 | static inline u32 gr_ds_zbc_color_g_r(void) |
1306 | { | 1310 | { |
1307 | return 0x00405808; | 1311 | return 0x00405808; |
@@ -1350,10 +1354,6 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | |||
1350 | { | 1354 | { |
1351 | return 0x00000004; | 1355 | return 0x00000004; |
1352 | } | 1356 | } |
1353 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1354 | { | ||
1355 | return 0x00000028; | ||
1356 | } | ||
1357 | static inline u32 gr_ds_zbc_z_r(void) | 1357 | static inline u32 gr_ds_zbc_z_r(void) |
1358 | { | 1358 | { |
1359 | return 0x00405818; | 1359 | return 0x00405818; |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h index 479db499..97517a77 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 899eeff7..9f9e756b 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A memory interface | 2 | * GK20A memory interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -73,6 +73,8 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) | |||
73 | 73 | ||
74 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 74 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
75 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | 75 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); |
76 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)) | ||
77 | gk20a_ce2_isr(g); | ||
76 | if (mc_intr_0 & mc_intr_0_pfifo_pending_f()) | 78 | if (mc_intr_0 & mc_intr_0_pfifo_pending_f()) |
77 | gk20a_fifo_isr(g); | 79 | gk20a_fifo_isr(g); |
78 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) | 80 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) |
@@ -107,6 +109,8 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g) | |||
107 | gk20a_fifo_nonstall_isr(g); | 109 | gk20a_fifo_nonstall_isr(g); |
108 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 110 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
109 | gk20a_gr_nonstall_isr(g); | 111 | gk20a_gr_nonstall_isr(g); |
112 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)) | ||
113 | gk20a_ce2_nonstall_isr(g); | ||
110 | 114 | ||
111 | gk20a_writel(g, mc_intr_en_1_r(), | 115 | gk20a_writel(g, mc_intr_en_1_r(), |
112 | mc_intr_en_1_inta_hardware_f()); | 116 | mc_intr_en_1_inta_hardware_f()); |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h new file mode 100644 index 00000000..ca0212f8 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ce2_gm20b_h_ | ||
51 | #define _hw_ce2_gm20b_h_ | ||
52 | |||
53 | static inline u32 ce2_intr_status_r(void) | ||
54 | { | ||
55 | return 0x00106908; | ||
56 | } | ||
57 | static inline u32 ce2_intr_status_blockpipe_pending_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 ce2_intr_status_blockpipe_reset_f(void) | ||
62 | { | ||
63 | return 0x1; | ||
64 | } | ||
65 | static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) | ||
66 | { | ||
67 | return 0x2; | ||
68 | } | ||
69 | static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) | ||
70 | { | ||
71 | return 0x2; | ||
72 | } | ||
73 | static inline u32 ce2_intr_status_launcherr_pending_f(void) | ||
74 | { | ||
75 | return 0x4; | ||
76 | } | ||
77 | static inline u32 ce2_intr_status_launcherr_reset_f(void) | ||
78 | { | ||
79 | return 0x4; | ||
80 | } | ||
81 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 34cf20de..714ceb16 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -1302,10 +1302,6 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | |||
1302 | { | 1302 | { |
1303 | return 0x00000004; | 1303 | return 0x00000004; |
1304 | } | 1304 | } |
1305 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1306 | { | ||
1307 | return 0x00000028; | ||
1308 | } | ||
1309 | static inline u32 gr_ds_zbc_z_r(void) | 1305 | static inline u32 gr_ds_zbc_z_r(void) |
1310 | { | 1306 | { |
1311 | return 0x00405818; | 1307 | return 0x00405818; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h index 96e21899..3750de06 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |