diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-21 14:31:55 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 03:05:05 -0400 |
commit | ec71ac29576afa676e056b42c13f073a17ba57e9 (patch) | |
tree | 63ea3e73fb827e8e2844f7a5f1f1eab57014dbbd /drivers | |
parent | 8f0f88d61e452e81d03670b4a1413fc0ced631c2 (diff) |
gpu: nvgpu: gv11b: init record_sm_error_state gr ops
Take care of t19x sm reg address changes and support multiple SM
JIRA GPUT19X-75
Change-Id: I675b76b90d08fe75331f0023f1fe722497d06373
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477673
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c1dc7920..8cc1cfde 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2673,6 +2673,45 @@ static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | |||
2673 | return err; | 2673 | return err; |
2674 | } | 2674 | } |
2675 | 2675 | ||
2676 | static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | ||
2677 | { | ||
2678 | int sm_id; | ||
2679 | struct gr_gk20a *gr = &g->gr; | ||
2680 | u32 offset, sm, sm_per_tpc; | ||
2681 | u32 gpc_tpc_offset; | ||
2682 | |||
2683 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
2684 | |||
2685 | sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | ||
2686 | gpc_tpc_offset = gk20a_gr_gpc_offset(g, gpc) + | ||
2687 | gk20a_gr_tpc_offset(g, tpc); | ||
2688 | |||
2689 | sm_id = gr_gpc0_tpc0_sm_cfg_tpc_id_v(gk20a_readl(g, | ||
2690 | gr_gpc0_tpc0_sm_cfg_r() + gpc_tpc_offset)); | ||
2691 | |||
2692 | sm = sm_id % sm_per_tpc; | ||
2693 | |||
2694 | offset = gpc_tpc_offset + gv11b_gr_sm_offset(g, sm); | ||
2695 | |||
2696 | gr->sm_error_states[sm_id].hww_global_esr = gk20a_readl(g, | ||
2697 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); | ||
2698 | |||
2699 | gr->sm_error_states[sm_id].hww_warp_esr = gk20a_readl(g, | ||
2700 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset); | ||
2701 | |||
2702 | gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, | ||
2703 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset); | ||
2704 | |||
2705 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, | ||
2706 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset); | ||
2707 | |||
2708 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, | ||
2709 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset); | ||
2710 | |||
2711 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
2712 | |||
2713 | return 0; | ||
2714 | } | ||
2676 | void gv11b_init_gr(struct gpu_ops *gops) | 2715 | void gv11b_init_gr(struct gpu_ops *gops) |
2677 | { | 2716 | { |
2678 | gp10b_init_gr(gops); | 2717 | gp10b_init_gr(gops); |
@@ -2739,4 +2778,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2739 | gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; | 2778 | gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; |
2740 | gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; | 2779 | gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; |
2741 | gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; | 2780 | gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; |
2781 | gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; | ||
2742 | } | 2782 | } |