nvgpu: Add dummy variables to accomodate PS3.5 structure

Change-Id: I437f2aba6a63de87033721fa9a29c565cf8f4256
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694546
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 25 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
index 7338fa3a..5b757cbf 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
@@ -59,7 +59,7 @@
                         BIT(CTRL_CLK_VIN_ID_GPC3) | \
                         BIT(CTRL_CLK_VIN_ID_GPC4) | \
                         BIT(CTRL_CLK_VIN_ID_GPC5))
-#define CTRL_CLK_LUT_NUM_ENTRIES 0x50
+#define CTRL_CLK_LUT_NUM_ENTRIES (100)
 #define CTRL_CLK_VIN_STEP_SIZE_UV (10000)
 #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000)
 #define CTRL_CLK_FLL_TYPE_DISABLED 0
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
index cf39658f..342ca199 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
@@ -50,12 +50,13 @@ struct nv_pmu_super_surface {
                 struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set;
                 struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set;
                 struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set;
+                u8 clk_rsvd2[0x200];
                 struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set;
                 struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set;
                 struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set;
-
                 struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status;
                 struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status;
+                u8 clk_rsvd1[0x800];
                 struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status;
                 u8 clk_rsvd[0x4660];
         } clk;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
index dde85435..471892ca 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -128,12 +128,30 @@ struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
         u32 slave_idxs_mask;
 };
 
+struct nv_pmu_clk_clk_domain_35_prog_boardobj_set {
+        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
+        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
+        u8 dummy;
+};
+
+struct nv_pmu_clk_clk_domain_35_master_boardobj_set {
+        struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
+        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
+        u32 master_slave_domains_grp_mask;
+};
+
+
 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
         struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
         u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
         u8 master_idx;
 };
 
+struct nv_pmu_clk_clk_domain_35_slave_boardobj_set {
+        struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
+        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
+        u8 master_idx;
+};
 union nv_pmu_clk_clk_domain_boardobj_set_union {
         struct nv_pmu_boardobj board_obj;
         struct nv_pmu_clk_clk_domain_boardobj_set super;
@@ -142,6 +160,9 @@ union nv_pmu_clk_clk_domain_boardobj_set_union {
         struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
         struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master;
         struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave;
+        struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog;
+        struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master;
+        struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave;
 };
 
 NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
@@ -504,6 +525,7 @@ struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header {
 struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
         struct nv_pmu_boardobj_query super;
         u8 current_regime_id;
+        bool b_dvco_min_reached;
         u16 min_freq_mhz;
         struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)];
 };