diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-03-18 18:28:23 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 22:00:43 -0400 |
commit | e9f8cb79f18da8b37e575ad15f57da8e82e8296e (patch) | |
tree | ab8441adca22169d9a11b53bb737d182e4b740e5 /drivers | |
parent | 84aae5639e95c8130bad8b6ea7808a240bef6bd2 (diff) |
gpu: nvgpu: Do not touch gr status mask
GR status disable mask was never set, so driver always disabled all
engines from status rollup.
Change-Id: I500a127be9253294f73d1f42ce89b886471a9117
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/719141
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 |
2 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0aa0037f..4933d442 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4214,10 +4214,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4214 | gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF); | 4214 | gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF); |
4215 | gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF); | 4215 | gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF); |
4216 | 4216 | ||
4217 | /* ignore status from some units */ | ||
4218 | data = gk20a_readl(g, gr_status_mask_r()); | ||
4219 | gk20a_writel(g, gr_status_mask_r(), data & gr->status_disable_mask); | ||
4220 | |||
4221 | gr_gk20a_load_zbc_table(g, gr); | 4217 | gr_gk20a_load_zbc_table(g, gr); |
4222 | 4218 | ||
4223 | g->ops.ltc.init_cbc(g, gr); | 4219 | g->ops.ltc.init_cbc(g, gr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index eac710d1..59176af8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -279,8 +279,6 @@ struct gr_gk20a { | |||
279 | s32 max_used_color_index; | 279 | s32 max_used_color_index; |
280 | s32 max_used_depth_index; | 280 | s32 max_used_depth_index; |
281 | 281 | ||
282 | u32 status_disable_mask; | ||
283 | |||
284 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ | 282 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ |
285 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; | 283 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; |
286 | u32 channel_tlb_flush_index; | 284 | u32 channel_tlb_flush_index; |