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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-03-29 19:02:34 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-04-08 12:42:41 -0400
commite8bac374c0ed24f05bf389e1e8b5aca47f61bd3a (patch)
tree36b6e111f8706c0560ee552bc9d6e15b87fc9621 /drivers
parent2382a8433fddaee3baecff6ae941944850787ab7 (diff)
gpu: nvgpu: Use device instead of platform_device
Use struct device instead of struct platform_device wherever possible. This allows adding other bus types later. Change-Id: I1657287a68d85a542cdbdd8a00d1902c3d6e00ed Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120466
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/cde_gk20a.c110
-rw-r--r--drivers/gpu/nvgpu/gk20a/cde_gk20a.h6
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c69
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/clk_gk20a.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c10
-rw-r--r--drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c31
-rw-r--r--drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.c64
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.h8
-rw-r--r--drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c327
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h44
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_scale.c84
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_scale.h27
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c213
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c16
-rw-r--r--drivers/gpu/nvgpu/gk20a/hal.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/ltc_gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/mc_gk20a.c12
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c32
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/platform_gk20a.h63
-rw-r--r--drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c10
-rw-r--r--drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c144
-rw-r--r--drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c14
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/regops_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/tsg_gk20a.c6
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.c2
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c4
-rw-r--r--drivers/gpu/nvgpu/gm20b/ltc_gm20b.c8
-rw-r--r--drivers/gpu/nvgpu/gm20b/mm_gm20b.c6
-rw-r--r--drivers/gpu/nvgpu/platform_tegra.h8
-rw-r--r--drivers/gpu/nvgpu/vgpu/vgpu.c62
37 files changed, 691 insertions, 736 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
index a2f7e7a4..7818f046 100644
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Color decompression engine support 2 * Color decompression engine support
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -227,14 +227,14 @@ static int gk20a_init_cde_buf(struct gk20a_cde_ctx *cde_ctx,
227 /* check that the file can hold the buf */ 227 /* check that the file can hold the buf */
228 if (buf->data_byte_offset != 0 && 228 if (buf->data_byte_offset != 0 &&
229 buf->data_byte_offset + buf->num_bytes > img->size) { 229 buf->data_byte_offset + buf->num_bytes > img->size) {
230 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid data section. buffer idx = %d", 230 gk20a_warn(cde_ctx->dev, "cde: invalid data section. buffer idx = %d",
231 cde_ctx->num_bufs); 231 cde_ctx->num_bufs);
232 return -EINVAL; 232 return -EINVAL;
233 } 233 }
234 234
235 /* check that we have enough buf elems available */ 235 /* check that we have enough buf elems available */
236 if (cde_ctx->num_bufs >= MAX_CDE_BUFS) { 236 if (cde_ctx->num_bufs >= MAX_CDE_BUFS) {
237 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid data section. buffer idx = %d", 237 gk20a_warn(cde_ctx->dev, "cde: invalid data section. buffer idx = %d",
238 cde_ctx->num_bufs); 238 cde_ctx->num_bufs);
239 return -ENOMEM; 239 return -ENOMEM;
240 } 240 }
@@ -243,7 +243,7 @@ static int gk20a_init_cde_buf(struct gk20a_cde_ctx *cde_ctx,
243 mem = cde_ctx->mem + cde_ctx->num_bufs; 243 mem = cde_ctx->mem + cde_ctx->num_bufs;
244 err = gk20a_gmmu_alloc_map(cde_ctx->vm, buf->num_bytes, mem); 244 err = gk20a_gmmu_alloc_map(cde_ctx->vm, buf->num_bytes, mem);
245 if (err) { 245 if (err) {
246 gk20a_warn(&cde_ctx->pdev->dev, "cde: could not allocate device memory. buffer idx = %d", 246 gk20a_warn(cde_ctx->dev, "cde: could not allocate device memory. buffer idx = %d",
247 cde_ctx->num_bufs); 247 cde_ctx->num_bufs);
248 return -ENOMEM; 248 return -ENOMEM;
249 } 249 }
@@ -281,7 +281,7 @@ static int gk20a_replace_data(struct gk20a_cde_ctx *cde_ctx, void *target,
281 current_value = (u64)(current_value >> 32) | 281 current_value = (u64)(current_value >> 32) |
282 (u64)(current_value << 32); 282 (u64)(current_value << 32);
283 } else { 283 } else {
284 gk20a_warn(&cde_ctx->pdev->dev, "cde: unknown type. type=%d", 284 gk20a_warn(cde_ctx->dev, "cde: unknown type. type=%d",
285 type); 285 type);
286 return -EINVAL; 286 return -EINVAL;
287 } 287 }
@@ -315,7 +315,7 @@ static int gk20a_init_cde_replace(struct gk20a_cde_ctx *cde_ctx,
315 315
316 if (replace->target_buf >= cde_ctx->num_bufs || 316 if (replace->target_buf >= cde_ctx->num_bufs ||
317 replace->source_buf >= cde_ctx->num_bufs) { 317 replace->source_buf >= cde_ctx->num_bufs) {
318 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid buffer. target_buf=%u, source_buf=%u, num_bufs=%d", 318 gk20a_warn(cde_ctx->dev, "cde: invalid buffer. target_buf=%u, source_buf=%u, num_bufs=%d",
319 replace->target_buf, replace->source_buf, 319 replace->target_buf, replace->source_buf,
320 cde_ctx->num_bufs); 320 cde_ctx->num_bufs);
321 return -EINVAL; 321 return -EINVAL;
@@ -327,7 +327,7 @@ static int gk20a_init_cde_replace(struct gk20a_cde_ctx *cde_ctx,
327 327
328 if (source_mem->size < (replace->source_byte_offset + 3) || 328 if (source_mem->size < (replace->source_byte_offset + 3) ||
329 target_mem->size < (replace->target_byte_offset + 3)) { 329 target_mem->size < (replace->target_byte_offset + 3)) {
330 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid buffer offsets. target_buf_offs=%lld, source_buf_offs=%lld, source_buf_size=%zu, dest_buf_size=%zu", 330 gk20a_warn(cde_ctx->dev, "cde: invalid buffer offsets. target_buf_offs=%lld, source_buf_offs=%lld, source_buf_size=%zu, dest_buf_size=%zu",
331 replace->target_byte_offset, 331 replace->target_byte_offset,
332 replace->source_byte_offset, 332 replace->source_byte_offset,
333 source_mem->size, 333 source_mem->size,
@@ -344,7 +344,7 @@ static int gk20a_init_cde_replace(struct gk20a_cde_ctx *cde_ctx,
344 replace->shift, replace->mask, 344 replace->shift, replace->mask,
345 vaddr); 345 vaddr);
346 if (err) { 346 if (err) {
347 gk20a_warn(&cde_ctx->pdev->dev, "cde: replace failed. err=%d, target_buf=%u, target_buf_offs=%lld, source_buf=%u, source_buf_offs=%lld", 347 gk20a_warn(cde_ctx->dev, "cde: replace failed. err=%d, target_buf=%u, target_buf_offs=%lld, source_buf=%u, source_buf_offs=%lld",
348 err, replace->target_buf, 348 err, replace->target_buf,
349 replace->target_byte_offset, 349 replace->target_byte_offset,
350 replace->source_buf, 350 replace->source_buf,
@@ -431,7 +431,7 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
431 param->shift, param->mask, new_data); 431 param->shift, param->mask, new_data);
432 432
433 if (err) { 433 if (err) {
434 gk20a_warn(&cde_ctx->pdev->dev, "cde: patch failed. err=%d, idx=%d, id=%d, target_buf=%u, target_buf_offs=%lld, patch_value=%llu", 434 gk20a_warn(cde_ctx->dev, "cde: patch failed. err=%d, idx=%d, id=%d, target_buf=%u, target_buf_offs=%lld, patch_value=%llu",
435 err, i, param->id, param->target_buf, 435 err, i, param->id, param->target_buf,
436 param->target_byte_offset, new_data); 436 param->target_byte_offset, new_data);
437 return err; 437 return err;
@@ -448,7 +448,7 @@ static int gk20a_init_cde_param(struct gk20a_cde_ctx *cde_ctx,
448 struct mem_desc *target_mem; 448 struct mem_desc *target_mem;
449 449
450 if (param->target_buf >= cde_ctx->num_bufs) { 450 if (param->target_buf >= cde_ctx->num_bufs) {
451 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid buffer parameter. param idx = %d, target_buf=%u, num_bufs=%u", 451 gk20a_warn(cde_ctx->dev, "cde: invalid buffer parameter. param idx = %d, target_buf=%u, num_bufs=%u",
452 cde_ctx->num_params, param->target_buf, 452 cde_ctx->num_params, param->target_buf,
453 cde_ctx->num_bufs); 453 cde_ctx->num_bufs);
454 return -EINVAL; 454 return -EINVAL;
@@ -456,7 +456,7 @@ static int gk20a_init_cde_param(struct gk20a_cde_ctx *cde_ctx,
456 456
457 target_mem = cde_ctx->mem + param->target_buf; 457 target_mem = cde_ctx->mem + param->target_buf;
458 if (target_mem->size< (param->target_byte_offset + 3)) { 458 if (target_mem->size< (param->target_byte_offset + 3)) {
459 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid buffer parameter. param idx = %d, target_buf_offs=%lld, target_buf_size=%zu", 459 gk20a_warn(cde_ctx->dev, "cde: invalid buffer parameter. param idx = %d, target_buf_offs=%lld, target_buf_size=%zu",
460 cde_ctx->num_params, param->target_byte_offset, 460 cde_ctx->num_params, param->target_byte_offset,
461 target_mem->size); 461 target_mem->size);
462 return -EINVAL; 462 return -EINVAL;
@@ -464,14 +464,14 @@ static int gk20a_init_cde_param(struct gk20a_cde_ctx *cde_ctx,
464 464
465 /* does this parameter fit into our parameter structure */ 465 /* does this parameter fit into our parameter structure */
466 if (cde_ctx->num_params >= MAX_CDE_PARAMS) { 466 if (cde_ctx->num_params >= MAX_CDE_PARAMS) {
467 gk20a_warn(&cde_ctx->pdev->dev, "cde: no room for new parameters param idx = %d", 467 gk20a_warn(cde_ctx->dev, "cde: no room for new parameters param idx = %d",
468 cde_ctx->num_params); 468 cde_ctx->num_params);
469 return -ENOMEM; 469 return -ENOMEM;
470 } 470 }
471 471
472 /* is the given id valid? */ 472 /* is the given id valid? */
473 if (param->id >= NUM_RESERVED_PARAMS + MAX_CDE_USER_PARAMS) { 473 if (param->id >= NUM_RESERVED_PARAMS + MAX_CDE_USER_PARAMS) {
474 gk20a_warn(&cde_ctx->pdev->dev, "cde: parameter id is not valid. param idx = %d, id=%u, max=%u", 474 gk20a_warn(cde_ctx->dev, "cde: parameter id is not valid. param idx = %d, id=%u, max=%u",
475 param->id, cde_ctx->num_params, 475 param->id, cde_ctx->num_params,
476 NUM_RESERVED_PARAMS + MAX_CDE_USER_PARAMS); 476 NUM_RESERVED_PARAMS + MAX_CDE_USER_PARAMS);
477 return -EINVAL; 477 return -EINVAL;
@@ -498,7 +498,7 @@ static int gk20a_init_cde_required_class(struct gk20a_cde_ctx *cde_ctx,
498 498
499 err = gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx); 499 err = gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx);
500 if (err) { 500 if (err) {
501 gk20a_warn(&cde_ctx->pdev->dev, "cde: failed to allocate ctx. err=%d", 501 gk20a_warn(cde_ctx->dev, "cde: failed to allocate ctx. err=%d",
502 err); 502 err);
503 return err; 503 return err;
504 } 504 }
@@ -524,7 +524,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx,
524 gpfifo = &cde_ctx->convert_cmd; 524 gpfifo = &cde_ctx->convert_cmd;
525 num_entries = &cde_ctx->convert_cmd_num_entries; 525 num_entries = &cde_ctx->convert_cmd_num_entries;
526 } else { 526 } else {
527 gk20a_warn(&cde_ctx->pdev->dev, "cde: unknown command. op=%u", 527 gk20a_warn(cde_ctx->dev, "cde: unknown command. op=%u",
528 op); 528 op);
529 return -EINVAL; 529 return -EINVAL;
530 } 530 }
@@ -533,7 +533,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx,
533 *gpfifo = kzalloc(sizeof(struct nvgpu_gpfifo) * num_elems, 533 *gpfifo = kzalloc(sizeof(struct nvgpu_gpfifo) * num_elems,
534 GFP_KERNEL); 534 GFP_KERNEL);
535 if (!*gpfifo) { 535 if (!*gpfifo) {
536 gk20a_warn(&cde_ctx->pdev->dev, "cde: could not allocate memory for gpfifo entries"); 536 gk20a_warn(cde_ctx->dev, "cde: could not allocate memory for gpfifo entries");
537 return -ENOMEM; 537 return -ENOMEM;
538 } 538 }
539 539
@@ -543,7 +543,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx,
543 543
544 /* validate the current entry */ 544 /* validate the current entry */
545 if (cmd_elem->target_buf >= cde_ctx->num_bufs) { 545 if (cmd_elem->target_buf >= cde_ctx->num_bufs) {
546 gk20a_warn(&cde_ctx->pdev->dev, "cde: target buffer is not available (target=%u, num_bufs=%u)", 546 gk20a_warn(cde_ctx->dev, "cde: target buffer is not available (target=%u, num_bufs=%u)",
547 cmd_elem->target_buf, cde_ctx->num_bufs); 547 cmd_elem->target_buf, cde_ctx->num_bufs);
548 return -EINVAL; 548 return -EINVAL;
549 } 549 }
@@ -551,7 +551,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx,
551 target_mem = cde_ctx->mem + cmd_elem->target_buf; 551 target_mem = cde_ctx->mem + cmd_elem->target_buf;
552 if (target_mem->size< 552 if (target_mem->size<
553 cmd_elem->target_byte_offset + cmd_elem->num_bytes) { 553 cmd_elem->target_byte_offset + cmd_elem->num_bytes) {
554 gk20a_warn(&cde_ctx->pdev->dev, "cde: target buffer cannot hold all entries (target_size=%zu, target_byte_offset=%lld, num_bytes=%llu)", 554 gk20a_warn(cde_ctx->dev, "cde: target buffer cannot hold all entries (target_size=%zu, target_byte_offset=%lld, num_bytes=%llu)",
555 target_mem->size, 555 target_mem->size,
556 cmd_elem->target_byte_offset, 556 cmd_elem->target_byte_offset,
557 cmd_elem->num_bytes); 557 cmd_elem->num_bytes);
@@ -585,7 +585,7 @@ static int gk20a_cde_pack_cmdbufs(struct gk20a_cde_ctx *cde_ctx)
585 /* allocate buffer that has space for both */ 585 /* allocate buffer that has space for both */
586 combined_cmd = kzalloc(total_bytes, GFP_KERNEL); 586 combined_cmd = kzalloc(total_bytes, GFP_KERNEL);
587 if (!combined_cmd) { 587 if (!combined_cmd) {
588 gk20a_warn(&cde_ctx->pdev->dev, 588 gk20a_warn(cde_ctx->dev,
589 "cde: could not allocate memory for gpfifo entries"); 589 "cde: could not allocate memory for gpfifo entries");
590 return -ENOMEM; 590 return -ENOMEM;
591 } 591 }
@@ -618,7 +618,7 @@ static int gk20a_init_cde_img(struct gk20a_cde_ctx *cde_ctx,
618 618
619 min_size += 2 * sizeof(u32); 619 min_size += 2 * sizeof(u32);
620 if (img->size < min_size) { 620 if (img->size < min_size) {
621 gk20a_warn(&cde_ctx->pdev->dev, "cde: invalid image header"); 621 gk20a_warn(cde_ctx->dev, "cde: invalid image header");
622 return -EINVAL; 622 return -EINVAL;
623 } 623 }
624 624
@@ -627,7 +627,7 @@ static int gk20a_init_cde_img(struct gk20a_cde_ctx *cde_ctx,
627 627
628 min_size += num_of_elems * sizeof(*elem); 628 min_size += num_of_elems * sizeof(*elem);
629 if (img->size < min_size) { 629 if (img->size < min_size) {
630 gk20a_warn(&cde_ctx->pdev->dev, "cde: bad image"); 630 gk20a_warn(cde_ctx->dev, "cde: bad image");
631 return -EINVAL; 631 return -EINVAL;
632 } 632 }
633 633
@@ -664,7 +664,7 @@ static int gk20a_init_cde_img(struct gk20a_cde_ctx *cde_ctx,
664 MAX_CDE_ARRAY_ENTRIES*sizeof(u32)); 664 MAX_CDE_ARRAY_ENTRIES*sizeof(u32));
665 break; 665 break;
666 default: 666 default:
667 gk20a_warn(&cde_ctx->pdev->dev, "cde: unknown header element"); 667 gk20a_warn(cde_ctx->dev, "cde: unknown header element");
668 err = -EINVAL; 668 err = -EINVAL;
669 } 669 }
670 670
@@ -675,13 +675,13 @@ static int gk20a_init_cde_img(struct gk20a_cde_ctx *cde_ctx,
675 } 675 }
676 676
677 if (!cde_ctx->init_convert_cmd || !cde_ctx->init_cmd_num_entries) { 677 if (!cde_ctx->init_convert_cmd || !cde_ctx->init_cmd_num_entries) {
678 gk20a_warn(&cde_ctx->pdev->dev, "cde: convert command not defined"); 678 gk20a_warn(cde_ctx->dev, "cde: convert command not defined");
679 err = -EINVAL; 679 err = -EINVAL;
680 goto deinit_image; 680 goto deinit_image;
681 } 681 }
682 682
683 if (!cde_ctx->convert_cmd || !cde_ctx->convert_cmd_num_entries) { 683 if (!cde_ctx->convert_cmd || !cde_ctx->convert_cmd_num_entries) {
684 gk20a_warn(&cde_ctx->pdev->dev, "cde: convert command not defined"); 684 gk20a_warn(cde_ctx->dev, "cde: convert command not defined");
685 err = -EINVAL; 685 err = -EINVAL;
686 goto deinit_image; 686 goto deinit_image;
687 } 687 }
@@ -714,12 +714,12 @@ static int gk20a_cde_execute_buffer(struct gk20a_cde_ctx *cde_ctx,
714 gpfifo = cde_ctx->convert_cmd; 714 gpfifo = cde_ctx->convert_cmd;
715 num_entries = cde_ctx->convert_cmd_num_entries; 715 num_entries = cde_ctx->convert_cmd_num_entries;
716 } else { 716 } else {
717 gk20a_warn(&cde_ctx->pdev->dev, "cde: unknown buffer"); 717 gk20a_warn(cde_ctx->dev, "cde: unknown buffer");
718 return -EINVAL; 718 return -EINVAL;
719 } 719 }
720 720
721 if (gpfifo == NULL || num_entries == 0) { 721 if (gpfifo == NULL || num_entries == 0) {
722 gk20a_warn(&cde_ctx->pdev->dev, "cde: buffer not available"); 722 gk20a_warn(cde_ctx->dev, "cde: buffer not available");
723 return -ENOSYS; 723 return -ENOSYS;
724 } 724 }
725 725
@@ -757,7 +757,7 @@ __releases(&cde_app->mutex)
757 struct gk20a_cde_ctx *cde_ctx = container_of(delay_work, 757 struct gk20a_cde_ctx *cde_ctx = container_of(delay_work,
758 struct gk20a_cde_ctx, ctx_deleter_work); 758 struct gk20a_cde_ctx, ctx_deleter_work);
759 struct gk20a_cde_app *cde_app = &cde_ctx->g->cde_app; 759 struct gk20a_cde_app *cde_app = &cde_ctx->g->cde_app;
760 struct platform_device *pdev = cde_ctx->pdev; 760 struct device *dev = cde_ctx->dev;
761 int err; 761 int err;
762 762
763 /* someone has just taken it? engine deletion started? */ 763 /* someone has just taken it? engine deletion started? */
@@ -767,11 +767,11 @@ __releases(&cde_app->mutex)
767 gk20a_dbg(gpu_dbg_fn | gpu_dbg_cde_ctx, 767 gk20a_dbg(gpu_dbg_fn | gpu_dbg_cde_ctx,
768 "cde: attempting to delete temporary %p", cde_ctx); 768 "cde: attempting to delete temporary %p", cde_ctx);
769 769
770 err = gk20a_busy(pdev); 770 err = gk20a_busy(dev);
771 if (err) { 771 if (err) {
772 /* this context would find new use anyway later, so not freeing 772 /* this context would find new use anyway later, so not freeing
773 * here does not leak anything */ 773 * here does not leak anything */
774 gk20a_warn(&pdev->dev, "cde: cannot set gk20a on, postponing" 774 gk20a_warn(dev, "cde: cannot set gk20a on, postponing"
775 " temp ctx deletion"); 775 " temp ctx deletion");
776 return; 776 return;
777 } 777 }
@@ -795,7 +795,7 @@ __releases(&cde_app->mutex)
795 795
796out: 796out:
797 mutex_unlock(&cde_app->mutex); 797 mutex_unlock(&cde_app->mutex);
798 gk20a_idle(pdev); 798 gk20a_idle(dev);
799} 799}
800 800
801static struct gk20a_cde_ctx *gk20a_cde_do_get_context(struct gk20a *g) 801static struct gk20a_cde_ctx *gk20a_cde_do_get_context(struct gk20a *g)
@@ -839,7 +839,7 @@ __must_hold(&cde_app->mutex)
839 839
840 cde_ctx = gk20a_cde_allocate_context(g); 840 cde_ctx = gk20a_cde_allocate_context(g);
841 if (IS_ERR(cde_ctx)) { 841 if (IS_ERR(cde_ctx)) {
842 gk20a_warn(&g->dev->dev, "cde: cannot allocate context: %ld", 842 gk20a_warn(g->dev, "cde: cannot allocate context: %ld",
843 PTR_ERR(cde_ctx)); 843 PTR_ERR(cde_ctx));
844 return cde_ctx; 844 return cde_ctx;
845 } 845 }
@@ -888,7 +888,7 @@ static struct gk20a_cde_ctx *gk20a_cde_allocate_context(struct gk20a *g)
888 return ERR_PTR(-ENOMEM); 888 return ERR_PTR(-ENOMEM);
889 889
890 cde_ctx->g = g; 890 cde_ctx->g = g;
891 cde_ctx->pdev = g->dev; 891 cde_ctx->dev = g->dev;
892 892
893 ret = gk20a_cde_load(cde_ctx); 893 ret = gk20a_cde_load(cde_ctx);
894 if (ret) { 894 if (ret) {
@@ -951,7 +951,7 @@ __releases(&cde_app->mutex)
951 /* First, map the buffer to local va */ 951 /* First, map the buffer to local va */
952 952
953 /* ensure that the compbits buffer has drvdata */ 953 /* ensure that the compbits buffer has drvdata */
954 err = gk20a_dmabuf_alloc_drvdata(compbits_scatter_buf, &g->dev->dev); 954 err = gk20a_dmabuf_alloc_drvdata(compbits_scatter_buf, g->dev);
955 if (err) 955 if (err)
956 goto exit_unlock; 956 goto exit_unlock;
957 957
@@ -1007,7 +1007,7 @@ __releases(&cde_app->mutex)
1007 1007
1008 surface = dma_buf_vmap(compbits_scatter_buf); 1008 surface = dma_buf_vmap(compbits_scatter_buf);
1009 if (IS_ERR(surface)) { 1009 if (IS_ERR(surface)) {
1010 gk20a_warn(&g->dev->dev, 1010 gk20a_warn(g->dev,
1011 "dma_buf_vmap failed"); 1011 "dma_buf_vmap failed");
1012 err = -EINVAL; 1012 err = -EINVAL;
1013 goto exit_unlock; 1013 goto exit_unlock;
@@ -1017,9 +1017,9 @@ __releases(&cde_app->mutex)
1017 1017
1018 gk20a_dbg(gpu_dbg_cde, "surface=0x%p scatterBuffer=0x%p", 1018 gk20a_dbg(gpu_dbg_cde, "surface=0x%p scatterBuffer=0x%p",
1019 surface, scatter_buffer); 1019 surface, scatter_buffer);
1020 sgt = gk20a_mm_pin(&g->dev->dev, compbits_scatter_buf); 1020 sgt = gk20a_mm_pin(g->dev, compbits_scatter_buf);
1021 if (IS_ERR(sgt)) { 1021 if (IS_ERR(sgt)) {
1022 gk20a_warn(&g->dev->dev, 1022 gk20a_warn(g->dev,
1023 "mm_pin failed"); 1023 "mm_pin failed");
1024 err = -EINVAL; 1024 err = -EINVAL;
1025 goto exit_unlock; 1025 goto exit_unlock;
@@ -1029,7 +1029,7 @@ __releases(&cde_app->mutex)
1029 scatterbuffer_size); 1029 scatterbuffer_size);
1030 WARN_ON(err); 1030 WARN_ON(err);
1031 1031
1032 gk20a_mm_unpin(&g->dev->dev, compbits_scatter_buf, 1032 gk20a_mm_unpin(g->dev, compbits_scatter_buf,
1033 sgt); 1033 sgt);
1034 if (err) 1034 if (err)
1035 goto exit_unlock; 1035 goto exit_unlock;
@@ -1041,7 +1041,7 @@ __releases(&cde_app->mutex)
1041 } 1041 }
1042 1042
1043 /* store source buffer compression tags */ 1043 /* store source buffer compression tags */
1044 gk20a_get_comptags(&g->dev->dev, compbits_scatter_buf, &comptags); 1044 gk20a_get_comptags(g->dev, compbits_scatter_buf, &comptags);
1045 cde_ctx->surf_param_offset = comptags.offset; 1045 cde_ctx->surf_param_offset = comptags.offset;
1046 cde_ctx->surf_param_lines = comptags.lines; 1046 cde_ctx->surf_param_lines = comptags.lines;
1047 1047
@@ -1067,7 +1067,7 @@ __releases(&cde_app->mutex)
1067 int id = param->id - NUM_RESERVED_PARAMS; 1067 int id = param->id - NUM_RESERVED_PARAMS;
1068 1068
1069 if (id < 0 || id >= MAX_CDE_USER_PARAMS) { 1069 if (id < 0 || id >= MAX_CDE_USER_PARAMS) {
1070 gk20a_warn(&cde_ctx->pdev->dev, "cde: unknown user parameter"); 1070 gk20a_warn(cde_ctx->dev, "cde: unknown user parameter");
1071 err = -EINVAL; 1071 err = -EINVAL;
1072 goto exit_unlock; 1072 goto exit_unlock;
1073 } 1073 }
@@ -1077,7 +1077,7 @@ __releases(&cde_app->mutex)
1077 /* patch data */ 1077 /* patch data */
1078 err = gk20a_cde_patch_params(cde_ctx); 1078 err = gk20a_cde_patch_params(cde_ctx);
1079 if (err) { 1079 if (err) {
1080 gk20a_warn(&cde_ctx->pdev->dev, "cde: failed to patch parameters"); 1080 gk20a_warn(cde_ctx->dev, "cde: failed to patch parameters");
1081 goto exit_unlock; 1081 goto exit_unlock;
1082 } 1082 }
1083 1083
@@ -1140,19 +1140,19 @@ __releases(&cde_app->mutex)
1140 1140
1141 if (ch->has_timedout) { 1141 if (ch->has_timedout) {
1142 if (cde_ctx->is_temporary) { 1142 if (cde_ctx->is_temporary) {
1143 gk20a_warn(&cde_ctx->pdev->dev, 1143 gk20a_warn(cde_ctx->dev,
1144 "cde: channel had timed out" 1144 "cde: channel had timed out"
1145 " (temporary channel)"); 1145 " (temporary channel)");
1146 /* going to be deleted anyway */ 1146 /* going to be deleted anyway */
1147 } else { 1147 } else {
1148 gk20a_warn(&cde_ctx->pdev->dev, 1148 gk20a_warn(cde_ctx->dev,
1149 "cde: channel had timed out" 1149 "cde: channel had timed out"
1150 ", reloading"); 1150 ", reloading");
1151 /* mark it to be deleted, replace with a new one */ 1151 /* mark it to be deleted, replace with a new one */
1152 mutex_lock(&cde_app->mutex); 1152 mutex_lock(&cde_app->mutex);
1153 cde_ctx->is_temporary = true; 1153 cde_ctx->is_temporary = true;
1154 if (gk20a_cde_create_context(g)) { 1154 if (gk20a_cde_create_context(g)) {
1155 gk20a_err(&cde_ctx->pdev->dev, 1155 gk20a_err(cde_ctx->dev,
1156 "cde: can't replace context"); 1156 "cde: can't replace context");
1157 } 1157 }
1158 mutex_unlock(&cde_app->mutex); 1158 mutex_unlock(&cde_app->mutex);
@@ -1181,14 +1181,14 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
1181 1181
1182 img = gk20a_request_firmware(g, "gpu2cde.bin"); 1182 img = gk20a_request_firmware(g, "gpu2cde.bin");
1183 if (!img) { 1183 if (!img) {
1184 dev_err(&cde_ctx->pdev->dev, "cde: could not fetch the firmware"); 1184 dev_err(cde_ctx->dev, "cde: could not fetch the firmware");
1185 return -ENOSYS; 1185 return -ENOSYS;
1186 } 1186 }
1187 1187
1188 ch = gk20a_open_new_channel_with_cb(g, gk20a_cde_finished_ctx_cb, 1188 ch = gk20a_open_new_channel_with_cb(g, gk20a_cde_finished_ctx_cb,
1189 cde_ctx); 1189 cde_ctx);
1190 if (!ch) { 1190 if (!ch) {
1191 gk20a_warn(&cde_ctx->pdev->dev, "cde: gk20a channel not available"); 1191 gk20a_warn(cde_ctx->dev, "cde: gk20a channel not available");
1192 err = -ENOMEM; 1192 err = -ENOMEM;
1193 goto err_get_gk20a_channel; 1193 goto err_get_gk20a_channel;
1194 } 1194 }
@@ -1198,7 +1198,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
1198 ch->vm = &g->mm.cde.vm; 1198 ch->vm = &g->mm.cde.vm;
1199 err = channel_gk20a_commit_va(ch); 1199 err = channel_gk20a_commit_va(ch);
1200 if (err) { 1200 if (err) {
1201 gk20a_warn(&cde_ctx->pdev->dev, "cde: could not bind vm"); 1201 gk20a_warn(cde_ctx->dev, "cde: could not bind vm");
1202 goto err_commit_va; 1202 goto err_commit_va;
1203 } 1203 }
1204 1204
@@ -1206,7 +1206,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
1206 err = gk20a_alloc_channel_gpfifo(ch, 1206 err = gk20a_alloc_channel_gpfifo(ch,
1207 &(struct nvgpu_alloc_gpfifo_args){1024, 0}); 1207 &(struct nvgpu_alloc_gpfifo_args){1024, 0});
1208 if (err) { 1208 if (err) {
1209 gk20a_warn(&cde_ctx->pdev->dev, "cde: unable to allocate gpfifo"); 1209 gk20a_warn(cde_ctx->dev, "cde: unable to allocate gpfifo");
1210 goto err_alloc_gpfifo; 1210 goto err_alloc_gpfifo;
1211 } 1211 }
1212 1212
@@ -1218,7 +1218,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
1218 false); 1218 false);
1219 1219
1220 if (!vaddr) { 1220 if (!vaddr) {
1221 gk20a_warn(&cde_ctx->pdev->dev, "cde: cannot map compression bit backing store"); 1221 gk20a_warn(cde_ctx->dev, "cde: cannot map compression bit backing store");
1222 err = -ENOMEM; 1222 err = -ENOMEM;
1223 goto err_map_backingstore; 1223 goto err_map_backingstore;
1224 } 1224 }
@@ -1231,7 +1231,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
1231 /* initialise the firmware */ 1231 /* initialise the firmware */
1232 err = gk20a_init_cde_img(cde_ctx, img); 1232 err = gk20a_init_cde_img(cde_ctx, img);
1233 if (err) { 1233 if (err) {
1234 gk20a_warn(&cde_ctx->pdev->dev, "cde: image initialisation failed"); 1234 gk20a_warn(cde_ctx->dev, "cde: image initialisation failed");
1235 goto err_init_cde_img; 1235 goto err_init_cde_img;
1236 } 1236 }
1237 1237
@@ -1248,7 +1248,7 @@ err_alloc_gpfifo:
1248err_commit_va: 1248err_commit_va:
1249err_get_gk20a_channel: 1249err_get_gk20a_channel:
1250 release_firmware(img); 1250 release_firmware(img);
1251 dev_err(&cde_ctx->pdev->dev, "cde: couldn't initialise buffer converter: %d", 1251 dev_err(cde_ctx->dev, "cde: couldn't initialise buffer converter: %d",
1252 err); 1252 err);
1253 return err; 1253 return err;
1254} 1254}
@@ -1386,17 +1386,17 @@ static int gk20a_buffer_convert_gpu_to_cde_v1(
1386 g->ops.cde.get_program_numbers(g, block_height_log2, 1386 g->ops.cde.get_program_numbers(g, block_height_log2,
1387 &hprog, &vprog); 1387 &hprog, &vprog);
1388 else { 1388 else {
1389 gk20a_warn(&g->dev->dev, "cde: chip not supported"); 1389 gk20a_warn(g->dev, "cde: chip not supported");
1390 return -ENOSYS; 1390 return -ENOSYS;
1391 } 1391 }
1392 1392
1393 if (hprog < 0 || vprog < 0) { 1393 if (hprog < 0 || vprog < 0) {
1394 gk20a_warn(&g->dev->dev, "cde: could not determine programs"); 1394 gk20a_warn(g->dev, "cde: could not determine programs");
1395 return -ENOSYS; 1395 return -ENOSYS;
1396 } 1396 }
1397 1397
1398 if (xtiles > 8192 / 8 || ytiles > 8192 / 8) 1398 if (xtiles > 8192 / 8 || ytiles > 8192 / 8)
1399 gk20a_warn(&g->dev->dev, "cde: surface is exceptionally large (xtiles=%d, ytiles=%d)", 1399 gk20a_warn(g->dev, "cde: surface is exceptionally large (xtiles=%d, ytiles=%d)",
1400 xtiles, ytiles); 1400 xtiles, ytiles);
1401 1401
1402 gk20a_dbg(gpu_dbg_cde, "w=%d, h=%d, bh_log2=%d, compbits_hoffset=0x%llx, compbits_voffset=0x%llx, scatterbuffer_offset=0x%llx", 1402 gk20a_dbg(gpu_dbg_cde, "w=%d, h=%d, bh_log2=%d, compbits_hoffset=0x%llx, compbits_voffset=0x%llx, scatterbuffer_offset=0x%llx",
@@ -1645,9 +1645,9 @@ static const struct file_operations gk20a_cde_reload_fops = {
1645 .write = gk20a_cde_reload_write, 1645 .write = gk20a_cde_reload_write,
1646}; 1646};
1647 1647
1648void gk20a_cde_debugfs_init(struct platform_device *dev) 1648void gk20a_cde_debugfs_init(struct device *dev)
1649{ 1649{
1650 struct gk20a_platform *platform = platform_get_drvdata(dev); 1650 struct gk20a_platform *platform = dev_get_drvdata(dev);
1651 struct gk20a *g = get_gk20a(dev); 1651 struct gk20a *g = get_gk20a(dev);
1652 1652
1653 debugfs_create_u32("cde_parameter", S_IWUSR | S_IRUGO, 1653 debugfs_create_u32("cde_parameter", S_IWUSR | S_IRUGO,
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.h b/drivers/gpu/nvgpu/gk20a/cde_gk20a.h
index fc5736ad..16d6b4ef 100644
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A color decompression engine support 2 * GK20A color decompression engine support
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -215,7 +215,7 @@ struct gk20a_cde_param {
215 215
216struct gk20a_cde_ctx { 216struct gk20a_cde_ctx {
217 struct gk20a *g; 217 struct gk20a *g;
218 struct platform_device *pdev; 218 struct device *dev;
219 219
220 /* channel related data */ 220 /* channel related data */
221 struct channel_gk20a *ch; 221 struct channel_gk20a *ch;
@@ -288,7 +288,7 @@ int gk20a_cde_convert(struct gk20a *g,
288 struct nvgpu_fence *fence, 288 struct nvgpu_fence *fence,
289 u32 __flags, struct gk20a_cde_param *params, 289 u32 __flags, struct gk20a_cde_param *params,
290 int num_params, struct gk20a_fence **fence_out); 290 int num_params, struct gk20a_fence **fence_out);
291void gk20a_cde_debugfs_init(struct platform_device *dev); 291void gk20a_cde_debugfs_init(struct device *dev);
292 292
293int gk20a_prepare_compressible_read( 293int gk20a_prepare_compressible_read(
294 struct gk20a *g, u32 buffer_fd, u32 request, u64 offset, 294 struct gk20a *g, u32 buffer_fd, u32 request, u64 offset,
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 58175141..61211239 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -74,7 +74,9 @@ static void gk20a_channel_clean_up_jobs(struct work_struct *work);
74static struct channel_gk20a *allocate_channel(struct fifo_gk20a *f) 74static struct channel_gk20a *allocate_channel(struct fifo_gk20a *f)
75{ 75{
76 struct channel_gk20a *ch = NULL; 76 struct channel_gk20a *ch = NULL;
77 struct gk20a_platform *platform = gk20a_get_platform(f->g->dev); 77 struct gk20a_platform *platform;
78
79 platform = gk20a_get_platform(f->g->dev);
78 80
79 mutex_lock(&f->free_chs_mutex); 81 mutex_lock(&f->free_chs_mutex);
80 if (!list_empty(&f->free_chs)) { 82 if (!list_empty(&f->free_chs)) {
@@ -156,7 +158,7 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g,
156 int timeslice_period, 158 int timeslice_period,
157 int *__timeslice_timeout, int *__timeslice_scale) 159 int *__timeslice_timeout, int *__timeslice_scale)
158{ 160{
159 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 161 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
160 int value = scale_ptimer(timeslice_period, 162 int value = scale_ptimer(timeslice_period,
161 ptimer_scalingfactor10x(platform->ptimer_src_freq)); 163 ptimer_scalingfactor10x(platform->ptimer_src_freq));
162 int shift = 0; 164 int shift = 0;
@@ -1068,7 +1070,7 @@ int gk20a_channel_release(struct inode *inode, struct file *filp)
1068 if (!ch) 1070 if (!ch)
1069 return 0; 1071 return 0;
1070 1072
1071 trace_gk20a_channel_release(dev_name(&g->dev->dev)); 1073 trace_gk20a_channel_release(dev_name(g->dev));
1072 1074
1073 err = gk20a_busy(g->dev); 1075 err = gk20a_busy(g->dev);
1074 if (err) { 1076 if (err) {
@@ -1189,7 +1191,9 @@ static int __gk20a_channel_open(struct gk20a *g, struct file *filp)
1189 int err; 1191 int err;
1190 struct channel_gk20a *ch; 1192 struct channel_gk20a *ch;
1191 1193
1192 trace_gk20a_channel_open(dev_name(&g->dev->dev)); 1194 gk20a_dbg_fn("");
1195
1196 trace_gk20a_channel_open(dev_name(g->dev));
1193 1197
1194 err = gk20a_busy(g->dev); 1198 err = gk20a_busy(g->dev);
1195 if (err) { 1199 if (err) {
@@ -1235,7 +1239,7 @@ int gk20a_channel_open_ioctl(struct gk20a *g,
1235 fd = err; 1239 fd = err;
1236 1240
1237 name = kasprintf(GFP_KERNEL, "nvhost-%s-fd%d", 1241 name = kasprintf(GFP_KERNEL, "nvhost-%s-fd%d",
1238 dev_name(&g->dev->dev), fd); 1242 dev_name(g->dev), fd);
1239 if (!name) { 1243 if (!name) {
1240 err = -ENOMEM; 1244 err = -ENOMEM;
1241 goto clean_up; 1245 goto clean_up;
@@ -1562,7 +1566,7 @@ static void trace_write_pushbuffer(struct channel_gk20a *c,
1562 */ 1566 */
1563 for (i = 0; i < words; i += 128U) { 1567 for (i = 0; i < words; i += 128U) {
1564 trace_gk20a_push_cmdbuf( 1568 trace_gk20a_push_cmdbuf(
1565 c->g->dev->name, 1569 dev_name(c->g->dev),
1566 0, 1570 0,
1567 min(words - i, 128U), 1571 min(words - i, 128U),
1568 offset + i * sizeof(u32), 1572 offset + i * sizeof(u32),
@@ -2051,7 +2055,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
2051 return err; 2055 return err;
2052 } 2056 }
2053 2057
2054 trace_gk20a_channel_submit_gpfifo(c->g->dev->name, 2058 trace_gk20a_channel_submit_gpfifo(dev_name(c->g->dev),
2055 c->hw_chid, 2059 c->hw_chid,
2056 num_entries, 2060 num_entries,
2057 flags, 2061 flags,
@@ -2069,11 +2073,11 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
2069 if (locked_path) 2073 if (locked_path)
2070 mutex_unlock(&c->ioctl_lock); 2074 mutex_unlock(&c->ioctl_lock);
2071 2075
2072 trace_gk20a_gpfifo_submit_wait_for_space(c->g->dev->name); 2076 trace_gk20a_gpfifo_submit_wait_for_space(dev_name(c->g->dev));
2073 err = wait_event_interruptible(c->submit_wq, 2077 err = wait_event_interruptible(c->submit_wq,
2074 get_gp_free_count(c) >= num_entries + extra_entries || 2078 get_gp_free_count(c) >= num_entries + extra_entries ||
2075 c->has_timedout); 2079 c->has_timedout);
2076 trace_gk20a_gpfifo_submit_wait_for_space_done(c->g->dev->name); 2080 trace_gk20a_gpfifo_submit_wait_for_space_done(dev_name(c->g->dev));
2077 2081
2078 if (locked_path) 2082 if (locked_path)
2079 mutex_lock(&c->ioctl_lock); 2083 mutex_lock(&c->ioctl_lock);
@@ -2156,7 +2160,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
2156 gpfifo_mem[c->gpfifo.put].entry0 = u64_lo32(wait_cmd->gva); 2160 gpfifo_mem[c->gpfifo.put].entry0 = u64_lo32(wait_cmd->gva);
2157 gpfifo_mem[c->gpfifo.put].entry1 = u64_hi32(wait_cmd->gva) | 2161 gpfifo_mem[c->gpfifo.put].entry1 = u64_hi32(wait_cmd->gva) |
2158 pbdma_gp_entry1_length_f(wait_cmd->size); 2162 pbdma_gp_entry1_length_f(wait_cmd->size);
2159 trace_gk20a_push_cmdbuf(c->g->dev->name, 2163 trace_gk20a_push_cmdbuf(dev_name(c->g->dev),
2160 0, wait_cmd->size, 0, wait_cmd->ptr); 2164 0, wait_cmd->size, 0, wait_cmd->ptr);
2161 2165
2162 c->gpfifo.put = (c->gpfifo.put + 1) & 2166 c->gpfifo.put = (c->gpfifo.put + 1) &
@@ -2244,7 +2248,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
2244 gpfifo_mem[c->gpfifo.put].entry0 = u64_lo32(incr_cmd->gva); 2248 gpfifo_mem[c->gpfifo.put].entry0 = u64_lo32(incr_cmd->gva);
2245 gpfifo_mem[c->gpfifo.put].entry1 = u64_hi32(incr_cmd->gva) | 2249 gpfifo_mem[c->gpfifo.put].entry1 = u64_hi32(incr_cmd->gva) |
2246 pbdma_gp_entry1_length_f(incr_cmd->size); 2250 pbdma_gp_entry1_length_f(incr_cmd->size);
2247 trace_gk20a_push_cmdbuf(c->g->dev->name, 2251 trace_gk20a_push_cmdbuf(dev_name(c->g->dev),
2248 0, incr_cmd->size, 0, incr_cmd->ptr); 2252 0, incr_cmd->size, 0, incr_cmd->ptr);
2249 2253
2250 c->gpfifo.put = (c->gpfifo.put + 1) & 2254 c->gpfifo.put = (c->gpfifo.put + 1) &
@@ -2273,7 +2277,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
2273 2277
2274 mutex_unlock(&c->submit_lock); 2278 mutex_unlock(&c->submit_lock);
2275 2279
2276 trace_gk20a_channel_submitted_gpfifo(c->g->dev->name, 2280 trace_gk20a_channel_submitted_gpfifo(dev_name(c->g->dev),
2277 c->hw_chid, 2281 c->hw_chid,
2278 num_entries, 2282 num_entries,
2279 flags, 2283 flags,
@@ -2357,7 +2361,7 @@ static int gk20a_channel_wait_semaphore(struct channel_gk20a *ch,
2357 ulong id, u32 offset, 2361 ulong id, u32 offset,
2358 u32 payload, long timeout) 2362 u32 payload, long timeout)
2359{ 2363{
2360 struct platform_device *pdev = ch->g->dev; 2364 struct device *dev = ch->g->dev;
2361 struct dma_buf *dmabuf; 2365 struct dma_buf *dmabuf;
2362 void *data; 2366 void *data;
2363 u32 *semaphore; 2367 u32 *semaphore;
@@ -2370,14 +2374,13 @@ static int gk20a_channel_wait_semaphore(struct channel_gk20a *ch,
2370 2374
2371 dmabuf = dma_buf_get(id); 2375 dmabuf = dma_buf_get(id);
2372 if (IS_ERR(dmabuf)) { 2376 if (IS_ERR(dmabuf)) {
2373 gk20a_err(&pdev->dev, "invalid notifier nvmap handle 0x%lx", 2377 gk20a_err(dev, "invalid notifier nvmap handle 0x%lx", id);
2374 id);
2375 return -EINVAL; 2378 return -EINVAL;
2376 } 2379 }
2377 2380
2378 data = dma_buf_kmap(dmabuf, offset >> PAGE_SHIFT); 2381 data = dma_buf_kmap(dmabuf, offset >> PAGE_SHIFT);
2379 if (!data) { 2382 if (!data) {
2380 gk20a_err(&pdev->dev, "failed to map notifier memory"); 2383 gk20a_err(dev, "failed to map notifier memory");
2381 ret = -EINVAL; 2384 ret = -EINVAL;
2382 goto cleanup_put; 2385 goto cleanup_put;
2383 } 2386 }
@@ -2917,7 +2920,7 @@ long gk20a_channel_ioctl(struct file *filp,
2917 unsigned int cmd, unsigned long arg) 2920 unsigned int cmd, unsigned long arg)
2918{ 2921{
2919 struct channel_gk20a *ch = filp->private_data; 2922 struct channel_gk20a *ch = filp->private_data;
2920 struct platform_device *dev = ch->g->dev; 2923 struct device *dev = ch->g->dev;
2921 u8 buf[NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE]; 2924 u8 buf[NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE];
2922 int err = 0; 2925 int err = 0;
2923 2926
@@ -2956,7 +2959,7 @@ long gk20a_channel_ioctl(struct file *filp,
2956 case NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX: 2959 case NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX:
2957 err = gk20a_busy(dev); 2960 err = gk20a_busy(dev);
2958 if (err) { 2961 if (err) {
2959 dev_err(&dev->dev, 2962 dev_err(dev,
2960 "%s: failed to host gk20a for ioctl cmd: 0x%x", 2963 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2961 __func__, cmd); 2964 __func__, cmd);
2962 break; 2965 break;
@@ -2968,7 +2971,7 @@ long gk20a_channel_ioctl(struct file *filp,
2968 case NVGPU_IOCTL_CHANNEL_FREE_OBJ_CTX: 2971 case NVGPU_IOCTL_CHANNEL_FREE_OBJ_CTX:
2969 err = gk20a_busy(dev); 2972 err = gk20a_busy(dev);
2970 if (err) { 2973 if (err) {
2971 dev_err(&dev->dev, 2974 dev_err(dev,
2972 "%s: failed to host gk20a for ioctl cmd: 0x%x", 2975 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2973 __func__, cmd); 2976 __func__, cmd);
2974 break; 2977 break;
@@ -2980,7 +2983,7 @@ long gk20a_channel_ioctl(struct file *filp,
2980 case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO: 2983 case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO:
2981 err = gk20a_busy(dev); 2984 err = gk20a_busy(dev);
2982 if (err) { 2985 if (err) {
2983 dev_err(&dev->dev, 2986 dev_err(dev,
2984 "%s: failed to host gk20a for ioctl cmd: 0x%x", 2987 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2985 __func__, cmd); 2988 __func__, cmd);
2986 break; 2989 break;
@@ -2996,7 +2999,7 @@ long gk20a_channel_ioctl(struct file *filp,
2996 case NVGPU_IOCTL_CHANNEL_WAIT: 2999 case NVGPU_IOCTL_CHANNEL_WAIT:
2997 err = gk20a_busy(dev); 3000 err = gk20a_busy(dev);
2998 if (err) { 3001 if (err) {
2999 dev_err(&dev->dev, 3002 dev_err(dev,
3000 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3003 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3001 __func__, cmd); 3004 __func__, cmd);
3002 break; 3005 break;
@@ -3016,7 +3019,7 @@ long gk20a_channel_ioctl(struct file *filp,
3016 case NVGPU_IOCTL_CHANNEL_ZCULL_BIND: 3019 case NVGPU_IOCTL_CHANNEL_ZCULL_BIND:
3017 err = gk20a_busy(dev); 3020 err = gk20a_busy(dev);
3018 if (err) { 3021 if (err) {
3019 dev_err(&dev->dev, 3022 dev_err(dev,
3020 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3023 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3021 __func__, cmd); 3024 __func__, cmd);
3022 break; 3025 break;
@@ -3028,7 +3031,7 @@ long gk20a_channel_ioctl(struct file *filp,
3028 case NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER: 3031 case NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER:
3029 err = gk20a_busy(dev); 3032 err = gk20a_busy(dev);
3030 if (err) { 3033 if (err) {
3031 dev_err(&dev->dev, 3034 dev_err(dev,
3032 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3035 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3033 __func__, cmd); 3036 __func__, cmd);
3034 break; 3037 break;
@@ -3041,7 +3044,7 @@ long gk20a_channel_ioctl(struct file *filp,
3041 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS: 3044 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS:
3042 err = gk20a_busy(dev); 3045 err = gk20a_busy(dev);
3043 if (err) { 3046 if (err) {
3044 dev_err(&dev->dev, 3047 dev_err(dev,
3045 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3048 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3046 __func__, cmd); 3049 __func__, cmd);
3047 break; 3050 break;
@@ -3080,7 +3083,7 @@ long gk20a_channel_ioctl(struct file *filp,
3080 case NVGPU_IOCTL_CHANNEL_SET_PRIORITY: 3083 case NVGPU_IOCTL_CHANNEL_SET_PRIORITY:
3081 err = gk20a_busy(dev); 3084 err = gk20a_busy(dev);
3082 if (err) { 3085 if (err) {
3083 dev_err(&dev->dev, 3086 dev_err(dev,
3084 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3087 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3085 __func__, cmd); 3088 __func__, cmd);
3086 break; 3089 break;
@@ -3092,7 +3095,7 @@ long gk20a_channel_ioctl(struct file *filp,
3092 case NVGPU_IOCTL_CHANNEL_ENABLE: 3095 case NVGPU_IOCTL_CHANNEL_ENABLE:
3093 err = gk20a_busy(dev); 3096 err = gk20a_busy(dev);
3094 if (err) { 3097 if (err) {
3095 dev_err(&dev->dev, 3098 dev_err(dev,
3096 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3099 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3097 __func__, cmd); 3100 __func__, cmd);
3098 break; 3101 break;
@@ -3106,7 +3109,7 @@ long gk20a_channel_ioctl(struct file *filp,
3106 case NVGPU_IOCTL_CHANNEL_DISABLE: 3109 case NVGPU_IOCTL_CHANNEL_DISABLE:
3107 err = gk20a_busy(dev); 3110 err = gk20a_busy(dev);
3108 if (err) { 3111 if (err) {
3109 dev_err(&dev->dev, 3112 dev_err(dev,
3110 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3113 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3111 __func__, cmd); 3114 __func__, cmd);
3112 break; 3115 break;
@@ -3120,7 +3123,7 @@ long gk20a_channel_ioctl(struct file *filp,
3120 case NVGPU_IOCTL_CHANNEL_PREEMPT: 3123 case NVGPU_IOCTL_CHANNEL_PREEMPT:
3121 err = gk20a_busy(dev); 3124 err = gk20a_busy(dev);
3122 if (err) { 3125 if (err) {
3123 dev_err(&dev->dev, 3126 dev_err(dev,
3124 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3127 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3125 __func__, cmd); 3128 __func__, cmd);
3126 break; 3129 break;
@@ -3131,7 +3134,7 @@ long gk20a_channel_ioctl(struct file *filp,
3131 case NVGPU_IOCTL_CHANNEL_FORCE_RESET: 3134 case NVGPU_IOCTL_CHANNEL_FORCE_RESET:
3132 err = gk20a_busy(dev); 3135 err = gk20a_busy(dev);
3133 if (err) { 3136 if (err) {
3134 dev_err(&dev->dev, 3137 dev_err(dev,
3135 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3138 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3136 __func__, cmd); 3139 __func__, cmd);
3137 break; 3140 break;
@@ -3147,7 +3150,7 @@ long gk20a_channel_ioctl(struct file *filp,
3147 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT: 3150 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT:
3148 err = gk20a_busy(dev); 3151 err = gk20a_busy(dev);
3149 if (err) { 3152 if (err) {
3150 dev_err(&dev->dev, 3153 dev_err(dev,
3151 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3154 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3152 __func__, cmd); 3155 __func__, cmd);
3153 break; 3156 break;
@@ -3164,7 +3167,7 @@ long gk20a_channel_ioctl(struct file *filp,
3164 case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE: 3167 case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE:
3165 err = gk20a_busy(dev); 3168 err = gk20a_busy(dev);
3166 if (err) { 3169 if (err) {
3167 dev_err(&dev->dev, 3170 dev_err(dev,
3168 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3171 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3169 __func__, cmd); 3172 __func__, cmd);
3170 break; 3173 break;
@@ -3176,7 +3179,7 @@ long gk20a_channel_ioctl(struct file *filp,
3176 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: 3179 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
3177 err = gk20a_busy(dev); 3180 err = gk20a_busy(dev);
3178 if (err) { 3181 if (err) {
3179 dev_err(&dev->dev, 3182 dev_err(dev,
3180 "%s: failed to host gk20a for ioctl cmd: 0x%x", 3183 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3181 __func__, cmd); 3184 __func__, cmd);
3182 break; 3185 break;
@@ -3186,7 +3189,7 @@ long gk20a_channel_ioctl(struct file *filp,
3186 gk20a_idle(dev); 3189 gk20a_idle(dev);
3187 break; 3190 break;
3188 default: 3191 default:
3189 dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); 3192 dev_dbg(dev, "unrecognized ioctl cmd: 0x%x", cmd);
3190 err = -ENOTTY; 3193 err = -ENOTTY;
3191 break; 3194 break;
3192 } 3195 }
diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
index cdf36454..30bb6efe 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
@@ -330,13 +330,13 @@ gk20a_channel_syncpt_create(struct channel_gk20a *c)
330 sp->host1x_pdev = c->g->host1x_dev; 330 sp->host1x_pdev = c->g->host1x_dev;
331 331
332 snprintf(syncpt_name, sizeof(syncpt_name), 332 snprintf(syncpt_name, sizeof(syncpt_name),
333 "%s_%d", dev_name(&c->g->dev->dev), c->hw_chid); 333 "%s_%d", dev_name(c->g->dev), c->hw_chid);
334 334
335 sp->id = nvhost_get_syncpt_host_managed(sp->host1x_pdev, 335 sp->id = nvhost_get_syncpt_host_managed(sp->host1x_pdev,
336 c->hw_chid, syncpt_name); 336 c->hw_chid, syncpt_name);
337 if (!sp->id) { 337 if (!sp->id) {
338 kfree(sp); 338 kfree(sp);
339 gk20a_err(&c->g->dev->dev, "failed to get free syncpt"); 339 gk20a_err(c->g->dev, "failed to get free syncpt");
340 return NULL; 340 return NULL;
341 } 341 }
342 342
@@ -387,7 +387,7 @@ static void gk20a_channel_semaphore_launcher(
387 fence, fence->name); 387 fence, fence->name);
388 err = sync_fence_wait(fence, -1); 388 err = sync_fence_wait(fence, -1);
389 if (err < 0) 389 if (err < 0)
390 dev_err(&g->dev->dev, "error waiting pre-fence: %d\n", err); 390 dev_err(g->dev, "error waiting pre-fence: %d\n", err);
391 391
392 gk20a_dbg_info( 392 gk20a_dbg_info(
393 "wait completed (%d) for fence %p '%s', triggering gpu work", 393 "wait completed (%d) for fence %p '%s', triggering gpu work",
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
index e10df6ac..26fd1eaf 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
@@ -1,9 +1,7 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/clk_gk20a.c
3 *
4 * GK20A Clocks 2 * GK20A Clocks
5 * 3 *
6 * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
7 * 5 *
8 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -831,7 +829,7 @@ DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
831static int clk_gk20a_debugfs_init(struct gk20a *g) 829static int clk_gk20a_debugfs_init(struct gk20a *g)
832{ 830{
833 struct dentry *d; 831 struct dentry *d;
834 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 832 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
835 833
836 d = debugfs_create_file( 834 d = debugfs_create_file(
837 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops); 835 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops);
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
index b2ae224f..87f0683f 100644
--- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
@@ -144,7 +144,7 @@ static int gk20a_ctrl_alloc_as(
144 struct gk20a *g, 144 struct gk20a *g,
145 struct nvgpu_alloc_as_args *args) 145 struct nvgpu_alloc_as_args *args)
146{ 146{
147 struct platform_device *dev = g->dev; 147 struct device *dev = g->dev;
148 struct gk20a_as_share *as_share; 148 struct gk20a_as_share *as_share;
149 int err; 149 int err;
150 int fd; 150 int fd;
@@ -157,7 +157,7 @@ static int gk20a_ctrl_alloc_as(
157 fd = err; 157 fd = err;
158 158
159 name = kasprintf(GFP_KERNEL, "nvhost-%s-fd%d", 159 name = kasprintf(GFP_KERNEL, "nvhost-%s-fd%d",
160 dev_name(&dev->dev), fd); 160 dev_name(dev), fd);
161 161
162 file = anon_inode_getfile(name, g->as.cdev.ops, NULL, O_RDWR); 162 file = anon_inode_getfile(name, g->as.cdev.ops, NULL, O_RDWR);
163 kfree(name); 163 kfree(name);
@@ -187,7 +187,7 @@ clean_up:
187static int gk20a_ctrl_open_tsg(struct gk20a *g, 187static int gk20a_ctrl_open_tsg(struct gk20a *g,
188 struct nvgpu_gpu_open_tsg_args *args) 188 struct nvgpu_gpu_open_tsg_args *args)
189{ 189{
190 struct platform_device *dev = g->dev; 190 struct device *dev = g->dev;
191 int err; 191 int err;
192 int fd; 192 int fd;
193 struct file *file; 193 struct file *file;
@@ -199,7 +199,7 @@ static int gk20a_ctrl_open_tsg(struct gk20a *g,
199 fd = err; 199 fd = err;
200 200
201 name = kasprintf(GFP_KERNEL, "nvgpu-%s-tsg%d", 201 name = kasprintf(GFP_KERNEL, "nvgpu-%s-tsg%d",
202 dev_name(&dev->dev), fd); 202 dev_name(dev), fd);
203 203
204 file = anon_inode_getfile(name, g->tsg.cdev.ops, NULL, O_RDWR); 204 file = anon_inode_getfile(name, g->tsg.cdev.ops, NULL, O_RDWR);
205 kfree(name); 205 kfree(name);
@@ -621,7 +621,7 @@ static int nvgpu_gpu_get_cpu_time_correlation_info(
621 621
622long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 622long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
623{ 623{
624 struct platform_device *dev = filp->private_data; 624 struct device *dev = filp->private_data;
625 struct gk20a *g = get_gk20a(dev); 625 struct gk20a *g = get_gk20a(dev);
626 struct nvgpu_gpu_zcull_get_ctx_size_args *get_ctx_size_args; 626 struct nvgpu_gpu_zcull_get_ctx_size_args *get_ctx_size_args;
627 struct nvgpu_gpu_zcull_get_info_args *get_info_args; 627 struct nvgpu_gpu_zcull_get_info_args *get_info_args;
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index d087d89e..321cebb2 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -65,7 +65,6 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode,
65 struct dbg_session_gk20a *dbg_session; 65 struct dbg_session_gk20a *dbg_session;
66 struct gk20a *g; 66 struct gk20a *g;
67 67
68 struct platform_device *pdev;
69 struct device *dev; 68 struct device *dev;
70 69
71 int err; 70 int err;
@@ -76,8 +75,7 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode,
76 else 75 else
77 g = container_of(inode->i_cdev, 76 g = container_of(inode->i_cdev,
78 struct gk20a, prof.cdev); 77 struct gk20a, prof.cdev);
79 pdev = g->dev; 78 dev = g->dev;
80 dev = &pdev->dev;
81 79
82 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "dbg session: %s", dev_name(dev)); 80 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "dbg session: %s", dev_name(dev));
83 81
@@ -86,7 +84,6 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode,
86 return err; 84 return err;
87 85
88 filp->private_data = dbg_session; 86 filp->private_data = dbg_session;
89 dbg_session->pdev = pdev;
90 dbg_session->dev = dev; 87 dbg_session->dev = dev;
91 dbg_session->g = g; 88 dbg_session->g = g;
92 dbg_session->is_profiler = is_profiler; 89 dbg_session->is_profiler = is_profiler;
@@ -95,7 +92,7 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode,
95 /* For vgpu, all power-gating features are currently disabled 92 /* For vgpu, all power-gating features are currently disabled
96 * in the server. Set is_pg_disable to true to reflect this 93 * in the server. Set is_pg_disable to true to reflect this
97 * on the client side. */ 94 * on the client side. */
98 if (gk20a_gpu_is_virtual(pdev)) 95 if (gk20a_gpu_is_virtual(dev))
99 dbg_session->is_pg_disabled = true; 96 dbg_session->is_pg_disabled = true;
100 97
101 INIT_LIST_HEAD(&dbg_session->dbg_s_list_node); 98 INIT_LIST_HEAD(&dbg_session->dbg_s_list_node);
@@ -486,7 +483,7 @@ static int nvgpu_dbg_gpu_ioctl_timeout(struct dbg_session_gk20a *dbg_s,
486 struct nvgpu_dbg_gpu_timeout_args *args) 483 struct nvgpu_dbg_gpu_timeout_args *args)
487{ 484{
488 int err; 485 int err;
489 struct gk20a *g = get_gk20a(dbg_s->pdev); 486 struct gk20a *g = get_gk20a(dbg_s->dev);
490 487
491 gk20a_dbg_fn("powergate mode = %d", args->enable); 488 gk20a_dbg_fn("powergate mode = %d", args->enable);
492 489
@@ -501,7 +498,7 @@ static void nvgpu_dbg_gpu_ioctl_get_timeout(struct dbg_session_gk20a *dbg_s,
501 struct nvgpu_dbg_gpu_timeout_args *args) 498 struct nvgpu_dbg_gpu_timeout_args *args)
502{ 499{
503 int status; 500 int status;
504 struct gk20a *g = get_gk20a(dbg_s->pdev); 501 struct gk20a *g = get_gk20a(dbg_s->dev);
505 502
506 mutex_lock(&g->dbg_sessions_lock); 503 mutex_lock(&g->dbg_sessions_lock);
507 status = g->timeouts_enabled; 504 status = g->timeouts_enabled;
@@ -532,7 +529,7 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
532 unsigned long arg) 529 unsigned long arg)
533{ 530{
534 struct dbg_session_gk20a *dbg_s = filp->private_data; 531 struct dbg_session_gk20a *dbg_s = filp->private_data;
535 struct gk20a *g = get_gk20a(dbg_s->pdev); 532 struct gk20a *g = get_gk20a(dbg_s->dev);
536 u8 buf[NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE]; 533 u8 buf[NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE];
537 int err = 0; 534 int err = 0;
538 535
@@ -672,7 +669,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
672 bool is_pg_disabled = false; 669 bool is_pg_disabled = false;
673 670
674 struct device *dev = dbg_s->dev; 671 struct device *dev = dbg_s->dev;
675 struct gk20a *g = get_gk20a(dbg_s->pdev); 672 struct gk20a *g = get_gk20a(dbg_s->dev);
676 struct nvgpu_dbg_gpu_reg_op *ops; 673 struct nvgpu_dbg_gpu_reg_op *ops;
677 u64 ops_size = sizeof(ops[0]) * args->num_ops; 674 u64 ops_size = sizeof(ops[0]) * args->num_ops;
678 675
@@ -689,7 +686,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
689 } 686 }
690 687
691 /* be sure that ctx info is in place */ 688 /* be sure that ctx info is in place */
692 if (!gk20a_gpu_is_virtual(dbg_s->pdev) && 689 if (!gk20a_gpu_is_virtual(dbg_s->dev) &&
693 !gr_context_info_available(dbg_s, &g->gr)) { 690 !gr_context_info_available(dbg_s, &g->gr)) {
694 gk20a_err(dev, "gr context data not available\n"); 691 gk20a_err(dev, "gr context data not available\n");
695 return -ENODEV; 692 return -ENODEV;
@@ -757,7 +754,7 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
757 __u32 powermode) 754 __u32 powermode)
758{ 755{
759 int err = 0; 756 int err = 0;
760 struct gk20a *g = get_gk20a(dbg_s->pdev); 757 struct gk20a *g = get_gk20a(dbg_s->dev);
761 758
762 /* This function must be called with g->dbg_sessions_lock held */ 759 /* This function must be called with g->dbg_sessions_lock held */
763 760
@@ -786,7 +783,7 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
786 if (err) 783 if (err)
787 return err; 784 return err;
788 785
789 err = gk20a_busy(dbg_s->pdev); 786 err = gk20a_busy(dbg_s->dev);
790 if (err) 787 if (err)
791 return -EPERM; 788 return -EPERM;
792 789
@@ -838,7 +835,7 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
838 gk20a_pmu_enable_elpg(g); 835 gk20a_pmu_enable_elpg(g);
839 836
840 gk20a_dbg(gpu_dbg_gpu_dbg | gpu_dbg_fn, "module idle"); 837 gk20a_dbg(gpu_dbg_gpu_dbg | gpu_dbg_fn, "module idle");
841 gk20a_idle(dbg_s->pdev); 838 gk20a_idle(dbg_s->dev);
842 gk20a_idle(g->dev); 839 gk20a_idle(g->dev);
843 } 840 }
844 841
@@ -862,7 +859,7 @@ static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s,
862 struct nvgpu_dbg_gpu_powergate_args *args) 859 struct nvgpu_dbg_gpu_powergate_args *args)
863{ 860{
864 int err; 861 int err;
865 struct gk20a *g = get_gk20a(dbg_s->pdev); 862 struct gk20a *g = get_gk20a(dbg_s->dev);
866 gk20a_dbg_fn("%s powergate mode = %d", 863 gk20a_dbg_fn("%s powergate mode = %d",
867 dev_name(dbg_s->dev), args->mode); 864 dev_name(dbg_s->dev), args->mode);
868 865
@@ -876,7 +873,7 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
876 struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *args) 873 struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *args)
877{ 874{
878 int err; 875 int err;
879 struct gk20a *g = get_gk20a(dbg_s->pdev); 876 struct gk20a *g = get_gk20a(dbg_s->dev);
880 struct channel_gk20a *ch_gk20a; 877 struct channel_gk20a *ch_gk20a;
881 878
882 gk20a_dbg_fn("%s smpc ctxsw mode = %d", 879 gk20a_dbg_fn("%s smpc ctxsw mode = %d",
@@ -912,7 +909,7 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
912 struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args) 909 struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args)
913{ 910{
914 int err; 911 int err;
915 struct gk20a *g = get_gk20a(dbg_s->pdev); 912 struct gk20a *g = get_gk20a(dbg_s->dev);
916 struct channel_gk20a *ch_gk20a; 913 struct channel_gk20a *ch_gk20a;
917 914
918 gk20a_dbg_fn("%s pm ctxsw mode = %d", 915 gk20a_dbg_fn("%s pm ctxsw mode = %d",
@@ -948,7 +945,7 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
948 struct dbg_session_gk20a *dbg_s, 945 struct dbg_session_gk20a *dbg_s,
949 struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args) 946 struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args)
950{ 947{
951 struct gk20a *g = get_gk20a(dbg_s->pdev); 948 struct gk20a *g = get_gk20a(dbg_s->dev);
952 struct channel_gk20a *ch = dbg_s->ch; 949 struct channel_gk20a *ch = dbg_s->ch;
953 bool ch_is_curr_ctx; 950 bool ch_is_curr_ctx;
954 int err = 0, action = args->mode; 951 int err = 0, action = args->mode;
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
index a2e075a6..0ff6cfb3 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Tegra GK20A GPU Debugger Driver 2 * Tegra GK20A GPU Debugger Driver
3 * 3 *
4 * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -66,7 +66,6 @@ struct dbg_session_gk20a {
66 66
67 /* gpu module vagaries */ 67 /* gpu module vagaries */
68 struct device *dev; 68 struct device *dev;
69 struct platform_device *pdev;
70 struct gk20a *g; 69 struct gk20a *g;
71 70
72 /* bound channel, if any */ 71 /* bound channel, if any */
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index 67434e7f..369fbe29 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * drivers/video/tegra/host/t20/debug_gk20a.c 2 * drivers/video/tegra/host/t20/debug_gk20a.c
3 * 3 *
4 * Copyright (C) 2011-2015 NVIDIA Corporation. All rights reserved. 4 * Copyright (C) 2011-2016 NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -32,7 +32,7 @@
32#include "hw_pbdma_gk20a.h" 32#include "hw_pbdma_gk20a.h"
33 33
34unsigned int gk20a_debug_trace_cmdbuf; 34unsigned int gk20a_debug_trace_cmdbuf;
35static struct platform_device *gk20a_device; 35static struct device *gk20a_device;
36 36
37struct ch_state { 37struct ch_state {
38 int pid; 38 int pid;
@@ -120,7 +120,7 @@ static void gk20a_debug_show_channel(struct gk20a *g,
120 syncpointb = gk20a_mem_rd32(inst_ptr, ram_fc_syncpointb_w()); 120 syncpointb = gk20a_mem_rd32(inst_ptr, ram_fc_syncpointb_w());
121 121
122 gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid, 122 gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid,
123 g->dev->name, 123 dev_name(g->dev),
124 ch_state->pid, 124 ch_state->pid,
125 ch_state->refs); 125 ch_state->refs);
126 gk20a_debug_output(o, "%s in use %s %s\n", 126 gk20a_debug_output(o, "%s in use %s %s\n",
@@ -181,7 +181,7 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
181 u32 status = gk20a_readl(g, fifo_pbdma_status_r(i)); 181 u32 status = gk20a_readl(g, fifo_pbdma_status_r(i));
182 u32 chan_status = fifo_pbdma_status_chan_status_v(status); 182 u32 chan_status = fifo_pbdma_status_chan_status_v(status);
183 183
184 gk20a_debug_output(o, "%s pbdma %d: ", g->dev->name, i); 184 gk20a_debug_output(o, "%s pbdma %d: ", dev_name(g->dev), i);
185 gk20a_debug_output(o, 185 gk20a_debug_output(o,
186 "id: %d (%s), next_id: %d (%s) status: %s\n", 186 "id: %d (%s), next_id: %d (%s) status: %s\n",
187 fifo_pbdma_status_id_v(status), 187 fifo_pbdma_status_id_v(status),
@@ -206,7 +206,7 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
206 u32 status = gk20a_readl(g, fifo_engine_status_r(i)); 206 u32 status = gk20a_readl(g, fifo_engine_status_r(i));
207 u32 ctx_status = fifo_engine_status_ctx_status_v(status); 207 u32 ctx_status = fifo_engine_status_ctx_status_v(status);
208 208
209 gk20a_debug_output(o, "%s eng %d: ", g->dev->name, i); 209 gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i);
210 gk20a_debug_output(o, 210 gk20a_debug_output(o,
211 "id: %d (%s), next_id: %d (%s), ctx: %s ", 211 "id: %d (%s), next_id: %d (%s), ctx: %s ",
212 fifo_engine_status_id_v(status), 212 fifo_engine_status_id_v(status),
@@ -270,67 +270,67 @@ done:
270 gk20a_idle(g->dev); 270 gk20a_idle(g->dev);
271} 271}
272 272
273static int gk20a_gr_dump_regs(struct platform_device *pdev, 273static int gk20a_gr_dump_regs(struct device *dev,
274 struct gk20a_debug_output *o) 274 struct gk20a_debug_output *o)
275{ 275{
276 struct gk20a_platform *platform = gk20a_get_platform(pdev); 276 struct gk20a_platform *platform = gk20a_get_platform(dev);
277 struct gk20a *g = platform->g; 277 struct gk20a *g = platform->g;
278 int err; 278 int err;
279 279
280 err = gk20a_busy(g->dev); 280 err = gk20a_busy(dev);
281 if (err) { 281 if (err) {
282 gk20a_err(&pdev->dev, "failed to power on gpu: %d\n", err); 282 gk20a_err(dev, "failed to power on gpu: %d\n", err);
283 return -EINVAL; 283 return -EINVAL;
284 } 284 }
285 285
286 gr_gk20a_elpg_protected_call(g, g->ops.gr.dump_gr_regs(g, o)); 286 gr_gk20a_elpg_protected_call(g, g->ops.gr.dump_gr_regs(g, o));
287 287
288 gk20a_idle(g->dev); 288 gk20a_idle(dev);
289 289
290 return 0; 290 return 0;
291} 291}
292 292
293int gk20a_gr_debug_dump(struct platform_device *pdev) 293int gk20a_gr_debug_dump(struct device *dev)
294{ 294{
295 struct gk20a_debug_output o = { 295 struct gk20a_debug_output o = {
296 .fn = gk20a_debug_write_printk 296 .fn = gk20a_debug_write_printk
297 }; 297 };
298 298
299 gk20a_gr_dump_regs(pdev, &o); 299 gk20a_gr_dump_regs(dev, &o);
300 300
301 return 0; 301 return 0;
302} 302}
303 303
304static int gk20a_gr_debug_show(struct seq_file *s, void *unused) 304static int gk20a_gr_debug_show(struct seq_file *s, void *unused)
305{ 305{
306 struct platform_device *pdev = s->private; 306 struct device *dev = s->private;
307 struct gk20a_debug_output o = { 307 struct gk20a_debug_output o = {
308 .fn = gk20a_debug_write_to_seqfile, 308 .fn = gk20a_debug_write_to_seqfile,
309 .ctx = s, 309 .ctx = s,
310 }; 310 };
311 311
312 gk20a_gr_dump_regs(pdev, &o); 312 gk20a_gr_dump_regs(dev, &o);
313 313
314 return 0; 314 return 0;
315} 315}
316 316
317void gk20a_debug_dump(struct platform_device *pdev) 317void gk20a_debug_dump(struct device *dev)
318{ 318{
319 struct gk20a_platform *platform = gk20a_get_platform(pdev); 319 struct gk20a_platform *platform = gk20a_get_platform(dev);
320 struct gk20a *g = platform->g; 320 struct gk20a *g = platform->g;
321 struct gk20a_debug_output o = { 321 struct gk20a_debug_output o = {
322 .fn = gk20a_debug_write_printk 322 .fn = gk20a_debug_write_printk
323 }; 323 };
324 324
325 if (platform->dump_platform_dependencies) 325 if (platform->dump_platform_dependencies)
326 platform->dump_platform_dependencies(pdev); 326 platform->dump_platform_dependencies(dev);
327 327
328 /* HAL only initialized after 1st power-on */ 328 /* HAL only initialized after 1st power-on */
329 if (g->ops.debug.show_dump) 329 if (g->ops.debug.show_dump)
330 g->ops.debug.show_dump(g, &o); 330 g->ops.debug.show_dump(g, &o);
331} 331}
332 332
333void gk20a_debug_dump_device(struct platform_device *pdev) 333void gk20a_debug_dump_device(void *data)
334{ 334{
335 struct gk20a_debug_output o = { 335 struct gk20a_debug_output o = {
336 .fn = gk20a_debug_write_printk 336 .fn = gk20a_debug_write_printk
@@ -341,15 +341,7 @@ void gk20a_debug_dump_device(struct platform_device *pdev)
341 if (!tegra_platform_is_silicon()) 341 if (!tegra_platform_is_silicon())
342 return; 342 return;
343 343
344 /* Dump the first device if no info is provided */ 344 g = gk20a_from_dev(gk20a_device);
345 if (!pdev) {
346 if (!gk20a_device)
347 return;
348
349 pdev = gk20a_device;
350 }
351
352 g = gk20a_get_platform(pdev)->g;
353 /* HAL only initialized after 1st power-on */ 345 /* HAL only initialized after 1st power-on */
354 if (g->ops.debug.show_dump) 346 if (g->ops.debug.show_dump)
355 g->ops.debug.show_dump(g, &o); 347 g->ops.debug.show_dump(g, &o);
@@ -358,14 +350,14 @@ EXPORT_SYMBOL(gk20a_debug_dump_device);
358 350
359static int gk20a_debug_show(struct seq_file *s, void *unused) 351static int gk20a_debug_show(struct seq_file *s, void *unused)
360{ 352{
361 struct platform_device *pdev = s->private; 353 struct device *dev = s->private;
362 struct gk20a_debug_output o = { 354 struct gk20a_debug_output o = {
363 .fn = gk20a_debug_write_to_seqfile, 355 .fn = gk20a_debug_write_to_seqfile,
364 .ctx = s, 356 .ctx = s,
365 }; 357 };
366 struct gk20a *g; 358 struct gk20a *g;
367 359
368 g = gk20a_get_platform(pdev)->g; 360 g = gk20a_get_platform(dev)->g;
369 /* HAL only initialized after 1st power-on */ 361 /* HAL only initialized after 1st power-on */
370 if (g->ops.debug.show_dump) 362 if (g->ops.debug.show_dump)
371 g->ops.debug.show_dump(g, &o); 363 g->ops.debug.show_dump(g, &o);
@@ -401,24 +393,24 @@ void gk20a_init_debug_ops(struct gpu_ops *gops)
401 gops->debug.show_dump = gk20a_debug_show_dump; 393 gops->debug.show_dump = gk20a_debug_show_dump;
402} 394}
403 395
404void gk20a_debug_init(struct platform_device *pdev) 396void gk20a_debug_init(struct device *dev)
405{ 397{
406 struct gk20a_platform *platform = platform_get_drvdata(pdev); 398 struct gk20a_platform *platform = dev_get_drvdata(dev);
407 399
408 /* Store the first device */ 400 /* Store the first device */
409 if (!gk20a_device) 401 if (!gk20a_device)
410 gk20a_device = pdev; 402 gk20a_device = dev;
411 403
412 platform->debugfs = debugfs_create_dir(pdev->name, NULL); 404 platform->debugfs = debugfs_create_dir(dev_name(dev), NULL);
413 if (platform->debugfs) { 405 if (platform->debugfs) {
414 platform->debugfs_alias = 406 platform->debugfs_alias =
415 debugfs_create_symlink("gpu.0", NULL, pdev->name); 407 debugfs_create_symlink("gpu.0", NULL, dev_name(dev));
416 } 408 }
417 409
418 debugfs_create_file("status", S_IRUGO, platform->debugfs, 410 debugfs_create_file("status", S_IRUGO, platform->debugfs,
419 pdev, &gk20a_debug_fops); 411 dev, &gk20a_debug_fops);
420 debugfs_create_file("gr_status", S_IRUGO, platform->debugfs, 412 debugfs_create_file("gr_status", S_IRUGO, platform->debugfs,
421 pdev, &gk20a_gr_debug_fops); 413 dev, &gk20a_gr_debug_fops);
422 debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, platform->debugfs, 414 debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, platform->debugfs,
423 &gk20a_debug_trace_cmdbuf); 415 &gk20a_debug_trace_cmdbuf);
424 416
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
index 620688cb..1044f881 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Debug functionality 2 * GK20A Debug functionality
3 * 3 *
4 * Copyright (C) 2011-2015 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (C) 2011-2016 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -32,10 +32,10 @@ struct gk20a_debug_output {
32void gk20a_debug_output(struct gk20a_debug_output *o, 32void gk20a_debug_output(struct gk20a_debug_output *o,
33 const char *fmt, ...); 33 const char *fmt, ...);
34 34
35void gk20a_debug_dump(struct platform_device *pdev); 35void gk20a_debug_dump(struct device *pdev);
36void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o); 36void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o);
37int gk20a_gr_debug_dump(struct platform_device *pdev); 37int gk20a_gr_debug_dump(struct device *pdev);
38void gk20a_debug_init(struct platform_device *pdev); 38void gk20a_debug_init(struct device *dev);
39void gk20a_init_debug_ops(struct gpu_ops *gops); 39void gk20a_init_debug_ops(struct gpu_ops *gops);
40 40
41#endif 41#endif
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
index bac36403..aef0c9b3 100644
--- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
@@ -545,7 +545,7 @@ DEFINE_SIMPLE_ATTRIBUTE(gk20a_fecs_trace_debugfs_write_fops,
545 545
546static void gk20a_fecs_trace_debugfs_init(struct gk20a *g) 546static void gk20a_fecs_trace_debugfs_init(struct gk20a *g)
547{ 547{
548 struct gk20a_platform *plat = platform_get_drvdata(g->dev); 548 struct gk20a_platform *plat = dev_get_drvdata(g->dev);
549 549
550 debugfs_create_file("ctxsw_trace_read", 0600, plat->debugfs, g, 550 debugfs_create_file("ctxsw_trace_read", 0600, plat->debugfs, g,
551 &gk20a_fecs_trace_debugfs_read_fops); 551 &gk20a_fecs_trace_debugfs_read_fops);
@@ -557,7 +557,7 @@ static void gk20a_fecs_trace_debugfs_init(struct gk20a *g)
557 557
558static void gk20a_fecs_trace_debugfs_cleanup(struct gk20a *g) 558static void gk20a_fecs_trace_debugfs_cleanup(struct gk20a *g)
559{ 559{
560 struct gk20a_platform *plat = platform_get_drvdata(g->dev); 560 struct gk20a_platform *plat = dev_get_drvdata(g->dev);
561 561
562 debugfs_remove_recursive(plat->debugfs); 562 debugfs_remove_recursive(plat->debugfs);
563} 563}
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 27a3992d..4422bca4 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -348,7 +348,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
348 u32 mask; 348 u32 mask;
349 u32 timeout; 349 u32 timeout;
350 int i; 350 int i;
351 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 351 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
352 352
353 gk20a_dbg_fn(""); 353 gk20a_dbg_fn("");
354 /* enable pmc pfifo */ 354 /* enable pmc pfifo */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index f2e6a683..f3bf0517 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -44,10 +44,6 @@
44 44
45#include <linux/sched.h> 45#include <linux/sched.h>
46 46
47#ifdef CONFIG_TEGRA_GK20A
48#include <linux/nvhost.h>
49#endif
50
51#include "gk20a.h" 47#include "gk20a.h"
52#include "debug_gk20a.h" 48#include "debug_gk20a.h"
53#include "ctrl_gk20a.h" 49#include "ctrl_gk20a.h"
@@ -79,7 +75,6 @@
79 75
80#define CLASS_NAME "nvidia-gpu" 76#define CLASS_NAME "nvidia-gpu"
81/* TODO: Change to e.g. "nvidia-gpu%s" once we have symlinks in place. */ 77/* TODO: Change to e.g. "nvidia-gpu%s" once we have symlinks in place. */
82#define INTERFACE_NAME "nvhost%s-gpu"
83 78
84#define GK20A_NUM_CDEVS 7 79#define GK20A_NUM_CDEVS 7
85 80
@@ -92,12 +87,11 @@ u32 gk20a_dbg_ftrace;
92 87
93#define GK20A_WAIT_FOR_IDLE_MS 2000 88#define GK20A_WAIT_FOR_IDLE_MS 2000
94 89
95static int gk20a_pm_finalize_poweron(struct device *dev);
96static int gk20a_pm_prepare_poweroff(struct device *dev); 90static int gk20a_pm_prepare_poweroff(struct device *dev);
97 91
98static inline void set_gk20a(struct platform_device *dev, struct gk20a *gk20a) 92static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a)
99{ 93{
100 gk20a_get_platform(dev)->g = gk20a; 94 gk20a_get_platform(&pdev->dev)->g = gk20a;
101} 95}
102 96
103static const struct file_operations gk20a_channel_ops = { 97static const struct file_operations gk20a_channel_ops = {
@@ -292,38 +286,38 @@ static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i,
292} 286}
293 287
294/* TBD: strip from released */ 288/* TBD: strip from released */
295static int gk20a_init_sim_support(struct platform_device *dev) 289static int gk20a_init_sim_support(struct platform_device *pdev)
296{ 290{
297 int err = 0; 291 int err = 0;
292 struct device *dev = &pdev->dev;
298 struct gk20a *g = get_gk20a(dev); 293 struct gk20a *g = get_gk20a(dev);
299 struct device *d = &dev->dev;
300 u64 phys; 294 u64 phys;
301 295
302 g->sim.g = g; 296 g->sim.g = g;
303 g->sim.regs = gk20a_ioremap_resource(dev, GK20A_SIM_IORESOURCE_MEM, 297 g->sim.regs = gk20a_ioremap_resource(pdev, GK20A_SIM_IORESOURCE_MEM,
304 &g->sim.reg_mem); 298 &g->sim.reg_mem);
305 if (IS_ERR(g->sim.regs)) { 299 if (IS_ERR(g->sim.regs)) {
306 dev_err(d, "failed to remap gk20a sim regs\n"); 300 dev_err(dev, "failed to remap gk20a sim regs\n");
307 err = PTR_ERR(g->sim.regs); 301 err = PTR_ERR(g->sim.regs);
308 goto fail; 302 goto fail;
309 } 303 }
310 304
311 /* allocate sim event/msg buffers */ 305 /* allocate sim event/msg buffers */
312 err = alloc_and_kmap_iopage(d, &g->sim.send_bfr.kvaddr, 306 err = alloc_and_kmap_iopage(dev, &g->sim.send_bfr.kvaddr,
313 &g->sim.send_bfr.phys, 307 &g->sim.send_bfr.phys,
314 &g->sim.send_bfr.page); 308 &g->sim.send_bfr.page);
315 309
316 err = err || alloc_and_kmap_iopage(d, &g->sim.recv_bfr.kvaddr, 310 err = err || alloc_and_kmap_iopage(dev, &g->sim.recv_bfr.kvaddr,
317 &g->sim.recv_bfr.phys, 311 &g->sim.recv_bfr.phys,
318 &g->sim.recv_bfr.page); 312 &g->sim.recv_bfr.page);
319 313
320 err = err || alloc_and_kmap_iopage(d, &g->sim.msg_bfr.kvaddr, 314 err = err || alloc_and_kmap_iopage(dev, &g->sim.msg_bfr.kvaddr,
321 &g->sim.msg_bfr.phys, 315 &g->sim.msg_bfr.phys,
322 &g->sim.msg_bfr.page); 316 &g->sim.msg_bfr.page);
323 317
324 if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && 318 if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr &&
325 g->sim.msg_bfr.kvaddr)) { 319 g->sim.msg_bfr.kvaddr)) {
326 dev_err(d, "couldn't allocate all sim buffers\n"); 320 dev_err(dev, "couldn't allocate all sim buffers\n");
327 goto fail; 321 goto fail;
328 } 322 }
329 323
@@ -566,25 +560,25 @@ void gk20a_pbus_isr(struct gk20a *g)
566 gk20a_err(dev_from_gk20a(g), "pmc_enable : 0x%x", 560 gk20a_err(dev_from_gk20a(g), "pmc_enable : 0x%x",
567 gk20a_readl(g, mc_enable_r())); 561 gk20a_readl(g, mc_enable_r()));
568 gk20a_err(dev_from_gk20a(g), "NV_PBUS_INTR_0 : 0x%x", val); 562 gk20a_err(dev_from_gk20a(g), "NV_PBUS_INTR_0 : 0x%x", val);
569 gk20a_err(&g->dev->dev, 563 gk20a_err(g->dev,
570 "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n", 564 "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n",
571 gk20a_readl(g, timer_pri_timeout_save_0_r())); 565 gk20a_readl(g, timer_pri_timeout_save_0_r()));
572 gk20a_err(&g->dev->dev, 566 gk20a_err(g->dev,
573 "NV_PTIMER_PRI_TIMEOUT_SAVE_1: 0x%x\n", 567 "NV_PTIMER_PRI_TIMEOUT_SAVE_1: 0x%x\n",
574 gk20a_readl(g, timer_pri_timeout_save_1_r())); 568 gk20a_readl(g, timer_pri_timeout_save_1_r()));
575 err_code = gk20a_readl(g, timer_pri_timeout_fecs_errcode_r()); 569 err_code = gk20a_readl(g, timer_pri_timeout_fecs_errcode_r());
576 gk20a_err(&g->dev->dev, 570 gk20a_err(g->dev,
577 "NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE: 0x%x\n", 571 "NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE: 0x%x\n",
578 err_code); 572 err_code);
579 if (err_code == 0xbadf13) 573 if (err_code == 0xbadf13)
580 gk20a_err(&g->dev->dev, 574 gk20a_err(g->dev,
581 "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n", 575 "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n",
582 gk20a_readl(g, gr_gpc0_fs_gpc_r())); 576 gk20a_readl(g, gr_gpc0_fs_gpc_r()));
583 577
584 } 578 }
585 579
586 if (val) 580 if (val)
587 gk20a_err(&g->dev->dev, 581 gk20a_err(g->dev,
588 "Unhandled pending pbus interrupt\n"); 582 "Unhandled pending pbus interrupt\n");
589 583
590 gk20a_writel(g, bus_intr_0_r(), val); 584 gk20a_writel(g, bus_intr_0_r(), val);
@@ -602,7 +596,7 @@ static irqreturn_t gk20a_intr_thread_nonstall(int irq, void *dev_id)
602 return g->ops.mc.isr_thread_nonstall(g); 596 return g->ops.mc.isr_thread_nonstall(g);
603} 597}
604 598
605static void gk20a_remove_support(struct platform_device *dev) 599static void gk20a_remove_support(struct device *dev)
606{ 600{
607 struct gk20a *g = get_gk20a(dev); 601 struct gk20a *g = get_gk20a(dev);
608 602
@@ -642,7 +636,7 @@ static void gk20a_remove_support(struct platform_device *dev)
642static int gk20a_init_support(struct platform_device *dev) 636static int gk20a_init_support(struct platform_device *dev)
643{ 637{
644 int err = 0; 638 int err = 0;
645 struct gk20a *g = get_gk20a(dev); 639 struct gk20a *g = get_gk20a(&dev->dev);
646 640
647#ifdef CONFIG_TEGRA_COMMON 641#ifdef CONFIG_TEGRA_COMMON
648 tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle); 642 tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle);
@@ -689,14 +683,13 @@ static int gk20a_init_support(struct platform_device *dev)
689 return 0; 683 return 0;
690 684
691 fail: 685 fail:
692 gk20a_remove_support(dev); 686 gk20a_remove_support(&dev->dev);
693 return err; 687 return err;
694} 688}
695 689
696static int gk20a_pm_prepare_poweroff(struct device *dev) 690static int gk20a_pm_prepare_poweroff(struct device *dev)
697{ 691{
698 struct platform_device *pdev = to_platform_device(dev); 692 struct gk20a *g = get_gk20a(dev);
699 struct gk20a *g = get_gk20a(pdev);
700 int ret = 0; 693 int ret = 0;
701 694
702 gk20a_dbg_fn(""); 695 gk20a_dbg_fn("");
@@ -706,7 +699,7 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
706 if (!g->power_on) 699 if (!g->power_on)
707 goto done; 700 goto done;
708 701
709 gk20a_scale_suspend(pdev); 702 gk20a_scale_suspend(dev);
710 703
711 /* cancel any pending cde work */ 704 /* cancel any pending cde work */
712 gk20a_cde_suspend(g); 705 gk20a_cde_suspend(g);
@@ -767,11 +760,10 @@ static int gk20a_detect_chip(struct gk20a *g)
767 return gpu_init_hal(g); 760 return gpu_init_hal(g);
768} 761}
769 762
770static int gk20a_pm_finalize_poweron(struct device *dev) 763int gk20a_pm_finalize_poweron(struct device *dev)
771{ 764{
772 struct platform_device *pdev = to_platform_device(dev); 765 struct gk20a *g = get_gk20a(dev);
773 struct gk20a *g = get_gk20a(pdev); 766 struct gk20a_platform *platform = gk20a_get_platform(dev);
774 struct gk20a_platform *platform = gk20a_get_platform(pdev);
775 int err, nice_value; 767 int err, nice_value;
776 768
777 gk20a_dbg_fn(""); 769 gk20a_dbg_fn("");
@@ -904,7 +896,7 @@ static int gk20a_pm_finalize_poweron(struct device *dev)
904 gk20a_channel_resume(g); 896 gk20a_channel_resume(g);
905 set_user_nice(current, nice_value); 897 set_user_nice(current, nice_value);
906 898
907 gk20a_scale_resume(pdev); 899 gk20a_scale_resume(dev);
908 900
909 trace_gk20a_finalize_poweron_done(dev_name(dev)); 901 trace_gk20a_finalize_poweron_done(dev_name(dev));
910 902
@@ -955,13 +947,13 @@ static struct of_device_id tegra_gk20a_of_match[] = {
955}; 947};
956 948
957static int gk20a_create_device( 949static int gk20a_create_device(
958 struct platform_device *pdev, int devno, const char *cdev_name, 950 struct device *dev, int devno,
951 const char *interface_name, const char *cdev_name,
959 struct cdev *cdev, struct device **out, 952 struct cdev *cdev, struct device **out,
960 const struct file_operations *ops) 953 const struct file_operations *ops)
961{ 954{
962 struct device *dev; 955 struct device *subdev;
963 int err; 956 int err;
964 struct gk20a *g = get_gk20a(pdev);
965 957
966 gk20a_dbg_fn(""); 958 gk20a_dbg_fn("");
967 959
@@ -970,127 +962,112 @@ static int gk20a_create_device(
970 962
971 err = cdev_add(cdev, devno, 1); 963 err = cdev_add(cdev, devno, 1);
972 if (err) { 964 if (err) {
973 dev_err(&pdev->dev, 965 dev_err(dev, "failed to add %s cdev\n", cdev_name);
974 "failed to add %s cdev\n", cdev_name);
975 return err; 966 return err;
976 } 967 }
977 968
978 dev = device_create(g->class, NULL, devno, NULL, 969 subdev = device_create(&nvgpu_class, NULL, devno, NULL,
979 (pdev->id <= 0) ? INTERFACE_NAME : INTERFACE_NAME ".%d", 970 interface_name, cdev_name);
980 cdev_name, pdev->id);
981 971
982 if (IS_ERR(dev)) { 972 if (IS_ERR(subdev)) {
983 err = PTR_ERR(dev); 973 err = PTR_ERR(dev);
984 cdev_del(cdev); 974 cdev_del(cdev);
985 dev_err(&pdev->dev, 975 dev_err(dev, "failed to create %s device for %s\n",
986 "failed to create %s device for %s\n", 976 cdev_name, dev_name(dev));
987 cdev_name, pdev->name);
988 return err; 977 return err;
989 } 978 }
990 979
991 *out = dev; 980 *out = subdev;
992 return 0; 981 return 0;
993} 982}
994 983
995void gk20a_user_deinit(struct platform_device *dev) 984void gk20a_user_deinit(struct device *dev)
996{ 985{
997 struct gk20a *g = get_gk20a(dev); 986 struct gk20a *g = gk20a_from_dev(dev);
998 987
999 if (g->channel.node) { 988 if (g->channel.node) {
1000 device_destroy(g->class, g->channel.cdev.dev); 989 device_destroy(&nvgpu_class, g->channel.cdev.dev);
1001 cdev_del(&g->channel.cdev); 990 cdev_del(&g->channel.cdev);
1002 } 991 }
1003 992
1004 if (g->as.node) { 993 if (g->as.node) {
1005 device_destroy(g->class, g->as.cdev.dev); 994 device_destroy(&nvgpu_class, g->as.cdev.dev);
1006 cdev_del(&g->as.cdev); 995 cdev_del(&g->as.cdev);
1007 } 996 }
1008 997
1009 if (g->ctrl.node) { 998 if (g->ctrl.node) {
1010 device_destroy(g->class, g->ctrl.cdev.dev); 999 device_destroy(&nvgpu_class, g->ctrl.cdev.dev);
1011 cdev_del(&g->ctrl.cdev); 1000 cdev_del(&g->ctrl.cdev);
1012 } 1001 }
1013 1002
1014 if (g->dbg.node) { 1003 if (g->dbg.node) {
1015 device_destroy(g->class, g->dbg.cdev.dev); 1004 device_destroy(&nvgpu_class, g->dbg.cdev.dev);
1016 cdev_del(&g->dbg.cdev); 1005 cdev_del(&g->dbg.cdev);
1017 } 1006 }
1018 1007
1019 if (g->prof.node) { 1008 if (g->prof.node) {
1020 device_destroy(g->class, g->prof.cdev.dev); 1009 device_destroy(&nvgpu_class, g->prof.cdev.dev);
1021 cdev_del(&g->prof.cdev); 1010 cdev_del(&g->prof.cdev);
1022 } 1011 }
1023 1012
1024 if (g->tsg.node) { 1013 if (g->tsg.node) {
1025 device_destroy(g->class, g->tsg.cdev.dev); 1014 device_destroy(&nvgpu_class, g->tsg.cdev.dev);
1026 cdev_del(&g->tsg.cdev); 1015 cdev_del(&g->tsg.cdev);
1027 } 1016 }
1028 1017
1029 if (g->ctxsw.node) { 1018 if (g->ctxsw.node) {
1030 device_destroy(g->class, g->ctxsw.cdev.dev); 1019 device_destroy(&nvgpu_class, g->ctxsw.cdev.dev);
1031 cdev_del(&g->ctxsw.cdev); 1020 cdev_del(&g->ctxsw.cdev);
1032 } 1021 }
1033 1022
1034 if (g->cdev_region) 1023 if (g->cdev_region)
1035 unregister_chrdev_region(g->cdev_region, GK20A_NUM_CDEVS); 1024 unregister_chrdev_region(g->cdev_region, GK20A_NUM_CDEVS);
1036
1037 if (g->class)
1038 class_destroy(g->class);
1039} 1025}
1040 1026
1041int gk20a_user_init(struct platform_device *dev) 1027int gk20a_user_init(struct device *dev, const char *interface_name)
1042{ 1028{
1043 int err; 1029 int err;
1044 dev_t devno; 1030 dev_t devno;
1045 struct gk20a *g = get_gk20a(dev); 1031 struct gk20a *g = gk20a_from_dev(dev);
1046
1047 g->class = class_create(THIS_MODULE, CLASS_NAME);
1048 if (IS_ERR(g->class)) {
1049 err = PTR_ERR(g->class);
1050 g->class = NULL;
1051 dev_err(&dev->dev,
1052 "failed to create " CLASS_NAME " class\n");
1053 goto fail;
1054 }
1055 1032
1056 err = alloc_chrdev_region(&devno, 0, GK20A_NUM_CDEVS, CLASS_NAME); 1033 err = alloc_chrdev_region(&devno, 0, GK20A_NUM_CDEVS, dev_name(dev));
1057 if (err) { 1034 if (err) {
1058 dev_err(&dev->dev, "failed to allocate devno\n"); 1035 dev_err(dev, "failed to allocate devno\n");
1059 goto fail; 1036 goto fail;
1060 } 1037 }
1061 g->cdev_region = devno; 1038 g->cdev_region = devno;
1062 1039
1063 err = gk20a_create_device(dev, devno++, "", 1040 err = gk20a_create_device(dev, devno++, interface_name, "",
1064 &g->channel.cdev, &g->channel.node, 1041 &g->channel.cdev, &g->channel.node,
1065 &gk20a_channel_ops); 1042 &gk20a_channel_ops);
1066 if (err) 1043 if (err)
1067 goto fail; 1044 goto fail;
1068 1045
1069 err = gk20a_create_device(dev, devno++, "-as", 1046 err = gk20a_create_device(dev, devno++, interface_name, "-as",
1070 &g->as.cdev, &g->as.node, 1047 &g->as.cdev, &g->as.node,
1071 &gk20a_as_ops); 1048 &gk20a_as_ops);
1072 if (err) 1049 if (err)
1073 goto fail; 1050 goto fail;
1074 1051
1075 err = gk20a_create_device(dev, devno++, "-ctrl", 1052 err = gk20a_create_device(dev, devno++, interface_name, "-ctrl",
1076 &g->ctrl.cdev, &g->ctrl.node, 1053 &g->ctrl.cdev, &g->ctrl.node,
1077 &gk20a_ctrl_ops); 1054 &gk20a_ctrl_ops);
1078 if (err) 1055 if (err)
1079 goto fail; 1056 goto fail;
1080 1057
1081 err = gk20a_create_device(dev, devno++, "-dbg", 1058 err = gk20a_create_device(dev, devno++, interface_name, "-dbg",
1082 &g->dbg.cdev, &g->dbg.node, 1059 &g->dbg.cdev, &g->dbg.node,
1083 &gk20a_dbg_ops); 1060 &gk20a_dbg_ops);
1084 if (err) 1061 if (err)
1085 goto fail; 1062 goto fail;
1086 1063
1087 err = gk20a_create_device(dev, devno++, "-prof", 1064 err = gk20a_create_device(dev, devno++, interface_name, "-prof",
1088 &g->prof.cdev, &g->prof.node, 1065 &g->prof.cdev, &g->prof.node,
1089 &gk20a_prof_ops); 1066 &gk20a_prof_ops);
1090 if (err) 1067 if (err)
1091 goto fail; 1068 goto fail;
1092 1069
1093 err = gk20a_create_device(dev, devno++, "-tsg", 1070 err = gk20a_create_device(dev, devno++, interface_name, "-tsg",
1094 &g->tsg.cdev, &g->tsg.node, 1071 &g->tsg.cdev, &g->tsg.node,
1095 &gk20a_tsg_ops); 1072 &gk20a_tsg_ops);
1096 if (err) 1073 if (err)
@@ -1190,7 +1167,7 @@ static void gk20a_pm_shutdown(struct platform_device *pdev)
1190#endif 1167#endif
1191 1168
1192 /* Be ready for rail-gate after this point */ 1169 /* Be ready for rail-gate after this point */
1193 if (gk20a_gpu_is_virtual(pdev)) 1170 if (gk20a_gpu_is_virtual(&pdev->dev))
1194 vgpu_pm_prepare_poweroff(&pdev->dev); 1171 vgpu_pm_prepare_poweroff(&pdev->dev);
1195 else 1172 else
1196 gk20a_pm_prepare_poweroff(&pdev->dev); 1173 gk20a_pm_prepare_poweroff(&pdev->dev);
@@ -1205,12 +1182,12 @@ static const struct dev_pm_ops gk20a_pm_ops = {
1205}; 1182};
1206#endif 1183#endif
1207 1184
1208static int _gk20a_pm_railgate(struct platform_device *pdev) 1185static int _gk20a_pm_railgate(struct device *dev)
1209{ 1186{
1210 struct gk20a_platform *platform = platform_get_drvdata(pdev); 1187 struct gk20a_platform *platform = dev_get_drvdata(dev);
1211 int ret = 0; 1188 int ret = 0;
1212 if (platform->railgate) 1189 if (platform->railgate)
1213 ret = platform->railgate(pdev); 1190 ret = platform->railgate(dev);
1214 return ret; 1191 return ret;
1215} 1192}
1216 1193
@@ -1223,14 +1200,14 @@ static int gk20a_pm_railgate(struct generic_pm_domain *domain)
1223 return _gk20a_pm_railgate(g->dev); 1200 return _gk20a_pm_railgate(g->dev);
1224} 1201}
1225 1202
1226static int _gk20a_pm_unrailgate(struct platform_device *pdev) 1203static int _gk20a_pm_unrailgate(struct device *dev)
1227{ 1204{
1228 struct gk20a_platform *platform = platform_get_drvdata(pdev); 1205 struct gk20a_platform *platform = dev_get_drvdata(dev);
1229 int ret = 0; 1206 int ret = 0;
1230 1207
1231 if (platform->unrailgate) { 1208 if (platform->unrailgate) {
1232 mutex_lock(&platform->railgate_lock); 1209 mutex_lock(&platform->railgate_lock);
1233 ret = platform->unrailgate(pdev); 1210 ret = platform->unrailgate(dev);
1234 mutex_unlock(&platform->railgate_lock); 1211 mutex_unlock(&platform->railgate_lock);
1235 } 1212 }
1236 1213
@@ -1242,7 +1219,7 @@ static int gk20a_pm_unrailgate(struct generic_pm_domain *domain)
1242 struct gk20a_domain_data *gk20a_domain = container_of(domain, 1219 struct gk20a_domain_data *gk20a_domain = container_of(domain,
1243 struct gk20a_domain_data, gpd); 1220 struct gk20a_domain_data, gpd);
1244 struct gk20a *g = gk20a_domain->gk20a; 1221 struct gk20a *g = gk20a_domain->gk20a;
1245 trace_gk20a_pm_unrailgate(dev_name(&g->dev->dev)); 1222 trace_gk20a_pm_unrailgate(dev_name(g->dev));
1246 1223
1247 return _gk20a_pm_unrailgate(g->dev); 1224 return _gk20a_pm_unrailgate(g->dev);
1248} 1225}
@@ -1273,11 +1250,14 @@ static int gk20a_pm_resume(struct device *dev)
1273} 1250}
1274 1251
1275#ifdef CONFIG_PM_GENERIC_DOMAINS_OF 1252#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
1276static int gk20a_pm_initialise_domain(struct platform_device *pdev) 1253static int gk20a_pm_initialise_domain(struct device *dev)
1277{ 1254{
1278 struct gk20a_platform *platform = platform_get_drvdata(pdev); 1255 struct gk20a_platform *platform = dev_get_drvdata(dev);
1279 struct dev_power_governor *pm_domain_gov = NULL; 1256 struct dev_power_governor *pm_domain_gov = NULL;
1280 struct generic_pm_domain *domain = dev_to_genpd(&pdev->dev); 1257 struct generic_pm_domain *domain = dev_to_genpd(dev);
1258
1259 if (IS_ERR(domain))
1260 return 0;
1281 1261
1282#ifdef CONFIG_PM 1262#ifdef CONFIG_PM
1283 if (!platform->can_railgate) 1263 if (!platform->can_railgate)
@@ -1288,14 +1268,14 @@ static int gk20a_pm_initialise_domain(struct platform_device *pdev)
1288 if (platform->railgate_delay) 1268 if (platform->railgate_delay)
1289 pm_genpd_set_poweroff_delay(domain, platform->railgate_delay); 1269 pm_genpd_set_poweroff_delay(domain, platform->railgate_delay);
1290 1270
1291 device_set_wakeup_capable(&pdev->dev, 0); 1271 device_set_wakeup_capable(dev, 0);
1292 return 0; 1272 return 0;
1293} 1273}
1294 1274
1295#else 1275#else
1296static int gk20a_pm_initialise_domain(struct platform_device *pdev) 1276static int gk20a_pm_initialise_domain(struct device *dev)
1297{ 1277{
1298 struct gk20a_platform *platform = platform_get_drvdata(pdev); 1278 struct gk20a_platform *platform = dev_get_drvdata(dev);
1299 struct dev_power_governor *pm_domain_gov = NULL; 1279 struct dev_power_governor *pm_domain_gov = NULL;
1300 struct generic_pm_domain *domain = NULL; 1280 struct generic_pm_domain *domain = NULL;
1301 int ret = 0; 1281 int ret = 0;
@@ -1326,8 +1306,8 @@ static int gk20a_pm_initialise_domain(struct platform_device *pdev)
1326 domain->dev_ops.suspend = gk20a_pm_suspend; 1306 domain->dev_ops.suspend = gk20a_pm_suspend;
1327 domain->dev_ops.resume = gk20a_pm_resume; 1307 domain->dev_ops.resume = gk20a_pm_resume;
1328 1308
1329 device_set_wakeup_capable(&pdev->dev, 0); 1309 device_set_wakeup_capable(dev, 0);
1330 ret = pm_genpd_add_device(domain, &pdev->dev); 1310 ret = pm_genpd_add_device(domain, dev);
1331 1311
1332 if (platform->railgate_delay) 1312 if (platform->railgate_delay)
1333 pm_genpd_set_poweroff_delay(domain, platform->railgate_delay); 1313 pm_genpd_set_poweroff_delay(domain, platform->railgate_delay);
@@ -1336,23 +1316,23 @@ static int gk20a_pm_initialise_domain(struct platform_device *pdev)
1336} 1316}
1337#endif 1317#endif
1338 1318
1339static int gk20a_pm_init(struct platform_device *dev) 1319static int gk20a_pm_init(struct device *dev)
1340{ 1320{
1341 struct gk20a_platform *platform = platform_get_drvdata(dev); 1321 struct gk20a_platform *platform = dev_get_drvdata(dev);
1342 int err = 0; 1322 int err = 0;
1343 1323
1344 gk20a_dbg_fn(""); 1324 gk20a_dbg_fn("");
1345 1325
1346 /* Initialise pm runtime */ 1326 /* Initialise pm runtime */
1347 if (platform->clockgate_delay) { 1327 if (platform->clockgate_delay) {
1348 pm_runtime_set_autosuspend_delay(&dev->dev, 1328 pm_runtime_set_autosuspend_delay(dev,
1349 platform->clockgate_delay); 1329 platform->clockgate_delay);
1350 pm_runtime_use_autosuspend(&dev->dev); 1330 pm_runtime_use_autosuspend(dev);
1351 } 1331 }
1352 1332
1353 pm_runtime_enable(&dev->dev); 1333 pm_runtime_enable(dev);
1354 if (!pm_runtime_enabled(&dev->dev)) 1334 if (!pm_runtime_enabled(dev))
1355 gk20a_pm_enable_clk(&dev->dev); 1335 gk20a_pm_enable_clk(dev);
1356 1336
1357 /* Enable runtime railgating if possible. If not, 1337 /* Enable runtime railgating if possible. If not,
1358 * turn on the rail now. */ 1338 * turn on the rail now. */
@@ -1374,7 +1354,7 @@ static int gk20a_secure_page_alloc(struct platform_device *pdev)
1374 int err = 0; 1354 int err = 0;
1375 1355
1376 if (platform->secure_page_alloc) { 1356 if (platform->secure_page_alloc) {
1377 err = platform->secure_page_alloc(pdev); 1357 err = platform->secure_page_alloc(&pdev->dev);
1378 if (!err) 1358 if (!err)
1379 platform->secure_alloc_ready = true; 1359 platform->secure_alloc_ready = true;
1380 } 1360 }
@@ -1418,7 +1398,7 @@ static int gk20a_probe(struct platform_device *dev)
1418 1398
1419 platform_set_drvdata(dev, platform); 1399 platform_set_drvdata(dev, platform);
1420 1400
1421 if (gk20a_gpu_is_virtual(dev)) 1401 if (gk20a_gpu_is_virtual(&dev->dev))
1422 return vgpu_probe(dev); 1402 return vgpu_probe(dev);
1423 1403
1424 gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL); 1404 gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL);
@@ -1437,7 +1417,7 @@ static int gk20a_probe(struct platform_device *dev)
1437#endif 1417#endif
1438 1418
1439 set_gk20a(dev, gk20a); 1419 set_gk20a(dev, gk20a);
1440 gk20a->dev = dev; 1420 gk20a->dev = &dev->dev;
1441 1421
1442 gk20a->irq_stall = platform_get_irq(dev, 0); 1422 gk20a->irq_stall = platform_get_irq(dev, 0);
1443 gk20a->irq_nonstall = platform_get_irq(dev, 1); 1423 gk20a->irq_nonstall = platform_get_irq(dev, 1);
@@ -1468,7 +1448,7 @@ static int gk20a_probe(struct platform_device *dev)
1468 disable_irq(gk20a->irq_stall); 1448 disable_irq(gk20a->irq_stall);
1469 disable_irq(gk20a->irq_nonstall); 1449 disable_irq(gk20a->irq_nonstall);
1470 1450
1471 err = gk20a_user_init(dev); 1451 err = gk20a_user_init(&dev->dev, INTERFACE_NAME);
1472 if (err) 1452 if (err)
1473 return err; 1453 return err;
1474 1454
@@ -1485,10 +1465,10 @@ static int gk20a_probe(struct platform_device *dev)
1485 platform->reset_control = NULL; 1465 platform->reset_control = NULL;
1486#endif 1466#endif
1487 1467
1488 gk20a_debug_init(dev); 1468 gk20a_debug_init(&dev->dev);
1489 1469
1490 /* Initialize the platform interface. */ 1470 /* Initialize the platform interface. */
1491 err = platform->probe(dev); 1471 err = platform->probe(&dev->dev);
1492 if (err) { 1472 if (err) {
1493 dev_err(&dev->dev, "platform probe failed"); 1473 dev_err(&dev->dev, "platform probe failed");
1494 return err; 1474 return err;
@@ -1499,7 +1479,7 @@ static int gk20a_probe(struct platform_device *dev)
1499 dev_err(&dev->dev, 1479 dev_err(&dev->dev,
1500 "failed to allocate secure buffer %d\n", err); 1480 "failed to allocate secure buffer %d\n", err);
1501 1481
1502 err = gk20a_pm_init(dev); 1482 err = gk20a_pm_init(&dev->dev);
1503 if (err) { 1483 if (err) {
1504 dev_err(&dev->dev, "pm init failed"); 1484 dev_err(&dev->dev, "pm init failed");
1505 return err; 1485 return err;
@@ -1509,7 +1489,7 @@ static int gk20a_probe(struct platform_device *dev)
1509 1489
1510 /* Initialise scaling */ 1490 /* Initialise scaling */
1511 if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) 1491 if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
1512 gk20a_scale_init(dev); 1492 gk20a_scale_init(&dev->dev);
1513 1493
1514 /* Set DMA parameters to allow larger sgt lists */ 1494 /* Set DMA parameters to allow larger sgt lists */
1515 dev->dev.dma_parms = &gk20a->dma_parms; 1495 dev->dev.dma_parms = &gk20a->dma_parms;
@@ -1547,14 +1527,14 @@ static int gk20a_probe(struct platform_device *dev)
1547 gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; 1527 gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT;
1548 1528
1549 if (platform->late_probe) { 1529 if (platform->late_probe) {
1550 err = platform->late_probe(dev); 1530 err = platform->late_probe(&dev->dev);
1551 if (err) { 1531 if (err) {
1552 dev_err(&dev->dev, "late probe failed"); 1532 dev_err(&dev->dev, "late probe failed");
1553 return err; 1533 return err;
1554 } 1534 }
1555 } 1535 }
1556 1536
1557 gk20a_create_sysfs(dev); 1537 gk20a_create_sysfs(&dev->dev);
1558 1538
1559#ifdef CONFIG_DEBUG_FS 1539#ifdef CONFIG_DEBUG_FS
1560 spin_lock_init(&gk20a->debugfs_lock); 1540 spin_lock_init(&gk20a->debugfs_lock);
@@ -1612,10 +1592,10 @@ static int gk20a_probe(struct platform_device *dev)
1612 &gk20a->runlist_interleave); 1592 &gk20a->runlist_interleave);
1613 1593
1614 gr_gk20a_debugfs_init(gk20a); 1594 gr_gk20a_debugfs_init(gk20a);
1615 gk20a_pmu_debugfs_init(dev); 1595 gk20a_pmu_debugfs_init(&dev->dev);
1616 gk20a_cde_debugfs_init(dev); 1596 gk20a_cde_debugfs_init(&dev->dev);
1617 gk20a_alloc_debugfs_init(dev); 1597 gk20a_alloc_debugfs_init(dev);
1618 gk20a_mm_debugfs_init(dev); 1598 gk20a_mm_debugfs_init(&dev->dev);
1619#endif 1599#endif
1620 1600
1621 gk20a_init_gr(gk20a); 1601 gk20a_init_gr(gk20a);
@@ -1623,8 +1603,9 @@ static int gk20a_probe(struct platform_device *dev)
1623 return 0; 1603 return 0;
1624} 1604}
1625 1605
1626static int __exit gk20a_remove(struct platform_device *dev) 1606static int __exit gk20a_remove(struct platform_device *pdev)
1627{ 1607{
1608 struct device *dev = &pdev->dev;
1628 struct gk20a *g = get_gk20a(dev); 1609 struct gk20a *g = get_gk20a(dev);
1629 struct gk20a_platform *platform = gk20a_get_platform(dev); 1610 struct gk20a_platform *platform = gk20a_get_platform(dev);
1630 struct gk20a_domain_data *gk20a_gpd; 1611 struct gk20a_domain_data *gk20a_gpd;
@@ -1632,7 +1613,7 @@ static int __exit gk20a_remove(struct platform_device *dev)
1632 gk20a_dbg_fn(""); 1613 gk20a_dbg_fn("");
1633 1614
1634 if (gk20a_gpu_is_virtual(dev)) 1615 if (gk20a_gpu_is_virtual(dev))
1635 return vgpu_remove(dev); 1616 return vgpu_remove(pdev);
1636 1617
1637 if (platform->has_cde) 1618 if (platform->has_cde)
1638 gk20a_cde_destroy(g); 1619 gk20a_cde_destroy(g);
@@ -1650,7 +1631,7 @@ static int __exit gk20a_remove(struct platform_device *dev)
1650 debugfs_remove_recursive(platform->debugfs); 1631 debugfs_remove_recursive(platform->debugfs);
1651 debugfs_remove_recursive(platform->debugfs_alias); 1632 debugfs_remove_recursive(platform->debugfs_alias);
1652 1633
1653 gk20a_remove_sysfs(&dev->dev); 1634 gk20a_remove_sysfs(dev);
1654 1635
1655 if (platform->secure_buffer.destroy) 1636 if (platform->secure_buffer.destroy)
1656 platform->secure_buffer.destroy(dev, 1637 platform->secure_buffer.destroy(dev,
@@ -1660,15 +1641,15 @@ static int __exit gk20a_remove(struct platform_device *dev)
1660 gk20a_gpd->gk20a = NULL; 1641 gk20a_gpd->gk20a = NULL;
1661 kfree(gk20a_gpd); 1642 kfree(gk20a_gpd);
1662 1643
1663 if (pm_runtime_enabled(&dev->dev)) 1644 if (pm_runtime_enabled(dev))
1664 pm_runtime_disable(&dev->dev); 1645 pm_runtime_disable(dev);
1665 else 1646 else
1666 gk20a_pm_disable_clk(&dev->dev); 1647 gk20a_pm_disable_clk(dev);
1667 1648
1668 if (platform->remove) 1649 if (platform->remove)
1669 platform->remove(dev); 1650 platform->remove(dev);
1670 1651
1671 set_gk20a(dev, NULL); 1652 set_gk20a(pdev, NULL);
1672 kfree(g); 1653 kfree(g);
1673 1654
1674 gk20a_dbg_fn("removed"); 1655 gk20a_dbg_fn("removed");
@@ -1751,11 +1732,20 @@ static int gk20a_domain_init(struct of_device_id *matches)
1751#endif 1732#endif
1752 1733
1753 1734
1735struct class nvgpu_class = {
1736 .owner = THIS_MODULE,
1737 .name = CLASS_NAME,
1738};
1739
1754static int __init gk20a_init(void) 1740static int __init gk20a_init(void)
1755{ 1741{
1756 1742
1757 int ret; 1743 int ret;
1758 1744
1745 ret = class_register(&nvgpu_class);
1746 if (ret)
1747 return ret;
1748
1759 ret = gk20a_domain_init(tegra_gpu_domain_match); 1749 ret = gk20a_domain_init(tegra_gpu_domain_match);
1760 if (ret) 1750 if (ret)
1761 return ret; 1751 return ret;
@@ -1766,50 +1756,51 @@ static int __init gk20a_init(void)
1766static void __exit gk20a_exit(void) 1756static void __exit gk20a_exit(void)
1767{ 1757{
1768 platform_driver_unregister(&gk20a_driver); 1758 platform_driver_unregister(&gk20a_driver);
1759 class_unregister(&nvgpu_class);
1769} 1760}
1770 1761
1771void gk20a_busy_noresume(struct platform_device *pdev) 1762void gk20a_busy_noresume(struct device *dev)
1772{ 1763{
1773 pm_runtime_get_noresume(&pdev->dev); 1764 pm_runtime_get_noresume(dev);
1774} 1765}
1775 1766
1776int gk20a_busy(struct platform_device *pdev) 1767int gk20a_busy(struct device *dev)
1777{ 1768{
1778 int ret = 0; 1769 int ret = 0;
1779 struct gk20a *g = get_gk20a(pdev); 1770 struct gk20a *g = get_gk20a(dev);
1780#ifdef CONFIG_PM 1771#ifdef CONFIG_PM
1781 struct gk20a_platform *platform = gk20a_get_platform(pdev); 1772 struct gk20a_platform *platform = gk20a_get_platform(dev);
1782#endif 1773#endif
1783 1774
1784 down_read(&g->busy_lock); 1775 down_read(&g->busy_lock);
1785 1776
1786#ifdef CONFIG_PM 1777#ifdef CONFIG_PM
1787 if (platform->busy) { 1778 if (platform->busy) {
1788 ret = platform->busy(pdev); 1779 ret = platform->busy(dev);
1789 if (ret < 0) { 1780 if (ret < 0) {
1790 dev_err(&pdev->dev, "%s: failed to poweron platform dependency\n", 1781 dev_err(dev, "%s: failed to poweron platform dependency\n",
1791 __func__); 1782 __func__);
1792 goto fail; 1783 goto fail;
1793 } 1784 }
1794 } 1785 }
1795 1786
1796 ret = pm_runtime_get_sync(&pdev->dev); 1787 ret = pm_runtime_get_sync(dev);
1797 if (ret < 0) { 1788 if (ret < 0) {
1798 pm_runtime_put_noidle(&pdev->dev); 1789 pm_runtime_put_noidle(dev);
1799 if (platform->idle) 1790 if (platform->idle)
1800 platform->idle(pdev); 1791 platform->idle(dev);
1801 goto fail; 1792 goto fail;
1802 } 1793 }
1803#else 1794#else
1804 if (!g->power_on) { 1795 if (!g->power_on) {
1805 ret = gk20a_gpu_is_virtual(pdev) ? 1796 ret = gk20a_gpu_is_virtual(pdev) ?
1806 vgpu_pm_finalize_poweron(&pdev->dev) 1797 vgpu_pm_finalize_poweron(dev)
1807 : gk20a_pm_finalize_poweron(&pdev->dev); 1798 : gk20a_pm_finalize_poweron(dev);
1808 if (ret) 1799 if (ret)
1809 goto fail; 1800 goto fail;
1810 } 1801 }
1811#endif 1802#endif
1812 gk20a_scale_notify_busy(pdev); 1803 gk20a_scale_notify_busy(dev);
1813 1804
1814fail: 1805fail:
1815 up_read(&g->busy_lock); 1806 up_read(&g->busy_lock);
@@ -1817,19 +1808,19 @@ fail:
1817 return ret < 0 ? ret : 0; 1808 return ret < 0 ? ret : 0;
1818} 1809}
1819 1810
1820void gk20a_idle(struct platform_device *pdev) 1811void gk20a_idle(struct device *dev)
1821{ 1812{
1822#ifdef CONFIG_PM 1813#ifdef CONFIG_PM
1823 struct gk20a_platform *platform = gk20a_get_platform(pdev); 1814 struct gk20a_platform *platform = gk20a_get_platform(dev);
1824 if (atomic_read(&pdev->dev.power.usage_count) == 1) 1815 if (atomic_read(&dev->power.usage_count) == 1)
1825 gk20a_scale_notify_idle(pdev); 1816 gk20a_scale_notify_idle(dev);
1826 pm_runtime_mark_last_busy(&pdev->dev); 1817 pm_runtime_mark_last_busy(dev);
1827 pm_runtime_put_sync_autosuspend(&pdev->dev); 1818 pm_runtime_put_sync_autosuspend(dev);
1828 1819
1829 if (platform->idle) 1820 if (platform->idle)
1830 platform->idle(pdev); 1821 platform->idle(dev);
1831#else 1822#else
1832 gk20a_scale_notify_idle(pdev); 1823 gk20a_scale_notify_idle(dev);
1833#endif 1824#endif
1834} 1825}
1835 1826
@@ -1882,10 +1873,10 @@ void gk20a_reset(struct gk20a *g, u32 units)
1882 * In success, we hold these locks and return 1873 * In success, we hold these locks and return
1883 * In failure, we release these locks and return 1874 * In failure, we release these locks and return
1884 */ 1875 */
1885int __gk20a_do_idle(struct platform_device *pdev, bool force_reset) 1876int __gk20a_do_idle(struct device *dev, bool force_reset)
1886{ 1877{
1887 struct gk20a *g = get_gk20a(pdev); 1878 struct gk20a *g = get_gk20a(dev);
1888 struct gk20a_platform *platform = dev_get_drvdata(&pdev->dev); 1879 struct gk20a_platform *platform = dev_get_drvdata(dev);
1889 unsigned long timeout = jiffies + 1880 unsigned long timeout = jiffies +
1890 msecs_to_jiffies(GK20A_WAIT_FOR_IDLE_MS); 1881 msecs_to_jiffies(GK20A_WAIT_FOR_IDLE_MS);
1891 int ref_cnt; 1882 int ref_cnt;
@@ -1898,7 +1889,7 @@ int __gk20a_do_idle(struct platform_device *pdev, bool force_reset)
1898 mutex_lock(&platform->railgate_lock); 1889 mutex_lock(&platform->railgate_lock);
1899 1890
1900 /* check if it is already railgated ? */ 1891 /* check if it is already railgated ? */
1901 if (platform->is_railgated(pdev)) 1892 if (platform->is_railgated(dev))
1902 return 0; 1893 return 0;
1903 1894
1904 /* 1895 /*
@@ -1906,17 +1897,17 @@ int __gk20a_do_idle(struct platform_device *pdev, bool force_reset)
1906 * re-acquire railgate_lock 1897 * re-acquire railgate_lock
1907 */ 1898 */
1908 mutex_unlock(&platform->railgate_lock); 1899 mutex_unlock(&platform->railgate_lock);
1909 pm_runtime_get_sync(&pdev->dev); 1900 pm_runtime_get_sync(dev);
1910 mutex_lock(&platform->railgate_lock); 1901 mutex_lock(&platform->railgate_lock);
1911 1902
1912 /* check and wait until GPU is idle (with a timeout) */ 1903 /* check and wait until GPU is idle (with a timeout) */
1913 do { 1904 do {
1914 msleep(1); 1905 msleep(1);
1915 ref_cnt = atomic_read(&pdev->dev.power.usage_count); 1906 ref_cnt = atomic_read(&dev->power.usage_count);
1916 } while (ref_cnt != 1 && time_before(jiffies, timeout)); 1907 } while (ref_cnt != 1 && time_before(jiffies, timeout));
1917 1908
1918 if (ref_cnt != 1) { 1909 if (ref_cnt != 1) {
1919 gk20a_err(&pdev->dev, "failed to idle - refcount %d != 1\n", 1910 gk20a_err(dev, "failed to idle - refcount %d != 1\n",
1920 ref_cnt); 1911 ref_cnt);
1921 goto fail_drop_usage_count; 1912 goto fail_drop_usage_count;
1922 } 1913 }
@@ -1931,7 +1922,7 @@ int __gk20a_do_idle(struct platform_device *pdev, bool force_reset)
1931 * if GPU is now idle, we will have only one ref count, 1922 * if GPU is now idle, we will have only one ref count,
1932 * drop this ref which will rail gate the GPU 1923 * drop this ref which will rail gate the GPU
1933 */ 1924 */
1934 pm_runtime_put_sync(&pdev->dev); 1925 pm_runtime_put_sync(dev);
1935 1926
1936 /* add sufficient delay to allow GPU to rail gate */ 1927 /* add sufficient delay to allow GPU to rail gate */
1937 msleep(platform->railgate_delay); 1928 msleep(platform->railgate_delay);
@@ -1941,13 +1932,13 @@ int __gk20a_do_idle(struct platform_device *pdev, bool force_reset)
1941 /* check in loop if GPU is railgated or not */ 1932 /* check in loop if GPU is railgated or not */
1942 do { 1933 do {
1943 msleep(1); 1934 msleep(1);
1944 is_railgated = platform->is_railgated(pdev); 1935 is_railgated = platform->is_railgated(dev);
1945 } while (!is_railgated && time_before(jiffies, timeout)); 1936 } while (!is_railgated && time_before(jiffies, timeout));
1946 1937
1947 if (is_railgated) { 1938 if (is_railgated) {
1948 return 0; 1939 return 0;
1949 } else { 1940 } else {
1950 gk20a_err(&pdev->dev, "failed to idle in timeout\n"); 1941 gk20a_err(dev, "failed to idle in timeout\n");
1951 goto fail_timeout; 1942 goto fail_timeout;
1952 } 1943 }
1953 } else { 1944 } else {
@@ -1964,12 +1955,12 @@ int __gk20a_do_idle(struct platform_device *pdev, bool force_reset)
1964 */ 1955 */
1965 1956
1966 /* Save the GPU state */ 1957 /* Save the GPU state */
1967 gk20a_pm_prepare_poweroff(&pdev->dev); 1958 gk20a_pm_prepare_poweroff(dev);
1968 1959
1969 gk20a_pm_disable_clk(&pdev->dev); 1960 gk20a_pm_disable_clk(dev);
1970 1961
1971 /* railgate GPU */ 1962 /* railgate GPU */
1972 platform->railgate(pdev); 1963 platform->railgate(dev);
1973 1964
1974 udelay(10); 1965 udelay(10);
1975 1966
@@ -1978,7 +1969,7 @@ int __gk20a_do_idle(struct platform_device *pdev, bool force_reset)
1978 } 1969 }
1979 1970
1980fail_drop_usage_count: 1971fail_drop_usage_count:
1981 pm_runtime_put_noidle(&pdev->dev); 1972 pm_runtime_put_noidle(dev);
1982fail_timeout: 1973fail_timeout:
1983 mutex_unlock(&platform->railgate_lock); 1974 mutex_unlock(&platform->railgate_lock);
1984 up_write(&g->busy_lock); 1975 up_write(&g->busy_lock);
@@ -1997,7 +1988,7 @@ int gk20a_do_idle(void)
1997 of_find_matching_node(NULL, tegra_gk20a_of_match); 1988 of_find_matching_node(NULL, tegra_gk20a_of_match);
1998 struct platform_device *pdev = of_find_device_by_node(node); 1989 struct platform_device *pdev = of_find_device_by_node(node);
1999 1990
2000 int ret = __gk20a_do_idle(pdev, true); 1991 int ret = __gk20a_do_idle(&pdev->dev, true);
2001 1992
2002 of_node_put(node); 1993 of_node_put(node);
2003 1994
@@ -2007,25 +1998,25 @@ int gk20a_do_idle(void)
2007/** 1998/**
2008 * __gk20a_do_unidle() - unblock all the tasks blocked by __gk20a_do_idle() 1999 * __gk20a_do_unidle() - unblock all the tasks blocked by __gk20a_do_idle()
2009 */ 2000 */
2010int __gk20a_do_unidle(struct platform_device *pdev) 2001int __gk20a_do_unidle(struct device *dev)
2011{ 2002{
2012 struct gk20a *g = get_gk20a(pdev); 2003 struct gk20a *g = get_gk20a(dev);
2013 struct gk20a_platform *platform = dev_get_drvdata(&pdev->dev); 2004 struct gk20a_platform *platform = dev_get_drvdata(dev);
2014 2005
2015 if (g->forced_reset) { 2006 if (g->forced_reset) {
2016 /* 2007 /*
2017 * If we did a forced-reset/railgate 2008 * If we did a forced-reset/railgate
2018 * then unrailgate the GPU here first 2009 * then unrailgate the GPU here first
2019 */ 2010 */
2020 platform->unrailgate(pdev); 2011 platform->unrailgate(dev);
2021 2012
2022 gk20a_pm_enable_clk(&pdev->dev); 2013 gk20a_pm_enable_clk(dev);
2023 2014
2024 /* restore the GPU state */ 2015 /* restore the GPU state */
2025 gk20a_pm_finalize_poweron(&pdev->dev); 2016 gk20a_pm_finalize_poweron(dev);
2026 2017
2027 /* balance GPU usage counter */ 2018 /* balance GPU usage counter */
2028 pm_runtime_put_sync(&pdev->dev); 2019 pm_runtime_put_sync(dev);
2029 2020
2030 g->forced_reset = false; 2021 g->forced_reset = false;
2031 } 2022 }
@@ -2046,7 +2037,7 @@ int gk20a_do_unidle(void)
2046 of_find_matching_node(NULL, tegra_gk20a_of_match); 2037 of_find_matching_node(NULL, tegra_gk20a_of_match);
2047 struct platform_device *pdev = of_find_device_by_node(node); 2038 struct platform_device *pdev = of_find_device_by_node(node);
2048 2039
2049 int ret = __gk20a_do_unidle(pdev); 2040 int ret = __gk20a_do_unidle(&pdev->dev);
2050 2041
2051 of_node_put(node); 2042 of_node_put(node);
2052 2043
@@ -2057,7 +2048,7 @@ int gk20a_do_unidle(void)
2057int gk20a_init_gpu_characteristics(struct gk20a *g) 2048int gk20a_init_gpu_characteristics(struct gk20a *g)
2058{ 2049{
2059 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; 2050 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
2060 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 2051 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
2061 2052
2062 gpu->L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g); 2053 gpu->L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g);
2063 gpu->on_board_video_memory_size = 0; /* integrated GPU */ 2054 gpu->on_board_video_memory_size = 0; /* integrated GPU */
@@ -2164,7 +2155,7 @@ do_request_firmware(struct device *dev, const char *prefix, const char *fw_name)
2164const struct firmware * 2155const struct firmware *
2165gk20a_request_firmware(struct gk20a *g, const char *fw_name) 2156gk20a_request_firmware(struct gk20a *g, const char *fw_name)
2166{ 2157{
2167 struct device *dev = &g->dev->dev; 2158 struct device *dev = g->dev;
2168 const struct firmware *fw; 2159 const struct firmware *fw;
2169 2160
2170 /* current->fs is NULL when calling from SYS_EXIT. 2161 /* current->fs is NULL when calling from SYS_EXIT.
@@ -2177,8 +2168,10 @@ gk20a_request_firmware(struct gk20a *g, const char *fw_name)
2177 2168
2178#ifdef CONFIG_TEGRA_GK20A 2169#ifdef CONFIG_TEGRA_GK20A
2179 /* TO BE REMOVED - Support loading from legacy SOC specific path. */ 2170 /* TO BE REMOVED - Support loading from legacy SOC specific path. */
2180 if (!fw) 2171 if (!fw) {
2181 fw = nvhost_client_request_firmware(g->dev, fw_name); 2172 struct gk20a_platform *platform = gk20a_get_platform(dev);
2173 fw = do_request_firmware(dev, platform->soc_name, fw_name);
2174 }
2182#endif 2175#endif
2183 2176
2184 if (!fw) { 2177 if (!fw) {
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 273eeaf4..9d8dc5f7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -18,7 +18,6 @@
18#ifndef GK20A_H 18#ifndef GK20A_H
19#define GK20A_H 19#define GK20A_H
20 20
21
22struct gk20a; 21struct gk20a;
23struct fifo_gk20a; 22struct fifo_gk20a;
24struct channel_gk20a; 23struct channel_gk20a;
@@ -206,7 +205,7 @@ struct gpu_ops {
206 bool *post_event, struct channel_gk20a *fault_ch); 205 bool *post_event, struct channel_gk20a *fault_ch);
207 int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, 206 int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
208 bool *post_event); 207 bool *post_event);
209 void (*create_gr_sysfs)(struct platform_device *dev); 208 void (*create_gr_sysfs)(struct device *dev);
210 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); 209 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
211 } gr; 210 } gr;
212 const char *name; 211 const char *name;
@@ -517,7 +516,7 @@ struct gpu_ops {
517}; 516};
518 517
519struct gk20a { 518struct gk20a {
520 struct platform_device *dev; 519 struct device *dev;
521 struct platform_device *host1x_dev; 520 struct platform_device *host1x_dev;
522 521
523 struct resource *reg_mem; 522 struct resource *reg_mem;
@@ -602,7 +601,7 @@ struct gk20a {
602 */ 601 */
603 u64 separate_fixed_allocs; 602 u64 separate_fixed_allocs;
604 603
605 void (*remove_support)(struct platform_device *); 604 void (*remove_support)(struct device *);
606 605
607 u64 pg_ingating_time_us; 606 u64 pg_ingating_time_us;
608 u64 pg_ungating_time_us; 607 u64 pg_ungating_time_us;
@@ -648,7 +647,6 @@ struct gk20a {
648 int client_refcount; /* open channels and ctrl nodes */ 647 int client_refcount; /* open channels and ctrl nodes */
649 648
650 dev_t cdev_region; 649 dev_t cdev_region;
651 struct class *class;
652 650
653 struct gpu_ops ops; 651 struct gpu_ops ops;
654 652
@@ -685,7 +683,7 @@ static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
685 g->gr_idle_timeout_default : MAX_SCHEDULE_TIMEOUT; 683 g->gr_idle_timeout_default : MAX_SCHEDULE_TIMEOUT;
686} 684}
687 685
688static inline struct gk20a *get_gk20a(struct platform_device *dev) 686static inline struct gk20a *get_gk20a(struct device *dev)
689{ 687{
690 return gk20a_get_platform(dev)->g; 688 return gk20a_get_platform(dev)->g;
691} 689}
@@ -880,7 +878,11 @@ static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b)
880/* convenience */ 878/* convenience */
881static inline struct device *dev_from_gk20a(struct gk20a *g) 879static inline struct device *dev_from_gk20a(struct gk20a *g)
882{ 880{
883 return &g->dev->dev; 881 return g->dev;
882}
883static inline struct gk20a *gk20a_from_dev(struct device *dev)
884{
885 return ((struct gk20a_platform *)dev_get_drvdata(dev))->g;
884} 886}
885static inline struct gk20a *gk20a_from_as(struct gk20a_as *as) 887static inline struct gk20a *gk20a_from_as(struct gk20a_as *as)
886{ 888{
@@ -927,14 +929,14 @@ enum {
927 KEPLER_CHANNEL_GPFIFO_C = 0xA26F, 929 KEPLER_CHANNEL_GPFIFO_C = 0xA26F,
928}; 930};
929 931
930static inline bool gk20a_gpu_is_virtual(struct platform_device *dev) 932static inline bool gk20a_gpu_is_virtual(struct device *dev)
931{ 933{
932 struct gk20a_platform *platform = gk20a_get_platform(dev); 934 struct gk20a_platform *platform = dev_get_drvdata(dev);
933 935
934 return platform->virtual_dev; 936 return platform->virtual_dev;
935} 937}
936 938
937static inline int support_gk20a_pmu(struct platform_device *dev) 939static inline int support_gk20a_pmu(struct device *dev)
938{ 940{
939 if (IS_ENABLED(CONFIG_GK20A_PMU)) { 941 if (IS_ENABLED(CONFIG_GK20A_PMU)) {
940 /* gPMU is not supported for vgpu */ 942 /* gPMU is not supported for vgpu */
@@ -944,23 +946,23 @@ static inline int support_gk20a_pmu(struct platform_device *dev)
944 return 0; 946 return 0;
945} 947}
946 948
947void gk20a_create_sysfs(struct platform_device *dev); 949void gk20a_create_sysfs(struct device *dev);
948void gk20a_remove_sysfs(struct device *dev); 950void gk20a_remove_sysfs(struct device *dev);
949 951
950#define GK20A_BAR0_IORESOURCE_MEM 0 952#define GK20A_BAR0_IORESOURCE_MEM 0
951#define GK20A_BAR1_IORESOURCE_MEM 1 953#define GK20A_BAR1_IORESOURCE_MEM 1
952#define GK20A_SIM_IORESOURCE_MEM 2 954#define GK20A_SIM_IORESOURCE_MEM 2
953 955
954void gk20a_busy_noresume(struct platform_device *pdev); 956void gk20a_busy_noresume(struct device *dev);
955int __must_check gk20a_busy(struct platform_device *pdev); 957int __must_check gk20a_busy(struct device *dev);
956void gk20a_idle(struct platform_device *pdev); 958void gk20a_idle(struct device *dev);
957void gk20a_disable(struct gk20a *g, u32 units); 959void gk20a_disable(struct gk20a *g, u32 units);
958void gk20a_enable(struct gk20a *g, u32 units); 960void gk20a_enable(struct gk20a *g, u32 units);
959void gk20a_reset(struct gk20a *g, u32 units); 961void gk20a_reset(struct gk20a *g, u32 units);
960int gk20a_do_idle(void); 962int gk20a_do_idle(void);
961int gk20a_do_unidle(void); 963int gk20a_do_unidle(void);
962int __gk20a_do_idle(struct platform_device *pdev, bool force_reset); 964int __gk20a_do_idle(struct device *dev, bool force_reset);
963int __gk20a_do_unidle(struct platform_device *pdev); 965int __gk20a_do_unidle(struct device *dev);
964 966
965const struct firmware * 967const struct firmware *
966gk20a_request_firmware(struct gk20a *g, const char *fw_name); 968gk20a_request_firmware(struct gk20a *g, const char *fw_name);
@@ -981,10 +983,10 @@ int gk20a_init_gpu_characteristics(struct gk20a *g);
981 983
982void gk20a_pbus_isr(struct gk20a *g); 984void gk20a_pbus_isr(struct gk20a *g);
983 985
984int gk20a_user_init(struct platform_device *dev); 986int gk20a_user_init(struct device *dev, const char *interface_name);
985void gk20a_user_deinit(struct platform_device *dev); 987void gk20a_user_deinit(struct device *dev);
986 988
987extern void gk20a_debug_dump_device(struct platform_device *pdev); 989void gk20a_debug_dump_device(void *dev);
988 990
989static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) 991static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq)
990{ 992{
@@ -999,4 +1001,8 @@ static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
999} 1001}
1000 1002
1001u64 gk20a_read_ptimer(struct gk20a *g); 1003u64 gk20a_read_ptimer(struct gk20a *g);
1004extern struct class nvgpu_class;
1005
1006#define INTERFACE_NAME "nvhost%s-gpu"
1007
1002#endif /* GK20A_H */ 1008#endif /* GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
index 65772d3b..e5c93db5 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * gk20a clock scaling profile 2 * gk20a clock scaling profile
3 * 3 *
4 * Copyright (c) 2013-2015, NVIDIA Corporation. All rights reserved. 4 * Copyright (c) 2013-2016, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -47,8 +47,8 @@ static int gk20a_scale_qos_notify(struct notifier_block *nb,
47 struct gk20a_scale_profile *profile = 47 struct gk20a_scale_profile *profile =
48 container_of(nb, struct gk20a_scale_profile, 48 container_of(nb, struct gk20a_scale_profile,
49 qos_notify_block); 49 qos_notify_block);
50 struct gk20a_platform *platform = platform_get_drvdata(profile->pdev); 50 struct gk20a_platform *platform = dev_get_drvdata(profile->dev);
51 struct gk20a *g = get_gk20a(profile->pdev); 51 struct gk20a *g = get_gk20a(profile->dev);
52 unsigned long freq; 52 unsigned long freq;
53 53
54 if (!platform->postscale) 54 if (!platform->postscale)
@@ -56,7 +56,7 @@ static int gk20a_scale_qos_notify(struct notifier_block *nb,
56 56
57 /* get the frequency requirement. if devfreq is enabled, check if it 57 /* get the frequency requirement. if devfreq is enabled, check if it
58 * has higher demand than qos */ 58 * has higher demand than qos */
59 freq = platform->clk_round_rate(profile->pdev, 59 freq = platform->clk_round_rate(profile->dev,
60 pm_qos_request(platform->qos_id)); 60 pm_qos_request(platform->qos_id));
61 if (g->devfreq) 61 if (g->devfreq)
62 freq = max(g->devfreq->previous_freq, freq); 62 freq = max(g->devfreq->previous_freq, freq);
@@ -64,7 +64,7 @@ static int gk20a_scale_qos_notify(struct notifier_block *nb,
64 /* Update gpu load because we may scale the emc target 64 /* Update gpu load because we may scale the emc target
65 * if the gpu load changed. */ 65 * if the gpu load changed. */
66 gk20a_pmu_load_update(g); 66 gk20a_pmu_load_update(g);
67 platform->postscale(profile->pdev, freq); 67 platform->postscale(profile->dev, freq);
68 68
69 return NOTIFY_OK; 69 return NOTIFY_OK;
70} 70}
@@ -77,12 +77,12 @@ static int gk20a_scale_qos_notify(struct notifier_block *nb,
77 77
78static int gk20a_scale_make_freq_table(struct gk20a_scale_profile *profile) 78static int gk20a_scale_make_freq_table(struct gk20a_scale_profile *profile)
79{ 79{
80 struct gk20a_platform *platform = platform_get_drvdata(profile->pdev); 80 struct gk20a_platform *platform = dev_get_drvdata(profile->dev);
81 int num_freqs, err; 81 int num_freqs, err;
82 unsigned long *freqs; 82 unsigned long *freqs;
83 83
84 /* get gpu frequency table */ 84 /* get gpu frequency table */
85 err = platform->get_clk_freqs(profile->pdev, &freqs, 85 err = platform->get_clk_freqs(profile->dev, &freqs,
86 &num_freqs); 86 &num_freqs);
87 if (err) 87 if (err)
88 return -ENOSYS; 88 return -ENOSYS;
@@ -103,22 +103,21 @@ static int gk20a_scale_target(struct device *dev, unsigned long *freq,
103 u32 flags) 103 u32 flags)
104{ 104{
105 struct gk20a_platform *platform = dev_get_drvdata(dev); 105 struct gk20a_platform *platform = dev_get_drvdata(dev);
106 struct platform_device *pdev = to_platform_device(dev);
107 unsigned long rounded_rate = 106 unsigned long rounded_rate =
108 platform->clk_round_rate(pdev, *freq); 107 platform->clk_round_rate(dev, *freq);
109 108
110 if (platform->clk_get_rate(pdev) == rounded_rate) 109 if (platform->clk_get_rate(dev) == rounded_rate)
111 *freq = rounded_rate; 110 *freq = rounded_rate;
112 else { 111 else {
113 platform->clk_set_rate(pdev, rounded_rate); 112 platform->clk_set_rate(dev, rounded_rate);
114 *freq = platform->clk_get_rate(pdev); 113 *freq = platform->clk_get_rate(dev);
115 } 114 }
116 115
117 /* postscale will only scale emc (dram clock) if evaluating 116 /* postscale will only scale emc (dram clock) if evaluating
118 * gk20a_tegra_get_emc_rate() produces a new or different emc 117 * gk20a_tegra_get_emc_rate() produces a new or different emc
119 * target because the load or_and gpufreq has changed */ 118 * target because the load or_and gpufreq has changed */
120 if (platform->postscale) 119 if (platform->postscale)
121 platform->postscale(pdev, rounded_rate); 120 platform->postscale(dev, rounded_rate);
122 121
123 return 0; 122 return 0;
124} 123}
@@ -130,9 +129,9 @@ static int gk20a_scale_target(struct device *dev, unsigned long *freq,
130 * based on the time it was asked last time. 129 * based on the time it was asked last time.
131 */ 130 */
132 131
133static void update_load_estimate_gpmu(struct platform_device *pdev) 132static void update_load_estimate_gpmu(struct device *dev)
134{ 133{
135 struct gk20a *g = get_gk20a(pdev); 134 struct gk20a *g = get_gk20a(dev);
136 struct gk20a_scale_profile *profile = g->scale_profile; 135 struct gk20a_scale_profile *profile = g->scale_profile;
137 unsigned long dt; 136 unsigned long dt;
138 u32 busy_time; 137 u32 busy_time;
@@ -148,14 +147,14 @@ static void update_load_estimate_gpmu(struct platform_device *pdev)
148} 147}
149 148
150/* 149/*
151 * gk20a_scale_suspend(pdev) 150 * gk20a_scale_suspend(dev)
152 * 151 *
153 * This function informs devfreq of suspend 152 * This function informs devfreq of suspend
154 */ 153 */
155 154
156void gk20a_scale_suspend(struct platform_device *pdev) 155void gk20a_scale_suspend(struct device *dev)
157{ 156{
158 struct gk20a *g = get_gk20a(pdev); 157 struct gk20a *g = get_gk20a(dev);
159 struct devfreq *devfreq = g->devfreq; 158 struct devfreq *devfreq = g->devfreq;
160 159
161 if (!devfreq) 160 if (!devfreq)
@@ -165,14 +164,14 @@ void gk20a_scale_suspend(struct platform_device *pdev)
165} 164}
166 165
167/* 166/*
168 * gk20a_scale_resume(pdev) 167 * gk20a_scale_resume(dev)
169 * 168 *
170 * This functions informs devfreq of resume 169 * This functions informs devfreq of resume
171 */ 170 */
172 171
173void gk20a_scale_resume(struct platform_device *pdev) 172void gk20a_scale_resume(struct device *dev)
174{ 173{
175 struct gk20a *g = get_gk20a(pdev); 174 struct gk20a *g = get_gk20a(dev);
176 struct devfreq *devfreq = g->devfreq; 175 struct devfreq *devfreq = g->devfreq;
177 176
178 if (!devfreq) 177 if (!devfreq)
@@ -182,15 +181,15 @@ void gk20a_scale_resume(struct platform_device *pdev)
182} 181}
183 182
184/* 183/*
185 * gk20a_scale_notify(pdev, busy) 184 * gk20a_scale_notify(dev, busy)
186 * 185 *
187 * Calling this function informs that the device is idling (..or busy). This 186 * Calling this function informs that the device is idling (..or busy). This
188 * data is used to estimate the current load 187 * data is used to estimate the current load
189 */ 188 */
190 189
191static void gk20a_scale_notify(struct platform_device *pdev, bool busy) 190static void gk20a_scale_notify(struct device *dev, bool busy)
192{ 191{
193 struct gk20a *g = get_gk20a(pdev); 192 struct gk20a *g = get_gk20a(dev);
194 struct gk20a_scale_profile *profile = g->scale_profile; 193 struct gk20a_scale_profile *profile = g->scale_profile;
195 struct devfreq *devfreq = g->devfreq; 194 struct devfreq *devfreq = g->devfreq;
196 195
@@ -204,15 +203,15 @@ static void gk20a_scale_notify(struct platform_device *pdev, bool busy)
204 mutex_unlock(&devfreq->lock); 203 mutex_unlock(&devfreq->lock);
205} 204}
206 205
207void gk20a_scale_notify_idle(struct platform_device *pdev) 206void gk20a_scale_notify_idle(struct device *dev)
208{ 207{
209 gk20a_scale_notify(pdev, false); 208 gk20a_scale_notify(dev, false);
210 209
211} 210}
212 211
213void gk20a_scale_notify_busy(struct platform_device *pdev) 212void gk20a_scale_notify_busy(struct device *dev)
214{ 213{
215 gk20a_scale_notify(pdev, true); 214 gk20a_scale_notify(dev, true);
216} 215}
217 216
218/* 217/*
@@ -224,24 +223,23 @@ void gk20a_scale_notify_busy(struct platform_device *pdev)
224static int gk20a_scale_get_dev_status(struct device *dev, 223static int gk20a_scale_get_dev_status(struct device *dev,
225 struct devfreq_dev_status *stat) 224 struct devfreq_dev_status *stat)
226{ 225{
227 struct gk20a *g = get_gk20a(to_platform_device(dev)); 226 struct gk20a *g = get_gk20a(dev);
228 struct gk20a_scale_profile *profile = g->scale_profile; 227 struct gk20a_scale_profile *profile = g->scale_profile;
229 struct platform_device *pdev = to_platform_device(dev); 228 struct gk20a_platform *platform = dev_get_drvdata(dev);
230 struct gk20a_platform *platform = platform_get_drvdata(pdev);
231 229
232 /* update the software shadow */ 230 /* update the software shadow */
233 gk20a_pmu_load_update(g); 231 gk20a_pmu_load_update(g);
234 232
235 /* inform edp about new constraint */ 233 /* inform edp about new constraint */
236 if (platform->prescale) 234 if (platform->prescale)
237 platform->prescale(pdev); 235 platform->prescale(dev);
238 236
239 /* Make sure there are correct values for the current frequency */ 237 /* Make sure there are correct values for the current frequency */
240 profile->dev_stat.current_frequency = 238 profile->dev_stat.current_frequency =
241 platform->clk_get_rate(profile->pdev); 239 platform->clk_get_rate(profile->dev);
242 240
243 /* Update load estimate */ 241 /* Update load estimate */
244 update_load_estimate_gpmu(to_platform_device(dev)); 242 update_load_estimate_gpmu(dev);
245 243
246 /* Copy the contents of the current device status */ 244 /* Copy the contents of the current device status */
247 *stat = profile->dev_stat; 245 *stat = profile->dev_stat;
@@ -254,12 +252,12 @@ static int gk20a_scale_get_dev_status(struct device *dev,
254} 252}
255 253
256/* 254/*
257 * gk20a_scale_init(pdev) 255 * gk20a_scale_init(dev)
258 */ 256 */
259 257
260void gk20a_scale_init(struct platform_device *pdev) 258void gk20a_scale_init(struct device *dev)
261{ 259{
262 struct gk20a_platform *platform = platform_get_drvdata(pdev); 260 struct gk20a_platform *platform = dev_get_drvdata(dev);
263 struct gk20a *g = platform->g; 261 struct gk20a *g = platform->g;
264 struct gk20a_scale_profile *profile; 262 struct gk20a_scale_profile *profile;
265 int err; 263 int err;
@@ -269,7 +267,7 @@ void gk20a_scale_init(struct platform_device *pdev)
269 267
270 profile = kzalloc(sizeof(*profile), GFP_KERNEL); 268 profile = kzalloc(sizeof(*profile), GFP_KERNEL);
271 269
272 profile->pdev = pdev; 270 profile->dev = dev;
273 profile->dev_stat.busy = false; 271 profile->dev_stat.busy = false;
274 272
275 /* Create frequency table */ 273 /* Create frequency table */
@@ -290,7 +288,7 @@ void gk20a_scale_init(struct platform_device *pdev)
290 profile->devfreq_profile.get_dev_status = 288 profile->devfreq_profile.get_dev_status =
291 gk20a_scale_get_dev_status; 289 gk20a_scale_get_dev_status;
292 290
293 devfreq = devfreq_add_device(&pdev->dev, 291 devfreq = devfreq_add_device(dev,
294 &profile->devfreq_profile, 292 &profile->devfreq_profile,
295 platform->devfreq_governor, NULL); 293 platform->devfreq_governor, NULL);
296 294
@@ -316,9 +314,9 @@ err_get_freqs:
316 kfree(profile); 314 kfree(profile);
317} 315}
318 316
319void gk20a_scale_exit(struct platform_device *pdev) 317void gk20a_scale_exit(struct device *dev)
320{ 318{
321 struct gk20a_platform *platform = platform_get_drvdata(pdev); 319 struct gk20a_platform *platform = dev_get_drvdata(dev);
322 struct gk20a *g = platform->g; 320 struct gk20a *g = platform->g;
323 int err; 321 int err;
324 322
@@ -344,9 +342,9 @@ void gk20a_scale_exit(struct platform_device *pdev)
344 * Initialize hardware portion of the device 342 * Initialize hardware portion of the device
345 */ 343 */
346 344
347void gk20a_scale_hw_init(struct platform_device *pdev) 345void gk20a_scale_hw_init(struct device *dev)
348{ 346{
349 struct gk20a_platform *platform = platform_get_drvdata(pdev); 347 struct gk20a_platform *platform = dev_get_drvdata(dev);
350 struct gk20a_scale_profile *profile = platform->g->scale_profile; 348 struct gk20a_scale_profile *profile = platform->g->scale_profile;
351 349
352 /* make sure that scaling has bee initialised */ 350 /* make sure that scaling has bee initialised */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_scale.h b/drivers/gpu/nvgpu/gk20a/gk20a_scale.h
index 889a3973..5c8618eb 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_scale.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_scale.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * gk20a clock scaling profile 2 * gk20a clock scaling profile
3 * 3 *
4 * Copyright (c) 2013-2015, NVIDIA Corporation. All rights reserved. 4 * Copyright (c) 2013-2016, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -21,11 +21,10 @@
21 21
22#include <linux/devfreq.h> 22#include <linux/devfreq.h>
23 23
24struct platform_device;
25struct clk; 24struct clk;
26 25
27struct gk20a_scale_profile { 26struct gk20a_scale_profile {
28 struct platform_device *pdev; 27 struct device *dev;
29 ktime_t last_event_time; 28 ktime_t last_event_time;
30 struct devfreq_dev_profile devfreq_profile; 29 struct devfreq_dev_profile devfreq_profile;
31 struct devfreq_dev_status dev_stat; 30 struct devfreq_dev_status dev_stat;
@@ -34,25 +33,25 @@ struct gk20a_scale_profile {
34}; 33};
35 34
36/* Initialization and de-initialization for module */ 35/* Initialization and de-initialization for module */
37void gk20a_scale_init(struct platform_device *); 36void gk20a_scale_init(struct device *);
38void gk20a_scale_exit(struct platform_device *); 37void gk20a_scale_exit(struct device *);
39void gk20a_scale_hw_init(struct platform_device *pdev); 38void gk20a_scale_hw_init(struct device *dev);
40 39
41#if defined(CONFIG_GK20A_DEVFREQ) 40#if defined(CONFIG_GK20A_DEVFREQ)
42/* 41/*
43 * call when performing submit to notify scaling mechanism that the module is 42 * call when performing submit to notify scaling mechanism that the module is
44 * in use 43 * in use
45 */ 44 */
46void gk20a_scale_notify_busy(struct platform_device *); 45void gk20a_scale_notify_busy(struct device *);
47void gk20a_scale_notify_idle(struct platform_device *); 46void gk20a_scale_notify_idle(struct device *);
48 47
49void gk20a_scale_suspend(struct platform_device *); 48void gk20a_scale_suspend(struct device *);
50void gk20a_scale_resume(struct platform_device *); 49void gk20a_scale_resume(struct device *);
51#else 50#else
52static inline void gk20a_scale_notify_busy(struct platform_device *pdev) {} 51static inline void gk20a_scale_notify_busy(struct device *dev) {}
53static inline void gk20a_scale_notify_idle(struct platform_device *pdev) {} 52static inline void gk20a_scale_notify_idle(struct device *dev) {}
54static inline void gk20a_scale_suspend(struct platform_device *pdev) {} 53static inline void gk20a_scale_suspend(struct device *dev) {}
55static inline void gk20a_scale_resume(struct platform_device *pdev) {} 54static inline void gk20a_scale_resume(struct device *dev) {}
56#endif 55#endif
57 56
58#endif 57#endif
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
index d433c9bb..9d25cfdd 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
@@ -18,7 +18,7 @@
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */ 19 */
20 20
21#include <linux/platform_device.h> 21#include <linux/device.h>
22#include <linux/pm_runtime.h> 22#include <linux/pm_runtime.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/fb.h> 24#include <linux/fb.h>
@@ -34,11 +34,10 @@
34 34
35#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) 35#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
36 36
37static ssize_t elcg_enable_store(struct device *device, 37static ssize_t elcg_enable_store(struct device *dev,
38 struct device_attribute *attr, const char *buf, size_t count) 38 struct device_attribute *attr, const char *buf, size_t count)
39{ 39{
40 struct platform_device *ndev = to_platform_device(device); 40 struct gk20a *g = get_gk20a(dev);
41 struct gk20a *g = get_gk20a(ndev);
42 unsigned long val = 0; 41 unsigned long val = 0;
43 int err; 42 int err;
44 43
@@ -60,28 +59,26 @@ static ssize_t elcg_enable_store(struct device *device,
60 } 59 }
61 gk20a_idle(g->dev); 60 gk20a_idle(g->dev);
62 61
63 dev_info(device, "ELCG is %s.\n", g->elcg_enabled ? "enabled" : 62 dev_info(dev, "ELCG is %s.\n", g->elcg_enabled ? "enabled" :
64 "disabled"); 63 "disabled");
65 64
66 return count; 65 return count;
67} 66}
68 67
69static ssize_t elcg_enable_read(struct device *device, 68static ssize_t elcg_enable_read(struct device *dev,
70 struct device_attribute *attr, char *buf) 69 struct device_attribute *attr, char *buf)
71{ 70{
72 struct platform_device *ndev = to_platform_device(device); 71 struct gk20a *g = get_gk20a(dev);
73 struct gk20a *g = get_gk20a(ndev);
74 72
75 return sprintf(buf, "%d\n", g->elcg_enabled ? 1 : 0); 73 return sprintf(buf, "%d\n", g->elcg_enabled ? 1 : 0);
76} 74}
77 75
78static DEVICE_ATTR(elcg_enable, ROOTRW, elcg_enable_read, elcg_enable_store); 76static DEVICE_ATTR(elcg_enable, ROOTRW, elcg_enable_read, elcg_enable_store);
79 77
80static ssize_t blcg_enable_store(struct device *device, 78static ssize_t blcg_enable_store(struct device *dev,
81 struct device_attribute *attr, const char *buf, size_t count) 79 struct device_attribute *attr, const char *buf, size_t count)
82{ 80{
83 struct platform_device *ndev = to_platform_device(device); 81 struct gk20a *g = get_gk20a(dev);
84 struct gk20a *g = get_gk20a(ndev);
85 unsigned long val = 0; 82 unsigned long val = 0;
86 int err; 83 int err;
87 84
@@ -118,17 +115,16 @@ static ssize_t blcg_enable_store(struct device *device,
118 g->blcg_enabled); 115 g->blcg_enabled);
119 gk20a_idle(g->dev); 116 gk20a_idle(g->dev);
120 117
121 dev_info(device, "BLCG is %s.\n", g->blcg_enabled ? "enabled" : 118 dev_info(dev, "BLCG is %s.\n", g->blcg_enabled ? "enabled" :
122 "disabled"); 119 "disabled");
123 120
124 return count; 121 return count;
125} 122}
126 123
127static ssize_t blcg_enable_read(struct device *device, 124static ssize_t blcg_enable_read(struct device *dev,
128 struct device_attribute *attr, char *buf) 125 struct device_attribute *attr, char *buf)
129{ 126{
130 struct platform_device *ndev = to_platform_device(device); 127 struct gk20a *g = get_gk20a(dev);
131 struct gk20a *g = get_gk20a(ndev);
132 128
133 return sprintf(buf, "%d\n", g->blcg_enabled ? 1 : 0); 129 return sprintf(buf, "%d\n", g->blcg_enabled ? 1 : 0);
134} 130}
@@ -136,11 +132,10 @@ static ssize_t blcg_enable_read(struct device *device,
136 132
137static DEVICE_ATTR(blcg_enable, ROOTRW, blcg_enable_read, blcg_enable_store); 133static DEVICE_ATTR(blcg_enable, ROOTRW, blcg_enable_read, blcg_enable_store);
138 134
139static ssize_t slcg_enable_store(struct device *device, 135static ssize_t slcg_enable_store(struct device *dev,
140 struct device_attribute *attr, const char *buf, size_t count) 136 struct device_attribute *attr, const char *buf, size_t count)
141{ 137{
142 struct platform_device *ndev = to_platform_device(device); 138 struct gk20a *g = get_gk20a(dev);
143 struct gk20a *g = get_gk20a(ndev);
144 unsigned long val = 0; 139 unsigned long val = 0;
145 int err; 140 int err;
146 141
@@ -185,17 +180,16 @@ static ssize_t slcg_enable_store(struct device *device,
185 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, g->slcg_enabled); 180 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, g->slcg_enabled);
186 gk20a_idle(g->dev); 181 gk20a_idle(g->dev);
187 182
188 dev_info(device, "SLCG is %s.\n", g->slcg_enabled ? "enabled" : 183 dev_info(dev, "SLCG is %s.\n", g->slcg_enabled ? "enabled" :
189 "disabled"); 184 "disabled");
190 185
191 return count; 186 return count;
192} 187}
193 188
194static ssize_t slcg_enable_read(struct device *device, 189static ssize_t slcg_enable_read(struct device *dev,
195 struct device_attribute *attr, char *buf) 190 struct device_attribute *attr, char *buf)
196{ 191{
197 struct platform_device *ndev = to_platform_device(device); 192 struct gk20a *g = get_gk20a(dev);
198 struct gk20a *g = get_gk20a(ndev);
199 193
200 return sprintf(buf, "%d\n", g->slcg_enabled ? 1 : 0); 194 return sprintf(buf, "%d\n", g->slcg_enabled ? 1 : 0);
201} 195}
@@ -203,8 +197,8 @@ static ssize_t slcg_enable_read(struct device *device,
203static DEVICE_ATTR(slcg_enable, ROOTRW, slcg_enable_read, slcg_enable_store); 197static DEVICE_ATTR(slcg_enable, ROOTRW, slcg_enable_read, slcg_enable_store);
204 198
205static ssize_t ptimer_scale_factor_show(struct device *dev, 199static ssize_t ptimer_scale_factor_show(struct device *dev,
206 struct device_attribute *attr, 200 struct device_attribute *attr,
207 char *buf) 201 char *buf)
208{ 202{
209 struct gk20a_platform *platform = dev_get_drvdata(dev); 203 struct gk20a_platform *platform = dev_get_drvdata(dev);
210 u32 src_freq_hz = platform->ptimer_src_freq; 204 u32 src_freq_hz = platform->ptimer_src_freq;
@@ -240,8 +234,7 @@ static ssize_t railgate_enable_store(struct device *dev,
240{ 234{
241 struct gk20a_platform *platform = dev_get_drvdata(dev); 235 struct gk20a_platform *platform = dev_get_drvdata(dev);
242 struct generic_pm_domain *genpd = dev_to_genpd(dev); 236 struct generic_pm_domain *genpd = dev_to_genpd(dev);
243 struct platform_device *ndev = to_platform_device(dev); 237 struct gk20a *g = get_gk20a(dev);
244 struct gk20a *g = get_gk20a(ndev);
245 unsigned long railgate_enable = 0; 238 unsigned long railgate_enable = 0;
246 int err; 239 int err;
247 240
@@ -255,7 +248,7 @@ static ssize_t railgate_enable_store(struct device *dev,
255 /* release extra ref count:if power domains not enabled */ 248 /* release extra ref count:if power domains not enabled */
256 if ((platform->railgate) && \ 249 if ((platform->railgate) && \
257 !IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) 250 !IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
258 err = platform->railgate(ndev); 251 err = platform->railgate(dev);
259 mutex_unlock(&platform->railgate_lock); 252 mutex_unlock(&platform->railgate_lock);
260 } else if (railgate_enable == 0 && platform->can_railgate) { 253 } else if (railgate_enable == 0 && platform->can_railgate) {
261 mutex_lock(&platform->railgate_lock); 254 mutex_lock(&platform->railgate_lock);
@@ -265,7 +258,7 @@ static ssize_t railgate_enable_store(struct device *dev,
265 /* take extra ref count - incase of power domains not enabled */ 258 /* take extra ref count - incase of power domains not enabled */
266 if ((platform->unrailgate) && \ 259 if ((platform->unrailgate) && \
267 !IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) 260 !IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
268 err = platform->unrailgate(ndev); 261 err = platform->unrailgate(dev);
269 mutex_unlock(&platform->railgate_lock); 262 mutex_unlock(&platform->railgate_lock);
270 } 263 }
271 dev_info(dev, "railgate is %s.\n", platform->can_railgate ? 264 dev_info(dev, "railgate is %s.\n", platform->can_railgate ?
@@ -279,11 +272,10 @@ static ssize_t railgate_enable_store(struct device *dev,
279 return count; 272 return count;
280} 273}
281 274
282static ssize_t railgate_enable_read(struct device *device, 275static ssize_t railgate_enable_read(struct device *dev,
283 struct device_attribute *attr, char *buf) 276 struct device_attribute *attr, char *buf)
284{ 277{
285 struct platform_device *ndev = to_platform_device(device); 278 struct gk20a_platform *platform = dev_get_drvdata(dev);
286 struct gk20a_platform *platform = dev_get_drvdata(&ndev->dev);
287 279
288 return sprintf(buf, "%d\n", platform->can_railgate ? 1 : 0); 280 return sprintf(buf, "%d\n", platform->can_railgate ? 1 : 0);
289} 281}
@@ -297,9 +289,8 @@ static ssize_t railgate_delay_store(struct device *dev,
297 const char *buf, size_t count) 289 const char *buf, size_t count)
298{ 290{
299 struct gk20a_platform *platform = dev_get_drvdata(dev); 291 struct gk20a_platform *platform = dev_get_drvdata(dev);
300 struct platform_device *ndev = to_platform_device(dev);
301 int railgate_delay = 0, ret = 0; 292 int railgate_delay = 0, ret = 0;
302 struct gk20a *g = get_gk20a(ndev); 293 struct gk20a *g = get_gk20a(dev);
303 int err; 294 int err;
304 295
305 if (!platform->can_railgate) { 296 if (!platform->can_railgate) {
@@ -373,8 +364,7 @@ static DEVICE_ATTR(clockgate_delay, ROOTRW, clockgate_delay_show,
373static ssize_t counters_show(struct device *dev, 364static ssize_t counters_show(struct device *dev,
374 struct device_attribute *attr, char *buf) 365 struct device_attribute *attr, char *buf)
375{ 366{
376 struct platform_device *pdev = to_platform_device(dev); 367 struct gk20a *g = get_gk20a(dev);
377 struct gk20a *g = get_gk20a(pdev);
378 u32 busy_cycles, total_cycles; 368 u32 busy_cycles, total_cycles;
379 ssize_t res; 369 ssize_t res;
380 370
@@ -390,8 +380,7 @@ static ssize_t counters_show_reset(struct device *dev,
390 struct device_attribute *attr, char *buf) 380 struct device_attribute *attr, char *buf)
391{ 381{
392 ssize_t res = counters_show(dev, attr, buf); 382 ssize_t res = counters_show(dev, attr, buf);
393 struct platform_device *pdev = to_platform_device(dev); 383 struct gk20a *g = get_gk20a(dev);
394 struct gk20a *g = get_gk20a(pdev);
395 384
396 gk20a_pmu_reset_load_counters(g); 385 gk20a_pmu_reset_load_counters(g);
397 386
@@ -403,8 +392,7 @@ static ssize_t gk20a_load_show(struct device *dev,
403 struct device_attribute *attr, 392 struct device_attribute *attr,
404 char *buf) 393 char *buf)
405{ 394{
406 struct platform_device *pdev = to_platform_device(dev); 395 struct gk20a *g = get_gk20a(dev);
407 struct gk20a *g = get_gk20a(pdev);
408 u32 busy_time; 396 u32 busy_time;
409 ssize_t res; 397 ssize_t res;
410 int err; 398 int err;
@@ -427,11 +415,10 @@ static ssize_t gk20a_load_show(struct device *dev,
427} 415}
428static DEVICE_ATTR(load, S_IRUGO, gk20a_load_show, NULL); 416static DEVICE_ATTR(load, S_IRUGO, gk20a_load_show, NULL);
429 417
430static ssize_t elpg_enable_store(struct device *device, 418static ssize_t elpg_enable_store(struct device *dev,
431 struct device_attribute *attr, const char *buf, size_t count) 419 struct device_attribute *attr, const char *buf, size_t count)
432{ 420{
433 struct platform_device *ndev = to_platform_device(device); 421 struct gk20a *g = get_gk20a(dev);
434 struct gk20a *g = get_gk20a(ndev);
435 unsigned long val = 0; 422 unsigned long val = 0;
436 int err; 423 int err;
437 424
@@ -455,28 +442,26 @@ static ssize_t elpg_enable_store(struct device *device,
455 } 442 }
456 gk20a_idle(g->dev); 443 gk20a_idle(g->dev);
457 444
458 dev_info(device, "ELPG is %s.\n", g->elpg_enabled ? "enabled" : 445 dev_info(dev, "ELPG is %s.\n", g->elpg_enabled ? "enabled" :
459 "disabled"); 446 "disabled");
460 447
461 return count; 448 return count;
462} 449}
463 450
464static ssize_t elpg_enable_read(struct device *device, 451static ssize_t elpg_enable_read(struct device *dev,
465 struct device_attribute *attr, char *buf) 452 struct device_attribute *attr, char *buf)
466{ 453{
467 struct platform_device *ndev = to_platform_device(device); 454 struct gk20a *g = get_gk20a(dev);
468 struct gk20a *g = get_gk20a(ndev);
469 455
470 return sprintf(buf, "%d\n", g->elpg_enabled ? 1 : 0); 456 return sprintf(buf, "%d\n", g->elpg_enabled ? 1 : 0);
471} 457}
472 458
473static DEVICE_ATTR(elpg_enable, ROOTRW, elpg_enable_read, elpg_enable_store); 459static DEVICE_ATTR(elpg_enable, ROOTRW, elpg_enable_read, elpg_enable_store);
474 460
475static ssize_t aelpg_param_store(struct device *device, 461static ssize_t aelpg_param_store(struct device *dev,
476 struct device_attribute *attr, const char *buf, size_t count) 462 struct device_attribute *attr, const char *buf, size_t count)
477{ 463{
478 struct platform_device *ndev = to_platform_device(device); 464 struct gk20a *g = get_gk20a(dev);
479 struct gk20a *g = get_gk20a(ndev);
480 int status = 0; 465 int status = 0;
481 union pmu_ap_cmd ap_cmd; 466 union pmu_ap_cmd ap_cmd;
482 int *paramlist = (int *)g->pmu.aelpg_param; 467 int *paramlist = (int *)g->pmu.aelpg_param;
@@ -514,11 +499,10 @@ static ssize_t aelpg_param_store(struct device *device,
514 return count; 499 return count;
515} 500}
516 501
517static ssize_t aelpg_param_read(struct device *device, 502static ssize_t aelpg_param_read(struct device *dev,
518 struct device_attribute *attr, char *buf) 503 struct device_attribute *attr, char *buf)
519{ 504{
520 struct platform_device *ndev = to_platform_device(device); 505 struct gk20a *g = get_gk20a(dev);
521 struct gk20a *g = get_gk20a(ndev);
522 506
523 return sprintf(buf, "%d %d %d %d %d\n", g->pmu.aelpg_param[0], 507 return sprintf(buf, "%d %d %d %d %d\n", g->pmu.aelpg_param[0],
524 g->pmu.aelpg_param[1], g->pmu.aelpg_param[2], 508 g->pmu.aelpg_param[1], g->pmu.aelpg_param[2],
@@ -528,11 +512,10 @@ static ssize_t aelpg_param_read(struct device *device,
528static DEVICE_ATTR(aelpg_param, ROOTRW, 512static DEVICE_ATTR(aelpg_param, ROOTRW,
529 aelpg_param_read, aelpg_param_store); 513 aelpg_param_read, aelpg_param_store);
530 514
531static ssize_t aelpg_enable_store(struct device *device, 515static ssize_t aelpg_enable_store(struct device *dev,
532 struct device_attribute *attr, const char *buf, size_t count) 516 struct device_attribute *attr, const char *buf, size_t count)
533{ 517{
534 struct platform_device *ndev = to_platform_device(device); 518 struct gk20a *g = get_gk20a(dev);
535 struct gk20a *g = get_gk20a(ndev);
536 unsigned long val = 0; 519 unsigned long val = 0;
537 int status = 0; 520 int status = 0;
538 union pmu_ap_cmd ap_cmd; 521 union pmu_ap_cmd ap_cmd;
@@ -558,21 +541,20 @@ static ssize_t aelpg_enable_store(struct device *device,
558 status = gk20a_pmu_ap_send_command(g, &ap_cmd, false); 541 status = gk20a_pmu_ap_send_command(g, &ap_cmd, false);
559 } 542 }
560 } else { 543 } else {
561 dev_info(device, "PMU is not ready, AELPG request failed\n"); 544 dev_info(dev, "PMU is not ready, AELPG request failed\n");
562 } 545 }
563 gk20a_idle(g->dev); 546 gk20a_idle(g->dev);
564 547
565 dev_info(device, "AELPG is %s.\n", g->aelpg_enabled ? "enabled" : 548 dev_info(dev, "AELPG is %s.\n", g->aelpg_enabled ? "enabled" :
566 "disabled"); 549 "disabled");
567 550
568 return count; 551 return count;
569} 552}
570 553
571static ssize_t aelpg_enable_read(struct device *device, 554static ssize_t aelpg_enable_read(struct device *dev,
572 struct device_attribute *attr, char *buf) 555 struct device_attribute *attr, char *buf)
573{ 556{
574 struct platform_device *ndev = to_platform_device(device); 557 struct gk20a *g = get_gk20a(dev);
575 struct gk20a *g = get_gk20a(ndev);
576 558
577 return sprintf(buf, "%d\n", g->aelpg_enabled ? 1 : 0); 559 return sprintf(buf, "%d\n", g->aelpg_enabled ? 1 : 0);
578} 560}
@@ -581,19 +563,17 @@ static DEVICE_ATTR(aelpg_enable, ROOTRW,
581 aelpg_enable_read, aelpg_enable_store); 563 aelpg_enable_read, aelpg_enable_store);
582 564
583 565
584static ssize_t allow_all_enable_read(struct device *device, 566static ssize_t allow_all_enable_read(struct device *dev,
585 struct device_attribute *attr, char *buf) 567 struct device_attribute *attr, char *buf)
586{ 568{
587 struct platform_device *ndev = to_platform_device(device); 569 struct gk20a *g = get_gk20a(dev);
588 struct gk20a *g = get_gk20a(ndev);
589 return sprintf(buf, "%d\n", g->allow_all ? 1 : 0); 570 return sprintf(buf, "%d\n", g->allow_all ? 1 : 0);
590} 571}
591 572
592static ssize_t allow_all_enable_store(struct device *device, 573static ssize_t allow_all_enable_store(struct device *dev,
593 struct device_attribute *attr, const char *buf, size_t count) 574 struct device_attribute *attr, const char *buf, size_t count)
594{ 575{
595 struct platform_device *ndev = to_platform_device(device); 576 struct gk20a *g = get_gk20a(dev);
596 struct gk20a *g = get_gk20a(ndev);
597 unsigned long val = 0; 577 unsigned long val = 0;
598 int err; 578 int err;
599 579
@@ -610,11 +590,10 @@ static ssize_t allow_all_enable_store(struct device *device,
610static DEVICE_ATTR(allow_all, ROOTRW, 590static DEVICE_ATTR(allow_all, ROOTRW,
611 allow_all_enable_read, allow_all_enable_store); 591 allow_all_enable_read, allow_all_enable_store);
612 592
613static ssize_t emc3d_ratio_store(struct device *device, 593static ssize_t emc3d_ratio_store(struct device *dev,
614 struct device_attribute *attr, const char *buf, size_t count) 594 struct device_attribute *attr, const char *buf, size_t count)
615{ 595{
616 struct platform_device *ndev = to_platform_device(device); 596 struct gk20a *g = get_gk20a(dev);
617 struct gk20a *g = get_gk20a(ndev);
618 unsigned long val = 0; 597 unsigned long val = 0;
619 598
620 if (kstrtoul(buf, 10, &val) < 0) 599 if (kstrtoul(buf, 10, &val) < 0)
@@ -625,22 +604,20 @@ static ssize_t emc3d_ratio_store(struct device *device,
625 return count; 604 return count;
626} 605}
627 606
628static ssize_t emc3d_ratio_read(struct device *device, 607static ssize_t emc3d_ratio_read(struct device *dev,
629 struct device_attribute *attr, char *buf) 608 struct device_attribute *attr, char *buf)
630{ 609{
631 struct platform_device *ndev = to_platform_device(device); 610 struct gk20a *g = get_gk20a(dev);
632 struct gk20a *g = get_gk20a(ndev);
633 611
634 return sprintf(buf, "%d\n", g->emc3d_ratio); 612 return sprintf(buf, "%d\n", g->emc3d_ratio);
635} 613}
636 614
637static DEVICE_ATTR(emc3d_ratio, ROOTRW, emc3d_ratio_read, emc3d_ratio_store); 615static DEVICE_ATTR(emc3d_ratio, ROOTRW, emc3d_ratio_read, emc3d_ratio_store);
638 616
639static ssize_t fmax_at_vmin_safe_read(struct device *device, 617static ssize_t fmax_at_vmin_safe_read(struct device *dev,
640 struct device_attribute *attr, char *buf) 618 struct device_attribute *attr, char *buf)
641{ 619{
642 struct platform_device *ndev = to_platform_device(device); 620 struct gk20a *g = get_gk20a(dev);
643 struct gk20a *g = get_gk20a(ndev);
644 unsigned long gpu_fmax_at_vmin_hz = 0; 621 unsigned long gpu_fmax_at_vmin_hz = 0;
645 622
646 gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t( 623 gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t(
@@ -652,11 +629,10 @@ static ssize_t fmax_at_vmin_safe_read(struct device *device,
652static DEVICE_ATTR(fmax_at_vmin_safe, S_IRUGO, fmax_at_vmin_safe_read, NULL); 629static DEVICE_ATTR(fmax_at_vmin_safe, S_IRUGO, fmax_at_vmin_safe_read, NULL);
653 630
654#ifdef CONFIG_PM 631#ifdef CONFIG_PM
655static ssize_t force_idle_store(struct device *device, 632static ssize_t force_idle_store(struct device *dev,
656 struct device_attribute *attr, const char *buf, size_t count) 633 struct device_attribute *attr, const char *buf, size_t count)
657{ 634{
658 struct platform_device *ndev = to_platform_device(device); 635 struct gk20a *g = get_gk20a(dev);
659 struct gk20a *g = get_gk20a(ndev);
660 unsigned long val = 0; 636 unsigned long val = 0;
661 int err = 0; 637 int err = 0;
662 638
@@ -667,10 +643,10 @@ static ssize_t force_idle_store(struct device *device,
667 if (g->forced_idle) 643 if (g->forced_idle)
668 return count; /* do nothing */ 644 return count; /* do nothing */
669 else { 645 else {
670 err = __gk20a_do_idle(ndev, false); 646 err = __gk20a_do_idle(dev, false);
671 if (!err) { 647 if (!err) {
672 g->forced_idle = 1; 648 g->forced_idle = 1;
673 dev_info(device, "gpu is idle : %d\n", 649 dev_info(dev, "gpu is idle : %d\n",
674 g->forced_idle); 650 g->forced_idle);
675 } 651 }
676 } 652 }
@@ -678,10 +654,10 @@ static ssize_t force_idle_store(struct device *device,
678 if (!g->forced_idle) 654 if (!g->forced_idle)
679 return count; /* do nothing */ 655 return count; /* do nothing */
680 else { 656 else {
681 err = __gk20a_do_unidle(ndev); 657 err = __gk20a_do_unidle(dev);
682 if (!err) { 658 if (!err) {
683 g->forced_idle = 0; 659 g->forced_idle = 0;
684 dev_info(device, "gpu is idle : %d\n", 660 dev_info(dev, "gpu is idle : %d\n",
685 g->forced_idle); 661 g->forced_idle);
686 } 662 }
687 } 663 }
@@ -690,11 +666,10 @@ static ssize_t force_idle_store(struct device *device,
690 return count; 666 return count;
691} 667}
692 668
693static ssize_t force_idle_read(struct device *device, 669static ssize_t force_idle_read(struct device *dev,
694 struct device_attribute *attr, char *buf) 670 struct device_attribute *attr, char *buf)
695{ 671{
696 struct platform_device *ndev = to_platform_device(device); 672 struct gk20a *g = get_gk20a(dev);
697 struct gk20a *g = get_gk20a(ndev);
698 673
699 return sprintf(buf, "%d\n", g->forced_idle ? 1 : 0); 674 return sprintf(buf, "%d\n", g->forced_idle ? 1 : 0);
700} 675}
@@ -702,11 +677,10 @@ static ssize_t force_idle_read(struct device *device,
702static DEVICE_ATTR(force_idle, ROOTRW, force_idle_read, force_idle_store); 677static DEVICE_ATTR(force_idle, ROOTRW, force_idle_read, force_idle_store);
703#endif 678#endif
704 679
705static ssize_t tpc_fs_mask_store(struct device *device, 680static ssize_t tpc_fs_mask_store(struct device *dev,
706 struct device_attribute *attr, const char *buf, size_t count) 681 struct device_attribute *attr, const char *buf, size_t count)
707{ 682{
708 struct platform_device *ndev = to_platform_device(device); 683 struct gk20a *g = get_gk20a(dev);
709 struct gk20a *g = get_gk20a(ndev);
710 unsigned long val = 0; 684 unsigned long val = 0;
711 685
712 if (kstrtoul(buf, 10, &val) < 0) 686 if (kstrtoul(buf, 10, &val) < 0)
@@ -730,11 +704,10 @@ static ssize_t tpc_fs_mask_store(struct device *device,
730 return count; 704 return count;
731} 705}
732 706
733static ssize_t tpc_fs_mask_read(struct device *device, 707static ssize_t tpc_fs_mask_read(struct device *dev,
734 struct device_attribute *attr, char *buf) 708 struct device_attribute *attr, char *buf)
735{ 709{
736 struct platform_device *ndev = to_platform_device(device); 710 struct gk20a *g = get_gk20a(dev);
737 struct gk20a *g = get_gk20a(ndev);
738 struct gr_gk20a *gr = &g->gr; 711 struct gr_gk20a *gr = &g->gr;
739 u32 gpc_index; 712 u32 gpc_index;
740 u32 tpc_fs_mask = 0; 713 u32 tpc_fs_mask = 0;
@@ -760,7 +733,7 @@ static DEVICE_ATTR(tpc_fs_mask, ROOTRW, tpc_fs_mask_read, tpc_fs_mask_store);
760 733
761void gk20a_remove_sysfs(struct device *dev) 734void gk20a_remove_sysfs(struct device *dev)
762{ 735{
763 struct gk20a *g = get_gk20a(to_platform_device(dev)); 736 struct gk20a *g = get_gk20a(dev);
764 737
765 device_remove_file(dev, &dev_attr_elcg_enable); 738 device_remove_file(dev, &dev_attr_elcg_enable);
766 device_remove_file(dev, &dev_attr_blcg_enable); 739 device_remove_file(dev, &dev_attr_blcg_enable);
@@ -797,50 +770,50 @@ void gk20a_remove_sysfs(struct device *dev)
797 } 770 }
798} 771}
799 772
800void gk20a_create_sysfs(struct platform_device *dev) 773void gk20a_create_sysfs(struct device *dev)
801{ 774{
802 struct gk20a *g = get_gk20a(dev); 775 struct gk20a *g = gk20a_from_dev(dev);
803 int error = 0; 776 int error = 0;
804 777
805 error |= device_create_file(&dev->dev, &dev_attr_elcg_enable); 778 error |= device_create_file(dev, &dev_attr_elcg_enable);
806 error |= device_create_file(&dev->dev, &dev_attr_blcg_enable); 779 error |= device_create_file(dev, &dev_attr_blcg_enable);
807 error |= device_create_file(&dev->dev, &dev_attr_slcg_enable); 780 error |= device_create_file(dev, &dev_attr_slcg_enable);
808 error |= device_create_file(&dev->dev, &dev_attr_ptimer_scale_factor); 781 error |= device_create_file(dev, &dev_attr_ptimer_scale_factor);
809 error |= device_create_file(&dev->dev, &dev_attr_elpg_enable); 782 error |= device_create_file(dev, &dev_attr_elpg_enable);
810 error |= device_create_file(&dev->dev, &dev_attr_emc3d_ratio); 783 error |= device_create_file(dev, &dev_attr_emc3d_ratio);
811 error |= device_create_file(&dev->dev, &dev_attr_fmax_at_vmin_safe); 784 error |= device_create_file(dev, &dev_attr_fmax_at_vmin_safe);
812 error |= device_create_file(&dev->dev, &dev_attr_counters); 785 error |= device_create_file(dev, &dev_attr_counters);
813 error |= device_create_file(&dev->dev, &dev_attr_counters_reset); 786 error |= device_create_file(dev, &dev_attr_counters_reset);
814 error |= device_create_file(&dev->dev, &dev_attr_load); 787 error |= device_create_file(dev, &dev_attr_load);
815 error |= device_create_file(&dev->dev, &dev_attr_railgate_delay); 788 error |= device_create_file(dev, &dev_attr_railgate_delay);
816 error |= device_create_file(&dev->dev, &dev_attr_is_railgated); 789 error |= device_create_file(dev, &dev_attr_is_railgated);
817 error |= device_create_file(&dev->dev, &dev_attr_clockgate_delay); 790 error |= device_create_file(dev, &dev_attr_clockgate_delay);
818#ifdef CONFIG_PM 791#ifdef CONFIG_PM
819 error |= device_create_file(&dev->dev, &dev_attr_force_idle); 792 error |= device_create_file(dev, &dev_attr_force_idle);
820#if defined(CONFIG_PM_GENERIC_DOMAINS) 793#if defined(CONFIG_PM_GENERIC_DOMAINS)
821 error |= device_create_file(&dev->dev, &dev_attr_railgate_enable); 794 error |= device_create_file(dev, &dev_attr_railgate_enable);
822#endif 795#endif
823#endif 796#endif
824 error |= device_create_file(&dev->dev, &dev_attr_aelpg_param); 797 error |= device_create_file(dev, &dev_attr_aelpg_param);
825 error |= device_create_file(&dev->dev, &dev_attr_aelpg_enable); 798 error |= device_create_file(dev, &dev_attr_aelpg_enable);
826 error |= device_create_file(&dev->dev, &dev_attr_allow_all); 799 error |= device_create_file(dev, &dev_attr_allow_all);
827 error |= device_create_file(&dev->dev, &dev_attr_tpc_fs_mask); 800 error |= device_create_file(dev, &dev_attr_tpc_fs_mask);
828 801
829 if (g->host1x_dev && (dev->dev.parent != &g->host1x_dev->dev)) { 802 if (g->host1x_dev && (dev->parent != &g->host1x_dev->dev)) {
830 error |= sysfs_create_link(&g->host1x_dev->dev.kobj, 803 error |= sysfs_create_link(&g->host1x_dev->dev.kobj,
831 &dev->dev.kobj, 804 &dev->kobj,
832 dev_name(&dev->dev)); 805 dev_name(dev));
833 if (strcmp(dev_name(&dev->dev), "gpu.0")) { 806 if (strcmp(dev_name(dev), "gpu.0")) {
834 struct kobject *kobj = &dev->dev.kobj; 807 struct kobject *kobj = &dev->kobj;
835 struct device *parent = container_of((kobj->parent), 808 struct device *parent = container_of((kobj->parent),
836 struct device, kobj); 809 struct device, kobj);
837 error |= sysfs_create_link(&parent->kobj, 810 error |= sysfs_create_link(&parent->kobj,
838 &dev->dev.kobj, "gpu.0"); 811 &dev->kobj, "gpu.0");
839 } 812 }
840 813
841 } 814 }
842 815
843 if (error) 816 if (error)
844 dev_err(&dev->dev, "Failed to create sysfs attributes!\n"); 817 dev_err(dev, "Failed to create sysfs attributes!\n");
845 818
846} 819}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index cc3a6813..b0b5571f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2439,10 +2439,10 @@ static int gk20a_gr_alloc_ctx_buffer(struct gk20a *g,
2439 2439
2440static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) 2440static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
2441{ 2441{
2442 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 2442 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
2443 struct gr_gk20a *gr = &g->gr; 2443 struct gr_gk20a *gr = &g->gr;
2444 int i, attr_buffer_size, err; 2444 int i, attr_buffer_size, err;
2445 struct platform_device *pdev = g->dev; 2445 struct device *dev = g->dev;
2446 2446
2447 u32 cb_buffer_size = gr->bundle_cb_default_size * 2447 u32 cb_buffer_size = gr->bundle_cb_default_size *
2448 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); 2448 gr_scc_bundle_cb_size_div_256b_byte_granularity_v();
@@ -2462,7 +2462,7 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
2462 goto clean_up; 2462 goto clean_up;
2463 2463
2464 if (platform->secure_alloc) 2464 if (platform->secure_alloc)
2465 platform->secure_alloc(pdev, 2465 platform->secure_alloc(dev,
2466 &gr->global_ctx_buffer[CIRCULAR_VPR], 2466 &gr->global_ctx_buffer[CIRCULAR_VPR],
2467 cb_buffer_size); 2467 cb_buffer_size);
2468 2468
@@ -2474,7 +2474,7 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
2474 goto clean_up; 2474 goto clean_up;
2475 2475
2476 if (platform->secure_alloc) 2476 if (platform->secure_alloc)
2477 platform->secure_alloc(pdev, 2477 platform->secure_alloc(dev,
2478 &gr->global_ctx_buffer[PAGEPOOL_VPR], 2478 &gr->global_ctx_buffer[PAGEPOOL_VPR],
2479 pagepool_buffer_size); 2479 pagepool_buffer_size);
2480 2480
@@ -2486,12 +2486,12 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
2486 goto clean_up; 2486 goto clean_up;
2487 2487
2488 if (platform->secure_alloc) 2488 if (platform->secure_alloc)
2489 platform->secure_alloc(pdev, 2489 platform->secure_alloc(dev,
2490 &gr->global_ctx_buffer[ATTRIBUTE_VPR], 2490 &gr->global_ctx_buffer[ATTRIBUTE_VPR],
2491 attr_buffer_size); 2491 attr_buffer_size);
2492 2492
2493 if (platform->secure_buffer.destroy) 2493 if (platform->secure_buffer.destroy)
2494 platform->secure_buffer.destroy(pdev, &platform->secure_buffer); 2494 platform->secure_buffer.destroy(dev, &platform->secure_buffer);
2495 2495
2496 gk20a_dbg_info("golden_image_size : %d", 2496 gk20a_dbg_info("golden_image_size : %d",
2497 gr->ctx_vars.golden_image_size); 2497 gr->ctx_vars.golden_image_size);
@@ -5016,7 +5016,7 @@ static int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr,
5016{ 5016{
5017 gk20a_dbg_fn(""); 5017 gk20a_dbg_fn("");
5018 5018
5019 trace_gr_gk20a_handle_sw_method(g->dev->name); 5019 trace_gr_gk20a_handle_sw_method(dev_name(g->dev));
5020 5020
5021 if (class_num == KEPLER_COMPUTE_A) { 5021 if (class_num == KEPLER_COMPUTE_A) {
5022 switch (offset << 2) { 5022 switch (offset << 2) {
@@ -8113,7 +8113,7 @@ static int gr_gk20a_dump_gr_status_regs(struct gk20a *g,
8113#ifdef CONFIG_DEBUG_FS 8113#ifdef CONFIG_DEBUG_FS
8114int gr_gk20a_debugfs_init(struct gk20a *g) 8114int gr_gk20a_debugfs_init(struct gk20a *g)
8115{ 8115{
8116 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 8116 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
8117 8117
8118 g->debugfs_gr_default_attrib_cb_size = 8118 g->debugfs_gr_default_attrib_cb_size =
8119 debugfs_create_u32("gr_default_attrib_cb_size", 8119 debugfs_create_u32("gr_default_attrib_cb_size",
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c
index 10607af0..7755bf7d 100644
--- a/drivers/gpu/nvgpu/gk20a/hal.c
+++ b/drivers/gpu/nvgpu/gk20a/hal.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * NVIDIA GPU HAL interface. 2 * NVIDIA GPU HAL interface.
3 * 3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -41,7 +41,7 @@ int gpu_init_hal(struct gk20a *g)
41 break; 41 break;
42#endif 42#endif
43 default: 43 default:
44 gk20a_err(&g->dev->dev, "no support for %x", ver); 44 gk20a_err(g->dev, "no support for %x", ver);
45 return -ENODEV; 45 return -ENODEV;
46 } 46 }
47 47
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
index 0d9a98b4..963f6bb7 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
@@ -111,7 +111,7 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
111 111
112 gk20a_dbg_fn(""); 112 gk20a_dbg_fn("");
113 113
114 trace_gk20a_ltc_cbc_ctrl_start(g->dev->name, op, min, max); 114 trace_gk20a_ltc_cbc_ctrl_start(dev_name(g->dev), op, min, max);
115 115
116 if (gr->compbit_store.mem.size == 0) 116 if (gr->compbit_store.mem.size == 0)
117 return 0; 117 return 0;
@@ -163,7 +163,7 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
163 } 163 }
164 } 164 }
165out: 165out:
166 trace_gk20a_ltc_cbc_ctrl_done(g->dev->name); 166 trace_gk20a_ltc_cbc_ctrl_done(dev_name(g->dev));
167 mutex_unlock(&g->mm.l2_op_lock); 167 mutex_unlock(&g->mm.l2_op_lock);
168 return err; 168 return err;
169} 169}
@@ -204,7 +204,7 @@ static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g)
204 204
205 gk20a_dbg_fn(""); 205 gk20a_dbg_fn("");
206 206
207 trace_gk20a_mm_g_elpg_flush_locked(g->dev->name); 207 trace_gk20a_mm_g_elpg_flush_locked(dev_name(g->dev));
208 208
209 /* Make sure all previous writes are committed to the L2. There's no 209 /* Make sure all previous writes are committed to the L2. There's no
210 guarantee that writes are to DRAM. This will be a sysmembar internal 210 guarantee that writes are to DRAM. This will be a sysmembar internal
@@ -227,7 +227,7 @@ static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g)
227 gk20a_warn(dev_from_gk20a(g), 227 gk20a_warn(dev_from_gk20a(g),
228 "g_elpg_flush too many retries"); 228 "g_elpg_flush too many retries");
229 229
230 trace_gk20a_mm_g_elpg_flush_locked_done(g->dev->name); 230 trace_gk20a_mm_g_elpg_flush_locked_done(dev_name(g->dev));
231 231
232} 232}
233 233
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 0a773d10..ea8b8024 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A memory interface 2 * GK20A Master Control
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -24,7 +24,7 @@ irqreturn_t mc_gk20a_isr_stall(struct gk20a *g)
24{ 24{
25 u32 mc_intr_0; 25 u32 mc_intr_0;
26 26
27 trace_mc_gk20a_intr_stall(g->dev->name); 27 trace_mc_gk20a_intr_stall(dev_name(g->dev));
28 28
29 if (!g->power_on) 29 if (!g->power_on)
30 return IRQ_NONE; 30 return IRQ_NONE;
@@ -42,7 +42,7 @@ irqreturn_t mc_gk20a_isr_stall(struct gk20a *g)
42 42
43 atomic_inc(&g->hw_irq_stall_count); 43 atomic_inc(&g->hw_irq_stall_count);
44 44
45 trace_mc_gk20a_intr_stall_done(g->dev->name); 45 trace_mc_gk20a_intr_stall_done(dev_name(g->dev));
46 46
47 return IRQ_WAKE_THREAD; 47 return IRQ_WAKE_THREAD;
48} 48}
@@ -77,7 +77,7 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
77 77
78 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); 78 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
79 79
80 trace_mc_gk20a_intr_thread_stall(g->dev->name); 80 trace_mc_gk20a_intr_thread_stall(dev_name(g->dev));
81 81
82 mc_intr_0 = gk20a_readl(g, mc_intr_0_r()); 82 mc_intr_0 = gk20a_readl(g, mc_intr_0_r());
83 hw_irq_count = atomic_read(&g->hw_irq_stall_count); 83 hw_irq_count = atomic_read(&g->hw_irq_stall_count);
@@ -111,7 +111,7 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
111 111
112 wake_up_all(&g->sw_irq_stall_last_handled_wq); 112 wake_up_all(&g->sw_irq_stall_last_handled_wq);
113 113
114 trace_mc_gk20a_intr_thread_stall_done(g->dev->name); 114 trace_mc_gk20a_intr_thread_stall_done(dev_name(g->dev));
115 115
116 return IRQ_HANDLED; 116 return IRQ_HANDLED;
117} 117}
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 7a02d68e..ac4625e0 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -3515,7 +3515,7 @@ int gk20a_mm_fb_flush(struct gk20a *g)
3515 3515
3516 gk20a_busy_noresume(g->dev); 3516 gk20a_busy_noresume(g->dev);
3517 if (!g->power_on) { 3517 if (!g->power_on) {
3518 pm_runtime_put_noidle(&g->dev->dev); 3518 pm_runtime_put_noidle(g->dev);
3519 return 0; 3519 return 0;
3520 } 3520 }
3521 3521
@@ -3525,7 +3525,7 @@ int gk20a_mm_fb_flush(struct gk20a *g)
3525 guarantee that writes are to DRAM. This will be a sysmembar internal 3525 guarantee that writes are to DRAM. This will be a sysmembar internal
3526 to the L2. */ 3526 to the L2. */
3527 3527
3528 trace_gk20a_mm_fb_flush(g->dev->name); 3528 trace_gk20a_mm_fb_flush(dev_name(g->dev));
3529 3529
3530 gk20a_writel(g, flush_fb_flush_r(), 3530 gk20a_writel(g, flush_fb_flush_r(),
3531 flush_fb_flush_pending_busy_f()); 3531 flush_fb_flush_pending_busy_f());
@@ -3552,11 +3552,11 @@ int gk20a_mm_fb_flush(struct gk20a *g)
3552 ret = -EBUSY; 3552 ret = -EBUSY;
3553 } 3553 }
3554 3554
3555 trace_gk20a_mm_fb_flush_done(g->dev->name); 3555 trace_gk20a_mm_fb_flush_done(dev_name(g->dev));
3556 3556
3557 mutex_unlock(&mm->l2_op_lock); 3557 mutex_unlock(&mm->l2_op_lock);
3558 3558
3559 pm_runtime_put_noidle(&g->dev->dev); 3559 pm_runtime_put_noidle(g->dev);
3560 3560
3561 return ret; 3561 return ret;
3562} 3562}
@@ -3566,7 +3566,7 @@ static void gk20a_mm_l2_invalidate_locked(struct gk20a *g)
3566 u32 data; 3566 u32 data;
3567 s32 retry = 200; 3567 s32 retry = 200;
3568 3568
3569 trace_gk20a_mm_l2_invalidate(g->dev->name); 3569 trace_gk20a_mm_l2_invalidate(dev_name(g->dev));
3570 3570
3571 /* Invalidate any clean lines from the L2 so subsequent reads go to 3571 /* Invalidate any clean lines from the L2 so subsequent reads go to
3572 DRAM. Dirty lines are not affected by this operation. */ 3572 DRAM. Dirty lines are not affected by this operation. */
@@ -3592,7 +3592,7 @@ static void gk20a_mm_l2_invalidate_locked(struct gk20a *g)
3592 gk20a_warn(dev_from_gk20a(g), 3592 gk20a_warn(dev_from_gk20a(g),
3593 "l2_system_invalidate too many retries"); 3593 "l2_system_invalidate too many retries");
3594 3594
3595 trace_gk20a_mm_l2_invalidate_done(g->dev->name); 3595 trace_gk20a_mm_l2_invalidate_done(dev_name(g->dev));
3596} 3596}
3597 3597
3598void gk20a_mm_l2_invalidate(struct gk20a *g) 3598void gk20a_mm_l2_invalidate(struct gk20a *g)
@@ -3604,7 +3604,7 @@ void gk20a_mm_l2_invalidate(struct gk20a *g)
3604 gk20a_mm_l2_invalidate_locked(g); 3604 gk20a_mm_l2_invalidate_locked(g);
3605 mutex_unlock(&mm->l2_op_lock); 3605 mutex_unlock(&mm->l2_op_lock);
3606 } 3606 }
3607 pm_runtime_put_noidle(&g->dev->dev); 3607 pm_runtime_put_noidle(g->dev);
3608} 3608}
3609 3609
3610void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate) 3610void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate)
@@ -3621,7 +3621,7 @@ void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate)
3621 3621
3622 mutex_lock(&mm->l2_op_lock); 3622 mutex_lock(&mm->l2_op_lock);
3623 3623
3624 trace_gk20a_mm_l2_flush(g->dev->name); 3624 trace_gk20a_mm_l2_flush(dev_name(g->dev));
3625 3625
3626 /* Flush all dirty lines from the L2 to DRAM. Lines are left in the L2 3626 /* Flush all dirty lines from the L2 to DRAM. Lines are left in the L2
3627 as clean, so subsequent reads might hit in the L2. */ 3627 as clean, so subsequent reads might hit in the L2. */
@@ -3646,7 +3646,7 @@ void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate)
3646 gk20a_warn(dev_from_gk20a(g), 3646 gk20a_warn(dev_from_gk20a(g),
3647 "l2_flush_dirty too many retries"); 3647 "l2_flush_dirty too many retries");
3648 3648
3649 trace_gk20a_mm_l2_flush_done(g->dev->name); 3649 trace_gk20a_mm_l2_flush_done(dev_name(g->dev));
3650 3650
3651 if (invalidate) 3651 if (invalidate)
3652 gk20a_mm_l2_invalidate_locked(g); 3652 gk20a_mm_l2_invalidate_locked(g);
@@ -3654,7 +3654,7 @@ void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate)
3654 mutex_unlock(&mm->l2_op_lock); 3654 mutex_unlock(&mm->l2_op_lock);
3655 3655
3656hw_was_off: 3656hw_was_off:
3657 pm_runtime_put_noidle(&g->dev->dev); 3657 pm_runtime_put_noidle(g->dev);
3658} 3658}
3659 3659
3660void gk20a_mm_cbc_clean(struct gk20a *g) 3660void gk20a_mm_cbc_clean(struct gk20a *g)
@@ -3696,7 +3696,7 @@ void gk20a_mm_cbc_clean(struct gk20a *g)
3696 mutex_unlock(&mm->l2_op_lock); 3696 mutex_unlock(&mm->l2_op_lock);
3697 3697
3698hw_was_off: 3698hw_was_off:
3699 pm_runtime_put_noidle(&g->dev->dev); 3699 pm_runtime_put_noidle(g->dev);
3700} 3700}
3701 3701
3702int gk20a_vm_find_buffer(struct vm_gk20a *vm, u64 gpu_va, 3702int gk20a_vm_find_buffer(struct vm_gk20a *vm, u64 gpu_va,
@@ -3746,7 +3746,7 @@ void gk20a_mm_tlb_invalidate(struct vm_gk20a *vm)
3746 3746
3747 mutex_lock(&tlb_lock); 3747 mutex_lock(&tlb_lock);
3748 3748
3749 trace_gk20a_mm_tlb_invalidate(g->dev->name); 3749 trace_gk20a_mm_tlb_invalidate(dev_name(g->dev));
3750 3750
3751 do { 3751 do {
3752 data = gk20a_readl(g, fb_mmu_ctrl_r()); 3752 data = gk20a_readl(g, fb_mmu_ctrl_r());
@@ -3783,7 +3783,7 @@ void gk20a_mm_tlb_invalidate(struct vm_gk20a *vm)
3783 gk20a_warn(dev_from_gk20a(g), 3783 gk20a_warn(dev_from_gk20a(g),
3784 "mmu invalidate too many retries"); 3784 "mmu invalidate too many retries");
3785 3785
3786 trace_gk20a_mm_tlb_invalidate_done(g->dev->name); 3786 trace_gk20a_mm_tlb_invalidate_done(dev_name(g->dev));
3787 3787
3788out: 3788out:
3789 mutex_unlock(&tlb_lock); 3789 mutex_unlock(&tlb_lock);
@@ -3868,11 +3868,11 @@ clean_up:
3868 return err; 3868 return err;
3869} 3869}
3870 3870
3871void gk20a_mm_debugfs_init(struct platform_device *pdev) 3871void gk20a_mm_debugfs_init(struct device *dev)
3872{ 3872{
3873 struct gk20a_platform *platform = platform_get_drvdata(pdev); 3873 struct gk20a_platform *platform = dev_get_drvdata(dev);
3874 struct dentry *gpu_root = platform->debugfs; 3874 struct dentry *gpu_root = platform->debugfs;
3875 struct gk20a *g = gk20a_get_platform(pdev)->g; 3875 struct gk20a *g = gk20a_get_platform(dev)->g;
3876 3876
3877 debugfs_create_x64("separate_fixed_allocs", 0664, gpu_root, 3877 debugfs_create_x64("separate_fixed_allocs", 0664, gpu_root,
3878 &g->separate_fixed_allocs); 3878 &g->separate_fixed_allocs);
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index 833d896d..52d6c4e5 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -288,7 +288,7 @@ struct channel_gk20a;
288int gk20a_init_mm_support(struct gk20a *g); 288int gk20a_init_mm_support(struct gk20a *g);
289int gk20a_init_mm_setup_sw(struct gk20a *g); 289int gk20a_init_mm_setup_sw(struct gk20a *g);
290int gk20a_init_mm_setup_hw(struct gk20a *g); 290int gk20a_init_mm_setup_hw(struct gk20a *g);
291void gk20a_mm_debugfs_init(struct platform_device *pdev); 291void gk20a_mm_debugfs_init(struct device *dev);
292 292
293int gk20a_mm_fb_flush(struct gk20a *g); 293int gk20a_mm_fb_flush(struct gk20a *g);
294void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate); 294void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate);
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
index 6bffed9e..b2f3b870 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
@@ -1,9 +1,7 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/soc/platform_gk20a.h
3 *
4 * GK20A Platform (SoC) Interface 2 * GK20A Platform (SoC) Interface
5 * 3 *
6 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
7 * 5 *
8 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -18,7 +16,7 @@
18#ifndef _GK20A_PLATFORM_H_ 16#ifndef _GK20A_PLATFORM_H_
19#define _GK20A_PLATFORM_H_ 17#define _GK20A_PLATFORM_H_
20 18
21#include <linux/platform_device.h> 19#include <linux/device.h>
22#include <linux/pm_domain.h> 20#include <linux/pm_domain.h>
23#include <linux/dma-attrs.h> 21#include <linux/dma-attrs.h>
24 22
@@ -28,7 +26,7 @@ struct gr_ctx_buffer_desc;
28struct gk20a_scale_profile; 26struct gk20a_scale_profile;
29 27
30struct secure_page_buffer { 28struct secure_page_buffer {
31 void (*destroy)(struct platform_device *, struct secure_page_buffer *); 29 void (*destroy)(struct device *, struct secure_page_buffer *);
32 size_t size; 30 size_t size;
33 u64 iova; 31 u64 iova;
34 struct dma_attrs attrs; 32 struct dma_attrs attrs;
@@ -114,28 +112,28 @@ struct gk20a_platform {
114 * After this function is finished, the driver will initialise 112 * After this function is finished, the driver will initialise
115 * pm runtime and genpd based on the platform configuration. 113 * pm runtime and genpd based on the platform configuration.
116 */ 114 */
117 int (*probe)(struct platform_device *dev); 115 int (*probe)(struct device *dev);
118 116
119 /* Second stage initialisation - called once all power management 117 /* Second stage initialisation - called once all power management
120 * initialisations are done. 118 * initialisations are done.
121 */ 119 */
122 int (*late_probe)(struct platform_device *dev); 120 int (*late_probe)(struct device *dev);
123 121
124 /* Remove device after power management has been done 122 /* Remove device after power management has been done
125 */ 123 */
126 int (*remove)(struct platform_device *dev); 124 int (*remove)(struct device *dev);
127 125
128 /* Poweron platform dependencies */ 126 /* Poweron platform dependencies */
129 int (*busy)(struct platform_device *dev); 127 int (*busy)(struct device *dev);
130 128
131 /* Powerdown platform dependencies */ 129 /* Powerdown platform dependencies */
132 void (*idle)(struct platform_device *dev); 130 void (*idle)(struct device *dev);
133 131
134 /* This function is called to allocate secure memory (memory that the 132 /* This function is called to allocate secure memory (memory that the
135 * CPU cannot see). The function should fill the context buffer 133 * CPU cannot see). The function should fill the context buffer
136 * descriptor (especially fields destroy, sgt, size). 134 * descriptor (especially fields destroy, sgt, size).
137 */ 135 */
138 int (*secure_alloc)(struct platform_device *dev, 136 int (*secure_alloc)(struct device *dev,
139 struct gr_ctx_buffer_desc *desc, 137 struct gr_ctx_buffer_desc *desc,
140 size_t size); 138 size_t size);
141 139
@@ -143,7 +141,7 @@ struct gk20a_platform {
143 * This is also helpful to trigger secure memory resizing 141 * This is also helpful to trigger secure memory resizing
144 * while GPU is off 142 * while GPU is off
145 */ 143 */
146 int (*secure_page_alloc)(struct platform_device *dev); 144 int (*secure_page_alloc)(struct device *dev);
147 struct secure_page_buffer secure_buffer; 145 struct secure_page_buffer secure_buffer;
148 bool secure_alloc_ready; 146 bool secure_alloc_ready;
149 147
@@ -151,33 +149,33 @@ struct gk20a_platform {
151 int (*suspend)(struct device *); 149 int (*suspend)(struct device *);
152 150
153 /* Called to turn off the device */ 151 /* Called to turn off the device */
154 int (*railgate)(struct platform_device *dev); 152 int (*railgate)(struct device *dev);
155 153
156 /* Called to turn on the device */ 154 /* Called to turn on the device */
157 int (*unrailgate)(struct platform_device *dev); 155 int (*unrailgate)(struct device *dev);
158 struct mutex railgate_lock; 156 struct mutex railgate_lock;
159 157
160 /* Called to check state of device */ 158 /* Called to check state of device */
161 bool (*is_railgated)(struct platform_device *dev); 159 bool (*is_railgated)(struct device *dev);
162 160
163 /* get supported frequency list */ 161 /* get supported frequency list */
164 int (*get_clk_freqs)(struct platform_device *pdev, 162 int (*get_clk_freqs)(struct device *pdev,
165 unsigned long **freqs, int *num_freqs); 163 unsigned long **freqs, int *num_freqs);
166 164
167 /* clk related supported functions */ 165 /* clk related supported functions */
168 unsigned long (*clk_get_rate)(struct platform_device *pdev); 166 unsigned long (*clk_get_rate)(struct device *dev);
169 long (*clk_round_rate)(struct platform_device *pdev, 167 long (*clk_round_rate)(struct device *dev,
170 unsigned long rate); 168 unsigned long rate);
171 int (*clk_set_rate)(struct platform_device *pdev, 169 int (*clk_set_rate)(struct device *dev,
172 unsigned long rate); 170 unsigned long rate);
173 171
174 172
175 /* Postscale callback is called after frequency change */ 173 /* Postscale callback is called after frequency change */
176 void (*postscale)(struct platform_device *pdev, 174 void (*postscale)(struct device *dev,
177 unsigned long freq); 175 unsigned long freq);
178 176
179 /* Pre callback is called before frequency change */ 177 /* Pre callback is called before frequency change */
180 void (*prescale)(struct platform_device *pdev); 178 void (*prescale)(struct device *dev);
181 179
182 /* Devfreq governor name. If scaling is enabled, we request 180 /* Devfreq governor name. If scaling is enabled, we request
183 * this governor to be used in scaling */ 181 * this governor to be used in scaling */
@@ -193,11 +191,11 @@ struct gk20a_platform {
193 * hw units which may interact with the gpu without direct supervision 191 * hw units which may interact with the gpu without direct supervision
194 * of the CPU. 192 * of the CPU.
195 */ 193 */
196 void (*dump_platform_dependencies)(struct platform_device *dev); 194 void (*dump_platform_dependencies)(struct device *dev);
197 195
198 /* Callbacks to assert/deassert GPU reset */ 196 /* Callbacks to assert/deassert GPU reset */
199 int (*reset_assert)(struct platform_device *pdev); 197 int (*reset_assert)(struct device *dev);
200 int (*reset_deassert)(struct platform_device *pdev); 198 int (*reset_deassert)(struct device *dev);
201 struct clk *clk_reset; 199 struct clk *clk_reset;
202 struct dvfs_rail *gpu_rail; 200 struct dvfs_rail *gpu_rail;
203 201
@@ -210,12 +208,15 @@ struct gk20a_platform {
210 u32 ptimer_src_freq; 208 u32 ptimer_src_freq;
211 209
212 bool has_cde; 210 bool has_cde;
211
212 /* soc name for finding firmware files */
213 const char *soc_name;
213}; 214};
214 215
215static inline struct gk20a_platform *gk20a_get_platform( 216static inline struct gk20a_platform *gk20a_get_platform(
216 struct platform_device *dev) 217 struct device *dev)
217{ 218{
218 return (struct gk20a_platform *)platform_get_drvdata(dev); 219 return (struct gk20a_platform *)dev_get_drvdata(dev);
219} 220}
220 221
221extern struct gk20a_platform gk20a_generic_platform; 222extern struct gk20a_platform gk20a_generic_platform;
@@ -227,14 +228,14 @@ extern struct gk20a_platform vgpu_tegra_platform;
227#endif 228#endif
228#endif 229#endif
229 230
230static inline bool gk20a_platform_has_syncpoints(struct platform_device *dev) 231static inline bool gk20a_platform_has_syncpoints(struct device *dev)
231{ 232{
232 struct gk20a_platform *p = gk20a_get_platform(dev); 233 struct gk20a_platform *p = dev_get_drvdata(dev);
233 return p->has_syncpoints; 234 return p->has_syncpoints;
234} 235}
235 236
236int gk20a_tegra_busy(struct platform_device *dev); 237int gk20a_tegra_busy(struct device *dev);
237void gk20a_tegra_idle(struct platform_device *dev); 238void gk20a_tegra_idle(struct device *dev);
238void gk20a_tegra_debug_dump(struct platform_device *pdev); 239void gk20a_tegra_debug_dump(struct device *pdev);
239 240
240#endif 241#endif
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c
index 74e59527..33e2fb37 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_generic.c
@@ -31,9 +31,9 @@
31 * the clock information to gk20a platform data. 31 * the clock information to gk20a platform data.
32 */ 32 */
33 33
34static int gk20a_generic_get_clocks(struct platform_device *pdev) 34static int gk20a_generic_get_clocks(struct device *pdev)
35{ 35{
36 struct gk20a_platform *platform = platform_get_drvdata(pdev); 36 struct gk20a_platform *platform = dev_get_drvdata(pdev);
37 37
38 platform->clk[0] = clk_get_sys("tegra_gk20a.0", "PLLG_ref"); 38 platform->clk[0] = clk_get_sys("tegra_gk20a.0", "PLLG_ref");
39 platform->clk[1] = clk_get_sys("tegra_gk20a.0", "pwr"); 39 platform->clk[1] = clk_get_sys("tegra_gk20a.0", "pwr");
@@ -65,19 +65,19 @@ err_get_clock:
65 return -ENODEV; 65 return -ENODEV;
66} 66}
67 67
68static int gk20a_generic_probe(struct platform_device *dev) 68static int gk20a_generic_probe(struct device *dev)
69{ 69{
70 gk20a_generic_get_clocks(dev); 70 gk20a_generic_get_clocks(dev);
71 71
72 return 0; 72 return 0;
73} 73}
74 74
75static int gk20a_generic_late_probe(struct platform_device *dev) 75static int gk20a_generic_late_probe(struct device *dev)
76{ 76{
77 return 0; 77 return 0;
78} 78}
79 79
80static int gk20a_generic_remove(struct platform_device *dev) 80static int gk20a_generic_remove(struct device *dev)
81{ 81{
82 return 0; 82 return 0;
83} 83}
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
index 15d6609d..468c9257 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/platform_gk20a_tegra.c
3 *
4 * GK20A Tegra Platform Interface 2 * GK20A Tegra Platform Interface
5 * 3 *
6 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
@@ -66,7 +64,7 @@ static inline void pmc_write(u32 val, unsigned long reg)
66#define MHZ_TO_HZ(x) ((x) * 1000000) 64#define MHZ_TO_HZ(x) ((x) * 1000000)
67#define HZ_TO_MHZ(x) ((x) / 1000000) 65#define HZ_TO_MHZ(x) ((x) / 1000000)
68 66
69static void gk20a_tegra_secure_page_destroy(struct platform_device *pdev, 67static void gk20a_tegra_secure_page_destroy(struct device *dev,
70 struct secure_page_buffer *secure_buffer) 68 struct secure_page_buffer *secure_buffer)
71{ 69{
72 dma_free_attrs(&tegra_vpr_dev, secure_buffer->size, 70 dma_free_attrs(&tegra_vpr_dev, secure_buffer->size,
@@ -74,9 +72,9 @@ static void gk20a_tegra_secure_page_destroy(struct platform_device *pdev,
74 secure_buffer->iova, &secure_buffer->attrs); 72 secure_buffer->iova, &secure_buffer->attrs);
75} 73}
76 74
77int gk20a_tegra_secure_page_alloc(struct platform_device *pdev) 75int gk20a_tegra_secure_page_alloc(struct device *dev)
78{ 76{
79 struct gk20a_platform *platform = platform_get_drvdata(pdev); 77 struct gk20a_platform *platform = dev_get_drvdata(dev);
80 struct secure_page_buffer *secure_buffer = &platform->secure_buffer; 78 struct secure_page_buffer *secure_buffer = &platform->secure_buffer;
81 DEFINE_DMA_ATTRS(attrs); 79 DEFINE_DMA_ATTRS(attrs);
82 dma_addr_t iova; 80 dma_addr_t iova;
@@ -113,12 +111,11 @@ static void gk20a_tegra_secure_destroy(struct gk20a *g,
113 } 111 }
114} 112}
115 113
116int gk20a_tegra_secure_alloc(struct platform_device *pdev, 114int gk20a_tegra_secure_alloc(struct device *dev,
117 struct gr_ctx_buffer_desc *desc, 115 struct gr_ctx_buffer_desc *desc,
118 size_t size) 116 size_t size)
119{ 117{
120 struct gk20a_platform *platform = platform_get_drvdata(pdev); 118 struct gk20a_platform *platform = dev_get_drvdata(dev);
121 struct device *dev = &pdev->dev;
122 DEFINE_DMA_ATTRS(attrs); 119 DEFINE_DMA_ATTRS(attrs);
123 dma_addr_t iova; 120 dma_addr_t iova;
124 struct sg_table *sgt; 121 struct sg_table *sgt;
@@ -198,13 +195,13 @@ static unsigned long gk20a_tegra_get_emc_rate(struct gk20a *g,
198 * This function sets emc frequency based on current gpu frequency 195 * This function sets emc frequency based on current gpu frequency
199 */ 196 */
200 197
201static void gk20a_tegra_postscale(struct platform_device *pdev, 198static void gk20a_tegra_postscale(struct device *dev,
202 unsigned long freq) 199 unsigned long freq)
203{ 200{
204 struct gk20a_platform *platform = platform_get_drvdata(pdev); 201 struct gk20a_platform *platform = dev_get_drvdata(dev);
205 struct gk20a_scale_profile *profile = platform->g->scale_profile; 202 struct gk20a_scale_profile *profile = platform->g->scale_profile;
206 struct gk20a_emc_params *emc_params = profile->private_data; 203 struct gk20a_emc_params *emc_params = profile->private_data;
207 struct gk20a *g = get_gk20a(pdev); 204 struct gk20a *g = get_gk20a(dev);
208 struct clk *emc_clk = platform->clk[2]; 205 struct clk *emc_clk = platform->clk[2];
209 enum tegra_chipid chip_id = tegra_get_chip_id(); 206 enum tegra_chipid chip_id = tegra_get_chip_id();
210 unsigned long emc_target; 207 unsigned long emc_target;
@@ -257,9 +254,9 @@ static void gk20a_tegra_postscale(struct platform_device *pdev,
257 * This function informs EDP about changed constraints. 254 * This function informs EDP about changed constraints.
258 */ 255 */
259 256
260static void gk20a_tegra_prescale(struct platform_device *pdev) 257static void gk20a_tegra_prescale(struct device *dev)
261{ 258{
262 struct gk20a *g = get_gk20a(pdev); 259 struct gk20a *g = get_gk20a(dev);
263 u32 avg = 0; 260 u32 avg = 0;
264 261
265 gk20a_pmu_load_norm(g, &avg); 262 gk20a_pmu_load_norm(g, &avg);
@@ -271,7 +268,7 @@ static void gk20a_tegra_prescale(struct platform_device *pdev)
271 * 268 *
272 */ 269 */
273 270
274static void gk20a_tegra_calibrate_emc(struct platform_device *pdev, 271static void gk20a_tegra_calibrate_emc(struct device *dev,
275 struct gk20a_emc_params *emc_params) 272 struct gk20a_emc_params *emc_params)
276{ 273{
277 enum tegra_chipid cid = tegra_get_chipid(); 274 enum tegra_chipid cid = tegra_get_chipid();
@@ -308,9 +305,9 @@ static void gk20a_tegra_calibrate_emc(struct platform_device *pdev,
308 * Check status of gk20a power rail 305 * Check status of gk20a power rail
309 */ 306 */
310 307
311static bool gk20a_tegra_is_railgated(struct platform_device *pdev) 308static bool gk20a_tegra_is_railgated(struct device *dev)
312{ 309{
313 struct gk20a_platform *platform = platform_get_drvdata(pdev); 310 struct gk20a_platform *platform = dev_get_drvdata(dev);
314 bool ret = false; 311 bool ret = false;
315 312
316 if (!tegra_platform_is_linsim()) 313 if (!tegra_platform_is_linsim())
@@ -325,9 +322,9 @@ static bool gk20a_tegra_is_railgated(struct platform_device *pdev)
325 * Gate (disable) gk20a power rail 322 * Gate (disable) gk20a power rail
326 */ 323 */
327 324
328static int gk20a_tegra_railgate(struct platform_device *pdev) 325static int gk20a_tegra_railgate(struct device *dev)
329{ 326{
330 struct gk20a_platform *platform = platform_get_drvdata(pdev); 327 struct gk20a_platform *platform = dev_get_drvdata(dev);
331 int ret = 0; 328 int ret = 0;
332 329
333 if (tegra_platform_is_linsim() || 330 if (tegra_platform_is_linsim() ||
@@ -344,7 +341,7 @@ static int gk20a_tegra_railgate(struct platform_device *pdev)
344 341
345 udelay(10); 342 udelay(10);
346 343
347 platform->reset_assert(pdev); 344 platform->reset_assert(dev);
348 345
349 udelay(10); 346 udelay(10);
350 347
@@ -367,7 +364,7 @@ static int gk20a_tegra_railgate(struct platform_device *pdev)
367 return 0; 364 return 0;
368 365
369err_power_off: 366err_power_off:
370 gk20a_err(&pdev->dev, "Could not railgate GPU"); 367 gk20a_err(dev, "Could not railgate GPU");
371 return ret; 368 return ret;
372} 369}
373 370
@@ -377,9 +374,9 @@ err_power_off:
377 * Gate (disable) gm20b power rail 374 * Gate (disable) gm20b power rail
378 */ 375 */
379 376
380static int gm20b_tegra_railgate(struct platform_device *pdev) 377static int gm20b_tegra_railgate(struct device *dev)
381{ 378{
382 struct gk20a_platform *platform = platform_get_drvdata(pdev); 379 struct gk20a_platform *platform = dev_get_drvdata(dev);
383 int ret = 0; 380 int ret = 0;
384 381
385 if (tegra_platform_is_linsim() || 382 if (tegra_platform_is_linsim() ||
@@ -396,7 +393,7 @@ static int gm20b_tegra_railgate(struct platform_device *pdev)
396 393
397 udelay(10); 394 udelay(10);
398 395
399 platform->reset_assert(pdev); 396 platform->reset_assert(dev);
400 397
401 udelay(10); 398 udelay(10);
402 399
@@ -422,7 +419,7 @@ static int gm20b_tegra_railgate(struct platform_device *pdev)
422 return 0; 419 return 0;
423 420
424err_power_off: 421err_power_off:
425 gk20a_err(&pdev->dev, "Could not railgate GPU"); 422 gk20a_err(dev, "Could not railgate GPU");
426 return ret; 423 return ret;
427} 424}
428 425
@@ -432,9 +429,9 @@ err_power_off:
432 * Ungate (enable) gk20a power rail 429 * Ungate (enable) gk20a power rail
433 */ 430 */
434 431
435static int gk20a_tegra_unrailgate(struct platform_device *pdev) 432static int gk20a_tegra_unrailgate(struct device *dev)
436{ 433{
437 struct gk20a_platform *platform = platform_get_drvdata(pdev); 434 struct gk20a_platform *platform = dev_get_drvdata(dev);
438 int ret = 0; 435 int ret = 0;
439 bool first = false; 436 bool first = false;
440 437
@@ -457,19 +454,19 @@ static int gk20a_tegra_unrailgate(struct platform_device *pdev)
457 if (!first) { 454 if (!first) {
458 ret = clk_enable(platform->clk[0]); 455 ret = clk_enable(platform->clk[0]);
459 if (ret) { 456 if (ret) {
460 gk20a_err(&pdev->dev, "could not turn on gpu pll"); 457 gk20a_err(dev, "could not turn on gpu pll");
461 goto err_clk_on; 458 goto err_clk_on;
462 } 459 }
463 ret = clk_enable(platform->clk[1]); 460 ret = clk_enable(platform->clk[1]);
464 if (ret) { 461 if (ret) {
465 gk20a_err(&pdev->dev, "could not turn on pwr clock"); 462 gk20a_err(dev, "could not turn on pwr clock");
466 goto err_clk_on; 463 goto err_clk_on;
467 } 464 }
468 } 465 }
469 466
470 udelay(10); 467 udelay(10);
471 468
472 platform->reset_assert(pdev); 469 platform->reset_assert(dev);
473 470
474 udelay(10); 471 udelay(10);
475 472
@@ -478,7 +475,7 @@ static int gk20a_tegra_unrailgate(struct platform_device *pdev)
478 475
479 udelay(10); 476 udelay(10);
480 477
481 platform->reset_deassert(pdev); 478 platform->reset_deassert(dev);
482 479
483 /* Flush MC after boot/railgate/SC7 */ 480 /* Flush MC after boot/railgate/SC7 */
484 tegra_mc_flush(MC_CLIENT_GPU); 481 tegra_mc_flush(MC_CLIENT_GPU);
@@ -503,9 +500,9 @@ err_clk_on:
503 * Ungate (enable) gm20b power rail 500 * Ungate (enable) gm20b power rail
504 */ 501 */
505 502
506static int gm20b_tegra_unrailgate(struct platform_device *pdev) 503static int gm20b_tegra_unrailgate(struct device *dev)
507{ 504{
508 struct gk20a_platform *platform = platform_get_drvdata(pdev); 505 struct gk20a_platform *platform = dev_get_drvdata(dev);
509 int ret = 0; 506 int ret = 0;
510 bool first = false; 507 bool first = false;
511 508
@@ -530,25 +527,25 @@ static int gm20b_tegra_unrailgate(struct platform_device *pdev)
530 if (!first) { 527 if (!first) {
531 ret = clk_enable(platform->clk_reset); 528 ret = clk_enable(platform->clk_reset);
532 if (ret) { 529 if (ret) {
533 gk20a_err(&pdev->dev, "could not turn on gpu_gate"); 530 gk20a_err(dev, "could not turn on gpu_gate");
534 goto err_clk_on; 531 goto err_clk_on;
535 } 532 }
536 533
537 ret = clk_enable(platform->clk[0]); 534 ret = clk_enable(platform->clk[0]);
538 if (ret) { 535 if (ret) {
539 gk20a_err(&pdev->dev, "could not turn on gpu pll"); 536 gk20a_err(dev, "could not turn on gpu pll");
540 goto err_clk_on; 537 goto err_clk_on;
541 } 538 }
542 ret = clk_enable(platform->clk[1]); 539 ret = clk_enable(platform->clk[1]);
543 if (ret) { 540 if (ret) {
544 gk20a_err(&pdev->dev, "could not turn on pwr clock"); 541 gk20a_err(dev, "could not turn on pwr clock");
545 goto err_clk_on; 542 goto err_clk_on;
546 } 543 }
547 } 544 }
548 545
549 udelay(10); 546 udelay(10);
550 547
551 platform->reset_assert(pdev); 548 platform->reset_assert(dev);
552 549
553 udelay(10); 550 udelay(10);
554 551
@@ -558,7 +555,7 @@ static int gm20b_tegra_unrailgate(struct platform_device *pdev)
558 udelay(10); 555 udelay(10);
559 556
560 clk_disable(platform->clk_reset); 557 clk_disable(platform->clk_reset);
561 platform->reset_deassert(pdev); 558 platform->reset_deassert(dev);
562 clk_enable(platform->clk_reset); 559 clk_enable(platform->clk_reset);
563 560
564 /* Flush MC after boot/railgate/SC7 */ 561 /* Flush MC after boot/railgate/SC7 */
@@ -594,16 +591,14 @@ static struct {
594 * the clock information to gk20a platform data. 591 * the clock information to gk20a platform data.
595 */ 592 */
596 593
597static int gk20a_tegra_get_clocks(struct platform_device *pdev) 594static int gk20a_tegra_get_clocks(struct device *dev)
598{ 595{
599 struct gk20a_platform *platform = platform_get_drvdata(pdev); 596 struct gk20a_platform *platform = dev_get_drvdata(dev);
600 char devname[16]; 597 char devname[16];
601 int i; 598 int i;
602 int ret = 0; 599 int ret = 0;
603 600
604 snprintf(devname, sizeof(devname), 601 snprintf(devname, sizeof(devname), "tegra_%s", dev_name(dev));
605 (pdev->id <= 0) ? "tegra_%s" : "tegra_%s.%d\n",
606 pdev->name, pdev->id);
607 602
608 platform->num_clks = 0; 603 platform->num_clks = 0;
609 for (i = 0; i < ARRAY_SIZE(tegra_gk20a_clocks); i++) { 604 for (i = 0; i < ARRAY_SIZE(tegra_gk20a_clocks); i++) {
@@ -630,7 +625,7 @@ err_get_clock:
630 return ret; 625 return ret;
631} 626}
632 627
633static int gk20a_tegra_reset_assert(struct platform_device *dev) 628static int gk20a_tegra_reset_assert(struct device *dev)
634{ 629{
635 struct gk20a_platform *platform = gk20a_get_platform(dev); 630 struct gk20a_platform *platform = gk20a_get_platform(dev);
636 631
@@ -642,7 +637,7 @@ static int gk20a_tegra_reset_assert(struct platform_device *dev)
642 return 0; 637 return 0;
643} 638}
644 639
645static int gk20a_tegra_reset_deassert(struct platform_device *dev) 640static int gk20a_tegra_reset_deassert(struct device *dev)
646{ 641{
647 struct gk20a_platform *platform = gk20a_get_platform(dev); 642 struct gk20a_platform *platform = gk20a_get_platform(dev);
648 643
@@ -654,14 +649,14 @@ static int gk20a_tegra_reset_deassert(struct platform_device *dev)
654 return 0; 649 return 0;
655} 650}
656 651
657static int gm20b_tegra_reset_assert(struct platform_device *dev) 652static int gm20b_tegra_reset_assert(struct device *dev)
658{ 653{
659 struct gk20a_platform *platform = gk20a_get_platform(dev); 654 struct gk20a_platform *platform = gk20a_get_platform(dev);
660 655
661 if (!platform->clk_reset) { 656 if (!platform->clk_reset) {
662 platform->clk_reset = clk_get(&dev->dev, "gpu_gate"); 657 platform->clk_reset = clk_get(dev, "gpu_gate");
663 if (IS_ERR(platform->clk_reset)) { 658 if (IS_ERR(platform->clk_reset)) {
664 gk20a_err(&dev->dev, "fail to get gpu reset clk\n"); 659 gk20a_err(dev, "fail to get gpu reset clk\n");
665 return PTR_ERR(platform->clk_reset); 660 return PTR_ERR(platform->clk_reset);
666 } 661 }
667 } 662 }
@@ -671,9 +666,9 @@ static int gm20b_tegra_reset_assert(struct platform_device *dev)
671 return 0; 666 return 0;
672} 667}
673 668
674static void gk20a_tegra_scale_init(struct platform_device *pdev) 669static void gk20a_tegra_scale_init(struct device *dev)
675{ 670{
676 struct gk20a_platform *platform = gk20a_get_platform(pdev); 671 struct gk20a_platform *platform = gk20a_get_platform(dev);
677 struct gk20a_scale_profile *profile = platform->g->scale_profile; 672 struct gk20a_scale_profile *profile = platform->g->scale_profile;
678 struct gk20a_emc_params *emc_params; 673 struct gk20a_emc_params *emc_params;
679 674
@@ -685,28 +680,28 @@ static void gk20a_tegra_scale_init(struct platform_device *pdev)
685 return; 680 return;
686 681
687 emc_params->freq_last_set = -1; 682 emc_params->freq_last_set = -1;
688 gk20a_tegra_calibrate_emc(pdev, emc_params); 683 gk20a_tegra_calibrate_emc(dev, emc_params);
689 684
690 profile->private_data = emc_params; 685 profile->private_data = emc_params;
691} 686}
692 687
693static void gk20a_tegra_scale_exit(struct platform_device *pdev) 688static void gk20a_tegra_scale_exit(struct device *dev)
694{ 689{
695 struct gk20a_platform *platform = gk20a_get_platform(pdev); 690 struct gk20a_platform *platform = dev_get_drvdata(dev);
696 struct gk20a_scale_profile *profile = platform->g->scale_profile; 691 struct gk20a_scale_profile *profile = platform->g->scale_profile;
697 692
698 if (profile) 693 if (profile)
699 kfree(profile->private_data); 694 kfree(profile->private_data);
700} 695}
701 696
702void gk20a_tegra_debug_dump(struct platform_device *pdev) 697void gk20a_tegra_debug_dump(struct device *dev)
703{ 698{
704 struct gk20a_platform *platform = gk20a_get_platform(pdev); 699 struct gk20a_platform *platform = gk20a_get_platform(dev);
705 struct gk20a *g = platform->g; 700 struct gk20a *g = platform->g;
706 nvhost_debug_dump_device(g->host1x_dev); 701 nvhost_debug_dump_device(g->host1x_dev);
707} 702}
708 703
709int gk20a_tegra_busy(struct platform_device *dev) 704int gk20a_tegra_busy(struct device *dev)
710{ 705{
711 struct gk20a_platform *platform = gk20a_get_platform(dev); 706 struct gk20a_platform *platform = gk20a_get_platform(dev);
712 struct gk20a *g = platform->g; 707 struct gk20a *g = platform->g;
@@ -716,7 +711,7 @@ int gk20a_tegra_busy(struct platform_device *dev)
716 return 0; 711 return 0;
717} 712}
718 713
719void gk20a_tegra_idle(struct platform_device *dev) 714void gk20a_tegra_idle(struct device *dev)
720{ 715{
721 struct gk20a_platform *platform = gk20a_get_platform(dev); 716 struct gk20a_platform *platform = gk20a_get_platform(dev);
722 struct gk20a *g = platform->g; 717 struct gk20a *g = platform->g;
@@ -725,10 +720,10 @@ void gk20a_tegra_idle(struct platform_device *dev)
725 nvhost_module_idle_ext(g->host1x_dev); 720 nvhost_module_idle_ext(g->host1x_dev);
726} 721}
727 722
728static int gk20a_tegra_probe(struct platform_device *dev) 723static int gk20a_tegra_probe(struct device *dev)
729{ 724{
730 struct gk20a_platform *platform = gk20a_get_platform(dev); 725 struct gk20a_platform *platform = dev_get_drvdata(dev);
731 struct device_node *np = dev->dev.of_node; 726 struct device_node *np = dev->of_node;
732 const __be32 *host1x_ptr; 727 const __be32 *host1x_ptr;
733 struct platform_device *host1x_pdev = NULL; 728 struct platform_device *host1x_pdev = NULL;
734 729
@@ -739,13 +734,13 @@ static int gk20a_tegra_probe(struct platform_device *dev)
739 734
740 host1x_pdev = of_find_device_by_node(host1x_node); 735 host1x_pdev = of_find_device_by_node(host1x_node);
741 if (!host1x_pdev) { 736 if (!host1x_pdev) {
742 dev_warn(&dev->dev, "host1x device not available"); 737 dev_warn(dev, "host1x device not available");
743 return -EPROBE_DEFER; 738 return -EPROBE_DEFER;
744 } 739 }
745 740
746 } else { 741 } else {
747 host1x_pdev = to_platform_device(dev->dev.parent); 742 host1x_pdev = to_platform_device(dev->parent);
748 dev_warn(&dev->dev, "host1x reference not found. assuming host1x to be parent"); 743 dev_warn(dev, "host1x reference not found. assuming host1x to be parent");
749 } 744 }
750 745
751 platform->g->host1x_dev = host1x_pdev; 746 platform->g->host1x_dev = host1x_pdev;
@@ -761,7 +756,7 @@ static int gk20a_tegra_probe(struct platform_device *dev)
761 np = of_find_node_by_path("/gpu-dvfs-rework"); 756 np = of_find_node_by_path("/gpu-dvfs-rework");
762 if (!(np && of_device_is_available(np))) { 757 if (!(np && of_device_is_available(np))) {
763 platform->devfreq_governor = ""; 758 platform->devfreq_governor = "";
764 dev_warn(&dev->dev, "board does not support scaling"); 759 dev_warn(dev, "board does not support scaling");
765 } 760 }
766 } 761 }
767 762
@@ -770,10 +765,10 @@ static int gk20a_tegra_probe(struct platform_device *dev)
770 return 0; 765 return 0;
771} 766}
772 767
773static int gk20a_tegra_late_probe(struct platform_device *dev) 768static int gk20a_tegra_late_probe(struct device *dev)
774{ 769{
775 /* Make gk20a power domain a subdomain of host1x */ 770 /* Make gk20a power domain a subdomain of host1x */
776 nvhost_register_client_domain(dev_to_genpd(&dev->dev)); 771 nvhost_register_client_domain(dev_to_genpd(dev));
777 772
778 /* Initialise tegra specific scaling quirks */ 773 /* Initialise tegra specific scaling quirks */
779 gk20a_tegra_scale_init(dev); 774 gk20a_tegra_scale_init(dev);
@@ -781,15 +776,15 @@ static int gk20a_tegra_late_probe(struct platform_device *dev)
781 return 0; 776 return 0;
782} 777}
783 778
784static int gk20a_tegra_remove(struct platform_device *dev) 779static int gk20a_tegra_remove(struct device *dev)
785{ 780{
786 struct gk20a_platform *platform = gk20a_get_platform(dev); 781 struct gk20a_platform *platform = dev_get_drvdata(dev);
787 782
788 if (platform->g->host1x_dev) 783 if (platform->g->host1x_dev)
789 nvhost_unregister_dump_device(platform->g->host1x_dev); 784 nvhost_unregister_dump_device(platform->g->host1x_dev);
790 785
791 /* remove gk20a power subdomain from host1x */ 786 /* remove gk20a power subdomain from host1x */
792 nvhost_unregister_client_domain(dev_to_genpd(&dev->dev)); 787 nvhost_unregister_client_domain(dev_to_genpd(dev));
793 788
794 /* deinitialise tegra specific scaling quirks */ 789 /* deinitialise tegra specific scaling quirks */
795 gk20a_tegra_scale_exit(dev); 790 gk20a_tegra_scale_exit(dev);
@@ -804,7 +799,7 @@ static int gk20a_tegra_suspend(struct device *dev)
804} 799}
805 800
806#ifdef CONFIG_TEGRA_CLK_FRAMEWORK 801#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
807static unsigned long gk20a_get_clk_rate(struct platform_device *dev) 802static unsigned long gk20a_get_clk_rate(struct device *dev)
808{ 803{
809 struct gk20a_platform *platform = gk20a_get_platform(dev); 804 struct gk20a_platform *platform = gk20a_get_platform(dev);
810 struct gk20a *g = platform->g; 805 struct gk20a *g = platform->g;
@@ -813,8 +808,7 @@ static unsigned long gk20a_get_clk_rate(struct platform_device *dev)
813 808
814} 809}
815 810
816static long gk20a_round_clk_rate(struct platform_device *dev, 811static long gk20a_round_clk_rate(struct device *dev, unsigned long rate)
817 unsigned long rate)
818{ 812{
819 struct gk20a_platform *platform = gk20a_get_platform(dev); 813 struct gk20a_platform *platform = gk20a_get_platform(dev);
820 struct gk20a *g = platform->g; 814 struct gk20a *g = platform->g;
@@ -822,7 +816,7 @@ static long gk20a_round_clk_rate(struct platform_device *dev,
822 return gk20a_clk_round_rate(g, rate); 816 return gk20a_clk_round_rate(g, rate);
823} 817}
824 818
825static int gk20a_set_clk_rate(struct platform_device *dev, unsigned long rate) 819static int gk20a_set_clk_rate(struct device *dev, unsigned long rate)
826{ 820{
827 struct gk20a_platform *platform = gk20a_get_platform(dev); 821 struct gk20a_platform *platform = gk20a_get_platform(dev);
828 struct gk20a *g = platform->g; 822 struct gk20a *g = platform->g;
@@ -830,7 +824,7 @@ static int gk20a_set_clk_rate(struct platform_device *dev, unsigned long rate)
830 return gk20a_clk_set_rate(g, rate); 824 return gk20a_clk_set_rate(g, rate);
831} 825}
832 826
833static int gk20a_clk_get_freqs(struct platform_device *dev, 827static int gk20a_clk_get_freqs(struct device *dev,
834 unsigned long **freqs, int *num_freqs) 828 unsigned long **freqs, int *num_freqs)
835{ 829{
836 struct gk20a_platform *platform = gk20a_get_platform(dev); 830 struct gk20a_platform *platform = gk20a_get_platform(dev);
@@ -900,6 +894,8 @@ struct gk20a_platform gk20a_tegra_platform = {
900 .secure_alloc = gk20a_tegra_secure_alloc, 894 .secure_alloc = gk20a_tegra_secure_alloc,
901 .secure_page_alloc = gk20a_tegra_secure_page_alloc, 895 .secure_page_alloc = gk20a_tegra_secure_page_alloc,
902 .dump_platform_dependencies = gk20a_tegra_debug_dump, 896 .dump_platform_dependencies = gk20a_tegra_debug_dump,
897
898 .soc_name = "tegra12x",
903}; 899};
904 900
905struct gk20a_platform gm20b_tegra_platform = { 901struct gk20a_platform gm20b_tegra_platform = {
@@ -958,4 +954,6 @@ struct gk20a_platform gm20b_tegra_platform = {
958 .dump_platform_dependencies = gk20a_tegra_debug_dump, 954 .dump_platform_dependencies = gk20a_tegra_debug_dump,
959 955
960 .has_cde = true, 956 .has_cde = true,
957
958 .soc_name = "tegra21x",
961}; 959};
diff --git a/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c
index ed65756a..bb8d05b8 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c
+++ b/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Tegra Virtualized GPU Platform Interface 2 * Tegra Virtualized GPU Platform Interface
3 * 3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -19,10 +19,10 @@
19#include "hal_gk20a.h" 19#include "hal_gk20a.h"
20#include "platform_gk20a.h" 20#include "platform_gk20a.h"
21 21
22static int gk20a_tegra_probe(struct platform_device *dev) 22static int gk20a_tegra_probe(struct device *dev)
23{ 23{
24 struct gk20a_platform *platform = gk20a_get_platform(dev); 24 struct gk20a_platform *platform = dev_get_drvdata(dev);
25 struct device_node *np = dev->dev.of_node; 25 struct device_node *np = dev->of_node;
26 const __be32 *host1x_ptr; 26 const __be32 *host1x_ptr;
27 struct platform_device *host1x_pdev = NULL; 27 struct platform_device *host1x_pdev = NULL;
28 28
@@ -33,13 +33,13 @@ static int gk20a_tegra_probe(struct platform_device *dev)
33 33
34 host1x_pdev = of_find_device_by_node(host1x_node); 34 host1x_pdev = of_find_device_by_node(host1x_node);
35 if (!host1x_pdev) { 35 if (!host1x_pdev) {
36 dev_warn(&dev->dev, "host1x device not available"); 36 dev_warn(dev, "host1x device not available");
37 return -EPROBE_DEFER; 37 return -EPROBE_DEFER;
38 } 38 }
39 39
40 } else { 40 } else {
41 host1x_pdev = to_platform_device(dev->dev.parent); 41 host1x_pdev = to_platform_device(dev->parent);
42 dev_warn(&dev->dev, "host1x reference not found. assuming host1x to be parent"); 42 dev_warn(dev, "host1x reference not found. assuming host1x to be parent");
43 } 43 }
44 44
45 platform->g->host1x_dev = host1x_pdev; 45 platform->g->host1x_dev = host1x_pdev;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 4edfe90c..3b154f30 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -1814,7 +1814,7 @@ int pmu_reset(struct pmu_gk20a *pmu)
1814int pmu_bootstrap(struct pmu_gk20a *pmu) 1814int pmu_bootstrap(struct pmu_gk20a *pmu)
1815{ 1815{
1816 struct gk20a *g = gk20a_from_pmu(pmu); 1816 struct gk20a *g = gk20a_from_pmu(pmu);
1817 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 1817 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
1818 struct mm_gk20a *mm = &g->mm; 1818 struct mm_gk20a *mm = &g->mm;
1819 struct pmu_ucode_desc *desc = pmu->desc; 1819 struct pmu_ucode_desc *desc = pmu->desc;
1820 u64 addr_code, addr_data, addr_load; 1820 u64 addr_code, addr_data, addr_load;
@@ -2955,7 +2955,7 @@ static u8 get_perfmon_id(struct pmu_gk20a *pmu)
2955 break; 2955 break;
2956#endif 2956#endif
2957 default: 2957 default:
2958 gk20a_err(&g->dev->dev, "no support for %x", ver); 2958 gk20a_err(g->dev, "no support for %x", ver);
2959 BUG(); 2959 BUG();
2960 } 2960 }
2961 2961
@@ -4667,10 +4667,10 @@ static const struct file_operations security_fops = {
4667 .release = single_release, 4667 .release = single_release,
4668}; 4668};
4669 4669
4670int gk20a_pmu_debugfs_init(struct platform_device *dev) 4670int gk20a_pmu_debugfs_init(struct device *dev)
4671{ 4671{
4672 struct dentry *d; 4672 struct dentry *d;
4673 struct gk20a_platform *platform = platform_get_drvdata(dev); 4673 struct gk20a_platform *platform = dev_get_drvdata(dev);
4674 struct gk20a *g = get_gk20a(dev); 4674 struct gk20a *g = get_gk20a(dev);
4675 4675
4676 d = debugfs_create_file( 4676 d = debugfs_create_file(
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index c533ba8d..4edb3283 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -1394,7 +1394,7 @@ int pmu_mutex_release(struct pmu_gk20a *pmu, u32 id, u32 *token);
1394int gk20a_pmu_destroy(struct gk20a *g); 1394int gk20a_pmu_destroy(struct gk20a *g);
1395int gk20a_pmu_load_norm(struct gk20a *g, u32 *load); 1395int gk20a_pmu_load_norm(struct gk20a *g, u32 *load);
1396int gk20a_pmu_load_update(struct gk20a *g); 1396int gk20a_pmu_load_update(struct gk20a *g);
1397int gk20a_pmu_debugfs_init(struct platform_device *dev); 1397int gk20a_pmu_debugfs_init(struct device *dev);
1398void gk20a_pmu_reset_load_counters(struct gk20a *g); 1398void gk20a_pmu_reset_load_counters(struct gk20a *g);
1399void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, 1399void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
1400 u32 *total_cycles); 1400 u32 *total_cycles);
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index a9c7fdfd..fda480cf 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -400,7 +400,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
400 * regops implementation, so we return -ENOSYS. This will allow 400 * regops implementation, so we return -ENOSYS. This will allow
401 * compute apps to run with vgpu. Tools will not work in this 401 * compute apps to run with vgpu. Tools will not work in this
402 * configuration and are not required to work at this time. */ 402 * configuration and are not required to work at this time. */
403 if (gk20a_gpu_is_virtual(dbg_s->pdev)) 403 if (gk20a_gpu_is_virtual(dbg_s->dev))
404 return -ENOSYS; 404 return -ENOSYS;
405 405
406 ok = validate_reg_ops(dbg_s, 406 ok = validate_reg_ops(dbg_s,
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 51e6407c..7b98c80f 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -470,7 +470,7 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
470 { 470 {
471 err = gk20a_busy(g->dev); 471 err = gk20a_busy(g->dev);
472 if (err) { 472 if (err) {
473 gk20a_err(&g->dev->dev, 473 gk20a_err(g->dev,
474 "failed to host gk20a for ioctl cmd: 0x%x", cmd); 474 "failed to host gk20a for ioctl cmd: 0x%x", cmd);
475 return err; 475 return err;
476 } 476 }
@@ -483,7 +483,7 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
483 { 483 {
484 err = gk20a_busy(g->dev); 484 err = gk20a_busy(g->dev);
485 if (err) { 485 if (err) {
486 gk20a_err(&g->dev->dev, 486 gk20a_err(g->dev,
487 "failed to host gk20a for ioctl cmd: 0x%x", cmd); 487 "failed to host gk20a for ioctl cmd: 0x%x", cmd);
488 return err; 488 return err;
489 } 489 }
@@ -496,7 +496,7 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
496 { 496 {
497 err = gk20a_busy(g->dev); 497 err = gk20a_busy(g->dev);
498 if (err) { 498 if (err) {
499 gk20a_err(&g->dev->dev, 499 gk20a_err(g->dev,
500 "failed to host gk20a for ioctl cmd: 0x%x", cmd); 500 "failed to host gk20a for ioctl cmd: 0x%x", cmd);
501 return err; 501 return err;
502 } 502 }
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 8a0be106..79f90f0b 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1257,7 +1257,7 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
1257 1257
1258 struct pmu_gk20a *pmu = &g->pmu; 1258 struct pmu_gk20a *pmu = &g->pmu;
1259 int err; 1259 int err;
1260 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 1260 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
1261 1261
1262 gk20a_dbg_fn(""); 1262 gk20a_dbg_fn("");
1263 1263
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 16f929a8..54406008 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B Clocks 2 * GM20B Clocks
3 * 3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -1651,7 +1651,7 @@ static const struct file_operations pll_param_fops = {
1651static int clk_gm20b_debugfs_init(struct gk20a *g) 1651static int clk_gm20b_debugfs_init(struct gk20a *g)
1652{ 1652{
1653 struct dentry *d; 1653 struct dentry *d;
1654 struct gk20a_platform *platform = platform_get_drvdata(g->dev); 1654 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
1655 1655
1656 d = debugfs_create_file( 1656 d = debugfs_create_file(
1657 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops); 1657 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops);
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index ffc36903..e4e27764 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -112,7 +112,7 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
112 112
113 gk20a_dbg_fn(""); 113 gk20a_dbg_fn("");
114 114
115 trace_gk20a_ltc_cbc_ctrl_start(g->dev->name, op, min, max); 115 trace_gk20a_ltc_cbc_ctrl_start(dev_name(g->dev), op, min, max);
116 116
117 if (gr->compbit_store.mem.size == 0) 117 if (gr->compbit_store.mem.size == 0)
118 return 0; 118 return 0;
@@ -162,7 +162,7 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
162 } 162 }
163 } 163 }
164out: 164out:
165 trace_gk20a_ltc_cbc_ctrl_done(g->dev->name); 165 trace_gk20a_ltc_cbc_ctrl_done(dev_name(g->dev));
166 mutex_unlock(&g->mm.l2_op_lock); 166 mutex_unlock(&g->mm.l2_op_lock);
167 return err; 167 return err;
168} 168}
@@ -230,7 +230,7 @@ void gm20b_ltc_g_elpg_flush_locked(struct gk20a *g)
230 230
231 gk20a_dbg_fn(""); 231 gk20a_dbg_fn("");
232 232
233 trace_gk20a_mm_g_elpg_flush_locked(g->dev->name); 233 trace_gk20a_mm_g_elpg_flush_locked(dev_name(g->dev));
234 234
235 for (i = 0; i < g->ltc_count; i++) 235 for (i = 0; i < g->ltc_count; i++)
236 done[i] = 0; 236 done[i] = 0;
@@ -264,7 +264,7 @@ void gm20b_ltc_g_elpg_flush_locked(struct gk20a *g)
264 gk20a_warn(dev_from_gk20a(g), 264 gk20a_warn(dev_from_gk20a(g),
265 "g_elpg_flush too many retries"); 265 "g_elpg_flush too many retries");
266 266
267 trace_gk20a_mm_g_elpg_flush_locked_done(g->dev->name); 267 trace_gk20a_mm_g_elpg_flush_locked_done(dev_name(g->dev));
268} 268}
269 269
270u32 gm20b_ltc_cbc_fix_config(struct gk20a *g, int base) 270u32 gm20b_ltc_cbc_fix_config(struct gk20a *g, int base)
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index 621ee687..7bc19972 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B MMU 2 * GM20B MMU
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -52,7 +52,7 @@ int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g)
52 52
53 gk20a_busy_noresume(g->dev); 53 gk20a_busy_noresume(g->dev);
54#ifdef CONFIG_PM 54#ifdef CONFIG_PM
55 if (!pm_runtime_active(&g->dev->dev)) 55 if (!pm_runtime_active(g->dev))
56 goto fail; 56 goto fail;
57#endif 57#endif
58 58
@@ -67,7 +67,7 @@ int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g)
67 ret = gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); 67 ret = gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT);
68 68
69fail: 69fail:
70 pm_runtime_put(&g->dev->dev); 70 pm_runtime_put(g->dev);
71 return ret; 71 return ret;
72} 72}
73 73
diff --git a/drivers/gpu/nvgpu/platform_tegra.h b/drivers/gpu/nvgpu/platform_tegra.h
index 6fa13831..815ac657 100644
--- a/drivers/gpu/nvgpu/platform_tegra.h
+++ b/drivers/gpu/nvgpu/platform_tegra.h
@@ -1,9 +1,7 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/soc/platform_gk20a.h
3 *
4 * GK20A Platform (SoC) Interface 2 * GK20A Platform (SoC) Interface
5 * 3 *
6 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
7 * 5 *
8 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -23,9 +21,9 @@
23struct platform_device; 21struct platform_device;
24struct gr_ctx_buffer_desc; 22struct gr_ctx_buffer_desc;
25 23
26int gk20a_tegra_secure_alloc(struct platform_device *pdev, 24int gk20a_tegra_secure_alloc(struct device *dev,
27 struct gr_ctx_buffer_desc *desc, 25 struct gr_ctx_buffer_desc *desc,
28 size_t size); 26 size_t size);
29int gk20a_tegra_secure_page_alloc(struct platform_device *pdev); 27int gk20a_tegra_secure_page_alloc(struct device *dev);
30 28
31#endif 29#endif
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index ab063c9b..b67f4d95 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -140,7 +140,7 @@ static int vgpu_intr_thread(void *dev_id)
140 return 0; 140 return 0;
141} 141}
142 142
143static void vgpu_remove_support(struct platform_device *dev) 143static void vgpu_remove_support(struct device *dev)
144{ 144{
145 struct gk20a *g = get_gk20a(dev); 145 struct gk20a *g = get_gk20a(dev);
146 struct gk20a_platform *platform = gk20a_get_platform(dev); 146 struct gk20a_platform *platform = gk20a_get_platform(dev);
@@ -174,10 +174,10 @@ static void vgpu_remove_support(struct platform_device *dev)
174 } 174 }
175} 175}
176 176
177static int vgpu_init_support(struct platform_device *dev) 177static int vgpu_init_support(struct platform_device *pdev)
178{ 178{
179 struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, 0); 179 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
180 struct gk20a *g = get_gk20a(dev); 180 struct gk20a *g = get_gk20a(&pdev->dev);
181 int err = 0; 181 int err = 0;
182 182
183 if (!r) { 183 if (!r) {
@@ -186,7 +186,7 @@ static int vgpu_init_support(struct platform_device *dev)
186 goto fail; 186 goto fail;
187 } 187 }
188 188
189 g->bar1 = devm_ioremap_resource(&dev->dev, r); 189 g->bar1 = devm_ioremap_resource(&pdev->dev, r);
190 if (IS_ERR(g->bar1)) { 190 if (IS_ERR(g->bar1)) {
191 dev_err(dev_from_gk20a(g), "failed to remap gk20a bar1\n"); 191 dev_err(dev_from_gk20a(g), "failed to remap gk20a bar1\n");
192 err = PTR_ERR(g->bar1); 192 err = PTR_ERR(g->bar1);
@@ -200,14 +200,13 @@ static int vgpu_init_support(struct platform_device *dev)
200 return 0; 200 return 0;
201 201
202 fail: 202 fail:
203 vgpu_remove_support(dev); 203 vgpu_remove_support(&pdev->dev);
204 return err; 204 return err;
205} 205}
206 206
207int vgpu_pm_prepare_poweroff(struct device *dev) 207int vgpu_pm_prepare_poweroff(struct device *dev)
208{ 208{
209 struct platform_device *pdev = to_platform_device(dev); 209 struct gk20a *g = get_gk20a(dev);
210 struct gk20a *g = get_gk20a(pdev);
211 int ret = 0; 210 int ret = 0;
212 211
213 gk20a_dbg_fn(""); 212 gk20a_dbg_fn("");
@@ -284,7 +283,7 @@ static int vgpu_init_hal(struct gk20a *g)
284 break; 283 break;
285#endif 284#endif
286 default: 285 default:
287 gk20a_err(&g->dev->dev, "no support for %x", ver); 286 gk20a_err(g->dev, "no support for %x", ver);
288 err = -ENODEV; 287 err = -ENODEV;
289 break; 288 break;
290 } 289 }
@@ -294,8 +293,7 @@ static int vgpu_init_hal(struct gk20a *g)
294 293
295int vgpu_pm_finalize_poweron(struct device *dev) 294int vgpu_pm_finalize_poweron(struct device *dev)
296{ 295{
297 struct platform_device *pdev = to_platform_device(dev); 296 struct gk20a *g = get_gk20a(dev);
298 struct gk20a *g = get_gk20a(pdev);
299 int err; 297 int err;
300 298
301 gk20a_dbg_fn(""); 299 gk20a_dbg_fn("");
@@ -342,9 +340,9 @@ done:
342 return err; 340 return err;
343} 341}
344 342
345static int vgpu_pm_initialise_domain(struct platform_device *pdev) 343static int vgpu_pm_initialise_domain(struct device *dev)
346{ 344{
347 struct gk20a_platform *platform = platform_get_drvdata(pdev); 345 struct gk20a_platform *platform = dev_get_drvdata(dev);
348 struct dev_power_governor *pm_domain_gov = NULL; 346 struct dev_power_governor *pm_domain_gov = NULL;
349 struct gk20a_domain_data *vgpu_pd_data; 347 struct gk20a_domain_data *vgpu_pd_data;
350 struct generic_pm_domain *domain; 348 struct generic_pm_domain *domain;
@@ -369,17 +367,17 @@ static int vgpu_pm_initialise_domain(struct platform_device *pdev)
369 domain->dev_ops.save_state = vgpu_pm_prepare_poweroff; 367 domain->dev_ops.save_state = vgpu_pm_prepare_poweroff;
370 domain->dev_ops.restore_state = vgpu_pm_finalize_poweron; 368 domain->dev_ops.restore_state = vgpu_pm_finalize_poweron;
371 369
372 device_set_wakeup_capable(&pdev->dev, 0); 370 device_set_wakeup_capable(dev, 0);
373 return pm_genpd_add_device(domain, &pdev->dev); 371 return pm_genpd_add_device(domain, dev);
374} 372}
375 373
376static int vgpu_pm_init(struct platform_device *dev) 374static int vgpu_pm_init(struct device *dev)
377{ 375{
378 int err = 0; 376 int err = 0;
379 377
380 gk20a_dbg_fn(""); 378 gk20a_dbg_fn("");
381 379
382 pm_runtime_enable(&dev->dev); 380 pm_runtime_enable(dev);
383 381
384 /* genpd will take care of runtime power management if it is enabled */ 382 /* genpd will take care of runtime power management if it is enabled */
385 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) 383 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
@@ -388,14 +386,15 @@ static int vgpu_pm_init(struct platform_device *dev)
388 return err; 386 return err;
389} 387}
390 388
391int vgpu_probe(struct platform_device *dev) 389int vgpu_probe(struct platform_device *pdev)
392{ 390{
393 struct gk20a *gk20a; 391 struct gk20a *gk20a;
394 int err; 392 int err;
393 struct device *dev = &pdev->dev;
395 struct gk20a_platform *platform = gk20a_get_platform(dev); 394 struct gk20a_platform *platform = gk20a_get_platform(dev);
396 395
397 if (!platform) { 396 if (!platform) {
398 dev_err(&dev->dev, "no platform data\n"); 397 dev_err(dev, "no platform data\n");
399 return -ENODATA; 398 return -ENODATA;
400 } 399 }
401 400
@@ -403,18 +402,18 @@ int vgpu_probe(struct platform_device *dev)
403 402
404 gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL); 403 gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL);
405 if (!gk20a) { 404 if (!gk20a) {
406 dev_err(&dev->dev, "couldn't allocate gk20a support"); 405 dev_err(dev, "couldn't allocate gk20a support");
407 return -ENOMEM; 406 return -ENOMEM;
408 } 407 }
409 408
410 platform->g = gk20a; 409 platform->g = gk20a;
411 gk20a->dev = dev; 410 gk20a->dev = dev;
412 411
413 err = gk20a_user_init(dev); 412 err = gk20a_user_init(dev, INTERFACE_NAME);
414 if (err) 413 if (err)
415 return err; 414 return err;
416 415
417 vgpu_init_support(dev); 416 vgpu_init_support(pdev);
418 vgpu_dbg_init(); 417 vgpu_dbg_init();
419 418
420 init_rwsem(&gk20a->busy_lock); 419 init_rwsem(&gk20a->busy_lock);
@@ -424,33 +423,33 @@ int vgpu_probe(struct platform_device *dev)
424 /* Initialize the platform interface. */ 423 /* Initialize the platform interface. */
425 err = platform->probe(dev); 424 err = platform->probe(dev);
426 if (err) { 425 if (err) {
427 dev_err(&dev->dev, "platform probe failed"); 426 dev_err(dev, "platform probe failed");
428 return err; 427 return err;
429 } 428 }
430 429
431 err = vgpu_pm_init(dev); 430 err = vgpu_pm_init(dev);
432 if (err) { 431 if (err) {
433 dev_err(&dev->dev, "pm init failed"); 432 dev_err(dev, "pm init failed");
434 return err; 433 return err;
435 } 434 }
436 435
437 if (platform->late_probe) { 436 if (platform->late_probe) {
438 err = platform->late_probe(dev); 437 err = platform->late_probe(dev);
439 if (err) { 438 if (err) {
440 dev_err(&dev->dev, "late probe failed"); 439 dev_err(dev, "late probe failed");
441 return err; 440 return err;
442 } 441 }
443 } 442 }
444 443
445 err = vgpu_comm_init(dev); 444 err = vgpu_comm_init(pdev);
446 if (err) { 445 if (err) {
447 dev_err(&dev->dev, "failed to init comm interface\n"); 446 dev_err(dev, "failed to init comm interface\n");
448 return -ENOSYS; 447 return -ENOSYS;
449 } 448 }
450 449
451 platform->virt_handle = vgpu_connect(); 450 platform->virt_handle = vgpu_connect();
452 if (!platform->virt_handle) { 451 if (!platform->virt_handle) {
453 dev_err(&dev->dev, "failed to connect to server node\n"); 452 dev_err(dev, "failed to connect to server node\n");
454 vgpu_comm_deinit(); 453 vgpu_comm_deinit();
455 return -ENOSYS; 454 return -ENOSYS;
456 } 455 }
@@ -462,8 +461,8 @@ int vgpu_probe(struct platform_device *dev)
462 gk20a_debug_init(dev); 461 gk20a_debug_init(dev);
463 462
464 /* Set DMA parameters to allow larger sgt lists */ 463 /* Set DMA parameters to allow larger sgt lists */
465 dev->dev.dma_parms = &gk20a->dma_parms; 464 dev->dma_parms = &gk20a->dma_parms;
466 dma_set_max_seg_size(&dev->dev, UINT_MAX); 465 dma_set_max_seg_size(dev, UINT_MAX);
467 466
468 gk20a->gr_idle_timeout_default = 467 gk20a->gr_idle_timeout_default =
469 CONFIG_GK20A_DEFAULT_TIMEOUT; 468 CONFIG_GK20A_DEFAULT_TIMEOUT;
@@ -475,8 +474,9 @@ int vgpu_probe(struct platform_device *dev)
475 return 0; 474 return 0;
476} 475}
477 476
478int vgpu_remove(struct platform_device *dev) 477int vgpu_remove(struct platform_device *pdev)
479{ 478{
479 struct device *dev = &pdev->dev;
480 struct gk20a *g = get_gk20a(dev); 480 struct gk20a *g = get_gk20a(dev);
481 struct gk20a_domain_data *vgpu_gpd; 481 struct gk20a_domain_data *vgpu_gpd;
482 gk20a_dbg_fn(""); 482 gk20a_dbg_fn("");