diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-07-04 01:55:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 03:39:21 -0400 |
commit | e808d345f11885453fc65862ec4e3dd4a375ff6d (patch) | |
tree | ccc3bb1ade5ff991ca1805084b76f154ca9736ee /drivers | |
parent | 2cf964d175abc0f3eae9ed0e01e6eeed5cd6b4da (diff) |
gpu: nvgpu: rename gk20a_pmu_cmd_post()
- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
wherever called.
JIRA NVGPU-93
Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/boardobj/boardobjgrp.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_pg.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/mclk_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/lpwr.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/perf.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/therm/thrmpmu.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.c | 2 |
17 files changed, 35 insertions, 35 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c index b3e1354d..a6c07180 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c | |||
@@ -744,7 +744,7 @@ static u32 boardobjgrp_pmucmdsend(struct gk20a *g, | |||
744 | handlerparams.pcmd = pcmd; | 744 | handlerparams.pcmd = pcmd; |
745 | handlerparams.success = 0; | 745 | handlerparams.success = 0; |
746 | 746 | ||
747 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 747 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
748 | PMU_COMMAND_QUEUE_LPQ, | 748 | PMU_COMMAND_QUEUE_LPQ, |
749 | boardobjgrp_pmucmdhandler, | 749 | boardobjgrp_pmucmdhandler, |
750 | (void *)&handlerparams, | 750 | (void *)&handlerparams, |
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 72b6d246..494a09cf 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -97,7 +97,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) | |||
97 | 97 | ||
98 | handler.prpccall = &rpccall; | 98 | handler.prpccall = &rpccall; |
99 | handler.success = 0; | 99 | handler.success = 0; |
100 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 100 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
101 | PMU_COMMAND_QUEUE_LPQ, | 101 | PMU_COMMAND_QUEUE_LPQ, |
102 | clkrpc_pmucmdhandler, (void *)&handler, | 102 | clkrpc_pmucmdhandler, (void *)&handler, |
103 | &seqdesc, ~0); | 103 | &seqdesc, ~0); |
@@ -160,7 +160,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) | |||
160 | 160 | ||
161 | handler.prpccall = &rpccall; | 161 | handler.prpccall = &rpccall; |
162 | handler.success = 0; | 162 | handler.success = 0; |
163 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 163 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
164 | PMU_COMMAND_QUEUE_LPQ, | 164 | PMU_COMMAND_QUEUE_LPQ, |
165 | clkrpc_pmucmdhandler, (void *)&handler, | 165 | clkrpc_pmucmdhandler, (void *)&handler, |
166 | &seqdesc, ~0); | 166 | &seqdesc, ~0); |
@@ -262,7 +262,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
262 | handler.prpccall = &rpccall; | 262 | handler.prpccall = &rpccall; |
263 | handler.success = 0; | 263 | handler.success = 0; |
264 | 264 | ||
265 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 265 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
266 | PMU_COMMAND_QUEUE_LPQ, | 266 | PMU_COMMAND_QUEUE_LPQ, |
267 | clkrpc_pmucmdhandler, (void *)&handler, | 267 | clkrpc_pmucmdhandler, (void *)&handler, |
268 | &seqdesc, ~0); | 268 | &seqdesc, ~0); |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 5edfe4cd..dcf6db9c 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -478,7 +478,7 @@ clean_up: | |||
478 | return err; | 478 | return err; |
479 | } | 479 | } |
480 | 480 | ||
481 | int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | 481 | int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, |
482 | struct pmu_msg *msg, struct pmu_payload *payload, | 482 | struct pmu_msg *msg, struct pmu_payload *payload, |
483 | u32 queue_id, pmu_callback callback, void *cb_param, | 483 | u32 queue_id, pmu_callback callback, void *cb_param, |
484 | u32 *seq_desc, unsigned long timeout) | 484 | u32 *seq_desc, unsigned long timeout) |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 750906ce..f87bd175 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | |||
@@ -112,7 +112,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu) | |||
112 | payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC); | 112 | payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC); |
113 | 113 | ||
114 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT"); | 114 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT"); |
115 | gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, | 115 | nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, |
116 | NULL, NULL, &seq, ~0); | 116 | NULL, NULL, &seq, ~0); |
117 | 117 | ||
118 | return 0; | 118 | return 0; |
@@ -160,7 +160,7 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu) | |||
160 | pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC); | 160 | pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC); |
161 | 161 | ||
162 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START"); | 162 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START"); |
163 | gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, | 163 | nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, |
164 | NULL, NULL, &seq, ~0); | 164 | NULL, NULL, &seq, ~0); |
165 | 165 | ||
166 | return 0; | 166 | return 0; |
@@ -183,7 +183,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu) | |||
183 | cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; | 183 | cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; |
184 | 184 | ||
185 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP"); | 185 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP"); |
186 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, | 186 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, |
187 | NULL, NULL, &seq, ~0); | 187 | NULL, NULL, &seq, ~0); |
188 | return 0; | 188 | return 0; |
189 | } | 189 | } |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 47ac8b64..06dab8ea 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c | |||
@@ -151,7 +151,7 @@ static int pmu_enable_elpg_locked(struct gk20a *g, u32 pg_engine_id) | |||
151 | pmu->mscg_transition_state = PMU_ELPG_STAT_ON_PENDING; | 151 | pmu->mscg_transition_state = PMU_ELPG_STAT_ON_PENDING; |
152 | 152 | ||
153 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_ALLOW"); | 153 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_ALLOW"); |
154 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 154 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, |
155 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, | 155 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, |
156 | pmu, &seq, ~0); | 156 | pmu, &seq, ~0); |
157 | WARN_ON(status != 0); | 157 | WARN_ON(status != 0); |
@@ -305,7 +305,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) | |||
305 | ptr = &pmu->mscg_transition_state; | 305 | ptr = &pmu->mscg_transition_state; |
306 | 306 | ||
307 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW"); | 307 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW"); |
308 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 308 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, |
309 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, | 309 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, |
310 | pmu, &seq, ~0); | 310 | pmu, &seq, ~0); |
311 | 311 | ||
@@ -376,7 +376,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
376 | cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_INIT; | 376 | cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_INIT; |
377 | 377 | ||
378 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_INIT"); | 378 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_INIT"); |
379 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 379 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
380 | pmu_handle_pg_elpg_msg, pmu, &seq, ~0); | 380 | pmu_handle_pg_elpg_msg, pmu, &seq, ~0); |
381 | 381 | ||
382 | /* alloc dmem for powergating state log */ | 382 | /* alloc dmem for powergating state log */ |
@@ -390,7 +390,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
390 | cmd.cmd.pg.stat.data = 0; | 390 | cmd.cmd.pg.stat.data = 0; |
391 | 391 | ||
392 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_STAT_CMD_ALLOC_DMEM"); | 392 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_STAT_CMD_ALLOC_DMEM"); |
393 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, | 393 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, |
394 | pmu_handle_pg_stat_msg, pmu, &seq, ~0); | 394 | pmu_handle_pg_stat_msg, pmu, &seq, ~0); |
395 | 395 | ||
396 | /* disallow ELPG initially | 396 | /* disallow ELPG initially |
@@ -409,7 +409,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
409 | cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_DISALLOW; | 409 | cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_DISALLOW; |
410 | 410 | ||
411 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW"); | 411 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW"); |
412 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 412 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
413 | pmu_handle_pg_elpg_msg, pmu, &seq, ~0); | 413 | pmu_handle_pg_elpg_msg, pmu, &seq, ~0); |
414 | 414 | ||
415 | if (g->ops.pmu.pmu_pg_set_sub_feature_mask) | 415 | if (g->ops.pmu.pmu_pg_set_sub_feature_mask) |
@@ -508,7 +508,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g) | |||
508 | 508 | ||
509 | pmu->buf_loaded = false; | 509 | pmu->buf_loaded = false; |
510 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS"); | 510 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS"); |
511 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, | 511 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, |
512 | pmu_handle_pg_buf_config_msg, pmu, &desc, ~0); | 512 | pmu_handle_pg_buf_config_msg, pmu, &desc, ~0); |
513 | nvgpu_pmu_state_change(g, PMU_STATE_LOADING_PG_BUF, false); | 513 | nvgpu_pmu_state_change(g, PMU_STATE_LOADING_PG_BUF, false); |
514 | return err; | 514 | return err; |
@@ -544,7 +544,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g) | |||
544 | 544 | ||
545 | pmu->buf_loaded = false; | 545 | pmu->buf_loaded = false; |
546 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC"); | 546 | nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC"); |
547 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, | 547 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, |
548 | pmu_handle_pg_buf_config_msg, pmu, &desc, ~0); | 548 | pmu_handle_pg_buf_config_msg, pmu, &desc, ~0); |
549 | nvgpu_pmu_state_change(g, PMU_STATE_LOADING_ZBC, false); | 549 | nvgpu_pmu_state_change(g, PMU_STATE_LOADING_ZBC, false); |
550 | } | 550 | } |
@@ -662,7 +662,7 @@ int nvgpu_pmu_ap_send_command(struct gk20a *g, | |||
662 | return 0x2f; | 662 | return 0x2f; |
663 | } | 663 | } |
664 | 664 | ||
665 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 665 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
666 | p_callback, pmu, &seq, ~0); | 666 | p_callback, pmu, &seq, ~0); |
667 | 667 | ||
668 | if (status) { | 668 | if (status) { |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 3fc73e42..b3cacb86 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -607,7 +607,7 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) | |||
607 | pmu->zbc_save_done = 0; | 607 | pmu->zbc_save_done = 0; |
608 | 608 | ||
609 | gk20a_dbg_pmu("cmd post ZBC_TABLE_UPDATE"); | 609 | gk20a_dbg_pmu("cmd post ZBC_TABLE_UPDATE"); |
610 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 610 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
611 | pmu_handle_zbc_msg, pmu, &seq, ~0); | 611 | pmu_handle_zbc_msg, pmu, &seq, ~0); |
612 | pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), | 612 | pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), |
613 | &pmu->zbc_save_done, 1); | 613 | &pmu->zbc_save_done, 1); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 3b655b62..ee55c8ef 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -153,7 +153,7 @@ int gm20b_pmu_init_acr(struct gk20a *g) | |||
153 | cmd.cmd.acr.init_wpr.regionid = 0x01; | 153 | cmd.cmd.acr.init_wpr.regionid = 0x01; |
154 | cmd.cmd.acr.init_wpr.wproffset = 0x00; | 154 | cmd.cmd.acr.init_wpr.wproffset = 0x00; |
155 | gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION"); | 155 | gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION"); |
156 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 156 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
157 | pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0); | 157 | pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0); |
158 | 158 | ||
159 | gk20a_dbg_fn("done"); | 159 | gk20a_dbg_fn("done"); |
@@ -217,7 +217,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags) | |||
217 | cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id; | 217 | cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id; |
218 | gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n", | 218 | gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n", |
219 | falcon_id); | 219 | falcon_id); |
220 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 220 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
221 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | 221 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); |
222 | } | 222 | } |
223 | 223 | ||
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c index c4ecdb1d..283847a9 100644 --- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c | |||
@@ -3371,7 +3371,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val) | |||
3371 | reg_alloc); | 3371 | reg_alloc); |
3372 | 3372 | ||
3373 | /* Send command to PMU to execute sequencer script */ | 3373 | /* Send command to PMU to execute sequencer script */ |
3374 | status = gk20a_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload, | 3374 | status = nvgpu_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload, |
3375 | PMU_COMMAND_QUEUE_LPQ, | 3375 | PMU_COMMAND_QUEUE_LPQ, |
3376 | mclk_seq_pmucmdhandler, | 3376 | mclk_seq_pmucmdhandler, |
3377 | &seq_completion_status, &seqdesc, ~0); | 3377 | &seq_completion_status, &seqdesc, ~0); |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index eec89695..a09aa30b 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -126,7 +126,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | |||
126 | PMU_PG_FEATURE_GR_RPPG_ENABLED; | 126 | PMU_PG_FEATURE_GR_RPPG_ENABLED; |
127 | 127 | ||
128 | gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM"); | 128 | gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM"); |
129 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 129 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
130 | pmu_handle_param_msg, pmu, &seq, ~0); | 130 | pmu_handle_param_msg, pmu, &seq, ~0); |
131 | } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { | 131 | } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { |
132 | cmd.hdr.unit_id = PMU_UNIT_PG; | 132 | cmd.hdr.unit_id = PMU_UNIT_PG; |
@@ -143,7 +143,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | |||
143 | NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING; | 143 | NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING; |
144 | 144 | ||
145 | gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM"); | 145 | gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM"); |
146 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 146 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
147 | pmu_handle_param_msg, pmu, &seq, ~0); | 147 | pmu_handle_param_msg, pmu, &seq, ~0); |
148 | } | 148 | } |
149 | 149 | ||
@@ -250,7 +250,7 @@ static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | |||
250 | 250 | ||
251 | gp106_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", | 251 | gp106_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", |
252 | falconidmask); | 252 | falconidmask); |
253 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 253 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
254 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | 254 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); |
255 | } | 255 | } |
256 | 256 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index b086bf1f..dbaf3ebf 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -166,7 +166,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | |||
166 | u64_hi32(g->pmu.wpr_buf.gpu_va); | 166 | u64_hi32(g->pmu.wpr_buf.gpu_va); |
167 | gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", | 167 | gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", |
168 | falconidmask); | 168 | falconidmask); |
169 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 169 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
170 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | 170 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); |
171 | } | 171 | } |
172 | 172 | ||
@@ -242,7 +242,7 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
242 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; | 242 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; |
243 | 243 | ||
244 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); | 244 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); |
245 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 245 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
246 | pmu_handle_gr_param_msg, pmu, &seq, ~0); | 246 | pmu_handle_gr_param_msg, pmu, &seq, ~0); |
247 | 247 | ||
248 | } else | 248 | } else |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 107d2b2d..556d9f39 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -383,7 +383,7 @@ int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id, | |||
383 | bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue); | 383 | bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue); |
384 | 384 | ||
385 | /* send a cmd to pmu */ | 385 | /* send a cmd to pmu */ |
386 | int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | 386 | int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, |
387 | struct pmu_msg *msg, struct pmu_payload *payload, | 387 | struct pmu_msg *msg, struct pmu_payload *payload, |
388 | u32 queue_id, pmu_callback callback, void *cb_param, | 388 | u32 queue_id, pmu_callback callback, void *cb_param, |
389 | u32 *seq_desc, unsigned long timeout); | 389 | u32 *seq_desc, unsigned long timeout); |
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c index 95eea2e3..c80ddee0 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/lpwr/lpwr.c | |||
@@ -243,7 +243,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) | |||
243 | cmd.cmd.pg.mclk_change.data = payload; | 243 | cmd.cmd.pg.mclk_change.data = payload; |
244 | 244 | ||
245 | nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE"); | 245 | nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE"); |
246 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 246 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, |
247 | PMU_COMMAND_QUEUE_HPQ, | 247 | PMU_COMMAND_QUEUE_HPQ, |
248 | nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); | 248 | nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); |
249 | 249 | ||
@@ -276,7 +276,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g) | |||
276 | PMU_PG_PARAM_CMD_POST_INIT; | 276 | PMU_PG_PARAM_CMD_POST_INIT; |
277 | 277 | ||
278 | nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT"); | 278 | nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT"); |
279 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 279 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, |
280 | PMU_COMMAND_QUEUE_LPQ, | 280 | PMU_COMMAND_QUEUE_LPQ, |
281 | nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); | 281 | nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); |
282 | 282 | ||
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index 553457f7..64046040 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c | |||
@@ -73,7 +73,7 @@ static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) | |||
73 | return -1; | 73 | return -1; |
74 | } | 74 | } |
75 | 75 | ||
76 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 76 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
77 | pmu_handle_rppg_init_msg, &success, &seq, ~0); | 77 | pmu_handle_rppg_init_msg, &success, &seq, ~0); |
78 | if (status) { | 78 | if (status) { |
79 | nvgpu_err(g, "Unable to submit parameter command %d", | 79 | nvgpu_err(g, "Unable to submit parameter command %d", |
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index f07a1ffd..6b98f884 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c | |||
@@ -96,7 +96,7 @@ u32 perf_pmu_vfe_load(struct gk20a *g) | |||
96 | handler.prpccall = &rpccall; | 96 | handler.prpccall = &rpccall; |
97 | handler.success = 0; | 97 | handler.success = 0; |
98 | 98 | ||
99 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 99 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
100 | PMU_COMMAND_QUEUE_LPQ, | 100 | PMU_COMMAND_QUEUE_LPQ, |
101 | perfrpc_pmucmdhandler, (void *)&handler, | 101 | perfrpc_pmucmdhandler, (void *)&handler, |
102 | &seqdesc, ~0); | 102 | &seqdesc, ~0); |
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index 771a8b8d..803b1bc0 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c | |||
@@ -109,7 +109,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g, | |||
109 | /* Setup the handler params to communicate back results.*/ | 109 | /* Setup the handler params to communicate back results.*/ |
110 | handlerparams.success = 0; | 110 | handlerparams.success = 0; |
111 | 111 | ||
112 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 112 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
113 | PMU_COMMAND_QUEUE_LPQ, | 113 | PMU_COMMAND_QUEUE_LPQ, |
114 | pmgr_pmucmdhandler, | 114 | pmgr_pmucmdhandler, |
115 | (void *)&handlerparams, | 115 | (void *)&handlerparams, |
@@ -392,7 +392,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking( | |||
392 | /* Setup the handler params to communicate back results.*/ | 392 | /* Setup the handler params to communicate back results.*/ |
393 | handlerparams.success = 0; | 393 | handlerparams.success = 0; |
394 | 394 | ||
395 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 395 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
396 | PMU_COMMAND_QUEUE_LPQ, | 396 | PMU_COMMAND_QUEUE_LPQ, |
397 | pmgr_pmucmdhandler, | 397 | pmgr_pmucmdhandler, |
398 | (void *)&handlerparams, | 398 | (void *)&handlerparams, |
@@ -436,7 +436,7 @@ static u32 pmgr_pmu_load_blocking(struct gk20a *g) | |||
436 | /* Setup the handler params to communicate back results.*/ | 436 | /* Setup the handler params to communicate back results.*/ |
437 | handlerparams.success = 0; | 437 | handlerparams.success = 0; |
438 | 438 | ||
439 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 439 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, |
440 | PMU_COMMAND_QUEUE_LPQ, | 440 | PMU_COMMAND_QUEUE_LPQ, |
441 | pmgr_pmucmdhandler, | 441 | pmgr_pmucmdhandler, |
442 | (void *)&handlerparams, | 442 | (void *)&handlerparams, |
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c index 918d4ad8..4609c95f 100644 --- a/drivers/gpu/nvgpu/therm/thrmpmu.c +++ b/drivers/gpu/nvgpu/therm/thrmpmu.c | |||
@@ -81,7 +81,7 @@ static u32 therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | |||
81 | u32 status; | 81 | u32 status; |
82 | struct therm_pmucmdhandler_params *handlerparams = NULL; | 82 | struct therm_pmucmdhandler_params *handlerparams = NULL; |
83 | 83 | ||
84 | status = gk20a_pmu_cmd_post(g, cmd, msg, payload, | 84 | status = nvgpu_pmu_cmd_post(g, cmd, msg, payload, |
85 | queue_id, | 85 | queue_id, |
86 | callback, | 86 | callback, |
87 | cb_param, | 87 | cb_param, |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index f9d421fc..8bc9671b 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c | |||
@@ -83,7 +83,7 @@ static u32 volt_pmu_rpc_execute(struct gk20a *g, | |||
83 | handler.prpc_call = prpc_call; | 83 | handler.prpc_call = prpc_call; |
84 | handler.success = 0; | 84 | handler.success = 0; |
85 | 85 | ||
86 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 86 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
87 | PMU_COMMAND_QUEUE_LPQ, | 87 | PMU_COMMAND_QUEUE_LPQ, |
88 | volt_rpc_pmucmdhandler, (void *)&handler, | 88 | volt_rpc_pmucmdhandler, (void *)&handler, |
89 | &seqdesc, ~0); | 89 | &seqdesc, ~0); |