diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-28 10:34:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-16 06:10:49 -0400 |
commit | e5000d299f84432f63b30c0bd43841046c704f04 (patch) | |
tree | acb11e42f0d38c4801692b15be04048038d88052 /drivers | |
parent | 0301cc01f6cbfb752290bc63a2ed4eb19129c7c1 (diff) |
gpu: nvgpu: implement new host semaphore methods for Volta
Semaphore methods currently being used in Volta are deprecated for future chips
And on Volta we support both old and new methods
So replace old methods by new methods on Volta itself so that new methods
get tested on silicon
Implement below HALs for Volta with new semaphore methods
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer
Also use new methods in these APIs
gv11b_fifo_add_syncpt_wait_cmd()
gv11b_fifo_add_syncpt_incr_cmd()
And change corresponding APIs to reflect correct size of command buffer
gv11b_fifo_get_syncpt_wait_cmd_size()
gv11b_fifo_get_syncpt_incr_cmd_size()
Jira NVGPUT-16
Change-Id: Ia3a37cd0560ddb54761dfea9bd28c4384cd8a11c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704518
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 114 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 6 |
5 files changed, 98 insertions, 40 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index c64a06ca..4a710689 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -597,9 +597,9 @@ static const struct gpu_ops gv100_ops = { | |||
597 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, | 597 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, |
598 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, | 598 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, |
599 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, | 599 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, |
600 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 600 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
601 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 601 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
602 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 602 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
603 | }, | 603 | }, |
604 | .gr_ctx = { | 604 | .gr_ctx = { |
605 | .get_netlist_name = gr_gv100_get_netlist_name, | 605 | .get_netlist_name = gr_gv100_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b374e517..9843c7de 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1659,6 +1659,55 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, | |||
1659 | nvgpu_log_info(g, "eng method buffers de-allocated"); | 1659 | nvgpu_log_info(g, "eng method buffers de-allocated"); |
1660 | } | 1660 | } |
1661 | 1661 | ||
1662 | u32 gv11b_fifo_get_sema_wait_cmd_size(void) | ||
1663 | { | ||
1664 | return 10; | ||
1665 | } | ||
1666 | |||
1667 | u32 gv11b_fifo_get_sema_incr_cmd_size(void) | ||
1668 | { | ||
1669 | return 12; | ||
1670 | } | ||
1671 | |||
1672 | void gv11b_fifo_add_sema_cmd(struct gk20a *g, | ||
1673 | struct nvgpu_semaphore *s, u64 sema_va, | ||
1674 | struct priv_cmd_entry *cmd, | ||
1675 | u32 off, bool acquire, bool wfi) | ||
1676 | { | ||
1677 | nvgpu_log_fn(g, " "); | ||
1678 | |||
1679 | /* sema_addr_lo */ | ||
1680 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); | ||
1681 | nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffff); | ||
1682 | |||
1683 | /* sema_addr_hi */ | ||
1684 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); | ||
1685 | nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32) & 0xff); | ||
1686 | |||
1687 | /* payload_lo */ | ||
1688 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); | ||
1689 | nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s)); | ||
1690 | |||
1691 | /* payload_hi : ignored */ | ||
1692 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); | ||
1693 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
1694 | |||
1695 | if (acquire) { | ||
1696 | /* sema_execute : acq_strict_geq | switch_en | 32bit */ | ||
1697 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); | ||
1698 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2 | (1 << 12)); | ||
1699 | } else { | ||
1700 | /* sema_execute : release | wfi | 32bit */ | ||
1701 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); | ||
1702 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
1703 | 0x1 | ((wfi ? 0x1 : 0x0) << 20)); | ||
1704 | |||
1705 | /* non_stall_int : payload is ignored */ | ||
1706 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008); | ||
1707 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
1708 | } | ||
1709 | } | ||
1710 | |||
1662 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 1711 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
1663 | static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) | 1712 | static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) |
1664 | { | 1713 | { |
@@ -1751,28 +1800,30 @@ void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, | |||
1751 | 1800 | ||
1752 | off = cmd->off + off; | 1801 | off = cmd->off + off; |
1753 | 1802 | ||
1754 | /* semaphore_a */ | 1803 | /* sema_addr_lo */ |
1755 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); | 1804 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); |
1756 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
1757 | (gpu_va >> 32) & 0xff); | ||
1758 | /* semaphore_b */ | ||
1759 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); | ||
1760 | /* offset */ | ||
1761 | nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); | 1805 | nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); |
1762 | 1806 | ||
1763 | /* semaphore_c */ | 1807 | /* sema_addr_hi */ |
1764 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); | 1808 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); |
1765 | /* payload */ | 1809 | nvgpu_mem_wr32(g, cmd->mem, off++, (gpu_va >> 32) & 0xff); |
1810 | |||
1811 | /* payload_lo */ | ||
1812 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); | ||
1766 | nvgpu_mem_wr32(g, cmd->mem, off++, thresh); | 1813 | nvgpu_mem_wr32(g, cmd->mem, off++, thresh); |
1767 | /* semaphore_d */ | 1814 | |
1768 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); | 1815 | /* payload_hi : ignored */ |
1769 | /* operation: acq_geq, switch_en */ | 1816 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); |
1770 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); | 1817 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); |
1818 | |||
1819 | /* sema_execute : acq_strict_geq | switch_en | 32bit */ | ||
1820 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); | ||
1821 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2 | (1 << 12)); | ||
1771 | } | 1822 | } |
1772 | 1823 | ||
1773 | u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) | 1824 | u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) |
1774 | { | 1825 | { |
1775 | return 8; | 1826 | return 10; |
1776 | } | 1827 | } |
1777 | 1828 | ||
1778 | u32 gv11b_fifo_get_syncpt_incr_per_release(void) | 1829 | u32 gv11b_fifo_get_syncpt_incr_per_release(void) |
@@ -1788,30 +1839,31 @@ void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, | |||
1788 | 1839 | ||
1789 | nvgpu_log_fn(g, " "); | 1840 | nvgpu_log_fn(g, " "); |
1790 | 1841 | ||
1791 | /* semaphore_a */ | 1842 | /* sema_addr_lo */ |
1792 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); | 1843 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); |
1793 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
1794 | (gpu_va >> 32) & 0xff); | ||
1795 | /* semaphore_b */ | ||
1796 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); | ||
1797 | /* offset */ | ||
1798 | nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); | 1844 | nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); |
1799 | 1845 | ||
1800 | /* semaphore_c */ | 1846 | /* sema_addr_hi */ |
1801 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); | 1847 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); |
1802 | /* payload */ | 1848 | nvgpu_mem_wr32(g, cmd->mem, off++, (gpu_va >> 32) & 0xff); |
1803 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); | 1849 | |
1804 | /* semaphore_d */ | 1850 | /* payload_lo */ |
1805 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); | 1851 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); |
1852 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
1853 | |||
1854 | /* payload_hi : ignored */ | ||
1855 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); | ||
1856 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
1806 | 1857 | ||
1807 | /* operation: 4 byte payload, release, wfi */ | 1858 | /* sema_execute : release | wfi | 32bit */ |
1859 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); | ||
1808 | nvgpu_mem_wr32(g, cmd->mem, off++, | 1860 | nvgpu_mem_wr32(g, cmd->mem, off++, |
1809 | (0x1 << 24) | 0x2 | ((wfi_cmd ? 0x0 : 0x1) << 20)); | 1861 | 0x1 | ((wfi_cmd ? 0x1 : 0x0) << 20)); |
1810 | } | 1862 | } |
1811 | 1863 | ||
1812 | u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) | 1864 | u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) |
1813 | { | 1865 | { |
1814 | return 8; | 1866 | return 10; |
1815 | } | 1867 | } |
1816 | #endif /* CONFIG_TEGRA_GK20A_NVHOST */ | 1868 | #endif /* CONFIG_TEGRA_GK20A_NVHOST */ |
1817 | 1869 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 9157c300..3f58f927 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -106,6 +106,12 @@ void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, | |||
106 | struct nvgpu_mem *syncpt_buf); | 106 | struct nvgpu_mem *syncpt_buf); |
107 | int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, | 107 | int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, |
108 | u64 *base_gpuva, u32 *sync_size); | 108 | u64 *base_gpuva, u32 *sync_size); |
109 | u32 gv11b_fifo_get_sema_wait_cmd_size(void); | ||
110 | u32 gv11b_fifo_get_sema_incr_cmd_size(void); | ||
111 | void gv11b_fifo_add_sema_cmd(struct gk20a *g, | ||
112 | struct nvgpu_semaphore *s, u64 sema_va, | ||
113 | struct priv_cmd_entry *cmd, | ||
114 | u32 off, bool acquire, bool wfi); | ||
109 | void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, | 115 | void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, |
110 | struct priv_cmd_entry *cmd, u32 off, | 116 | struct priv_cmd_entry *cmd, u32 off, |
111 | u32 id, u32 thresh, u64 gpu_va_base); | 117 | u32 id, u32 thresh, u64 gpu_va_base); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7bfcc1dd..290a9452 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -566,9 +566,9 @@ static const struct gpu_ops gv11b_ops = { | |||
566 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, | 566 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, |
567 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, | 567 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, |
568 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, | 568 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, |
569 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 569 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
570 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 570 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
571 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 571 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
572 | }, | 572 | }, |
573 | .gr_ctx = { | 573 | .gr_ctx = { |
574 | .get_netlist_name = gr_gv11b_get_netlist_name, | 574 | .get_netlist_name = gr_gv11b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 7bc053e8..9fe76573 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -425,9 +425,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
425 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, | 425 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, |
426 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, | 426 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, |
427 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, | 427 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, |
428 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 428 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
429 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 429 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
430 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 430 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
431 | }, | 431 | }, |
432 | .gr_ctx = { | 432 | .gr_ctx = { |
433 | .get_netlist_name = gr_gv11b_get_netlist_name, | 433 | .get_netlist_name = gr_gv11b_get_netlist_name, |