gpu: nvgpu: Fix priv ring error detection

Use hardware headers instead of hardcoded register numbers in priv
ring. This required updating the priv ring headers to add all the
registers and fields needed.

Incidentally this also gets rid of a lot of GPC priv ring registers
as they're not used in our code.

Also delete duplicate prints for the same information. We were
dumping GPC error also in gk20a_pbus_isr(), and we dumped master
information twice.

Dump status of each GPC separately instead of supporting only GPC0.

Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295481
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>

12 files changed, 403 insertions, 220 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index 420b65f1..a44df1e8 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -23,6 +23,7 @@
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
 
 void gk20a_enable_priv_ring(struct gk20a *g)
 {
@@ -71,6 +72,8 @@ void gk20a_priv_ring_isr(struct gk20a *g)
         u32 status0, status1;
         u32 cmd;
         s32 retry = 100;
+        u32 gpc;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
         struct gk20a_platform *platform = dev_get_drvdata(g->dev);
 
         if (platform->is_fmodel)
@@ -82,20 +85,28 @@ void gk20a_priv_ring_isr(struct gk20a *g)
         gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x,"
                 "status1: 0x%08x", status0, status1);
 
-        if (status0 & (0x1 | 0x2 | 0x4)) {
+        if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 ||
+            pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0 ||
+            pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
                 gk20a_reset_priv_ring(g);
         }
 
-        if (status0 & 0x100) {
+        if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
                 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
-                        gk20a_readl(g, 0x122120), gk20a_readl(g, 0x122124), gk20a_readl(g, 0x122128),
-                        gk20a_readl(g, 0x12212c));
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
+                        gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
         }
 
-        if (status1 & 0x1) {
-                gk20a_dbg(gpu_dbg_intr, "GPC write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
-                        gk20a_readl(g, 0x128120), gk20a_readl(g, 0x128124), gk20a_readl(g, 0x128128),
-                        gk20a_readl(g, 0x12812c));
+        for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
+                if (status1 & BIT(gpc)) {
+                        gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),
+                                gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride));
+                }
         }
 
         cmd = gk20a_readl(g, pri_ringmaster_command_r());
@@ -112,10 +123,4 @@ void gk20a_priv_ring_isr(struct gk20a *g)
         if (retry <= 0)
                 gk20a_warn(dev_from_gk20a(g),
                         "priv ringmaster cmd ack too many retries");
-
-        status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
-        status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
-
-        gk20a_dbg_info("ringmaster intr status0: 0x%08x,"
-                " status1: 0x%08x", status0, status1);
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
index d4007613..10e3174d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void)
 {
         return 0x00120058;
 }
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
 static inline u32 pri_ringmaster_intr_status1_r(void)
 {
         return 0x0012005c;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
index e8aad933..7a48efd8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
@@ -1,7 +1,5 @@
 /*
- * drivers/video/tegra/host/gk20a/hw_pri_ringstation_gpc_gk20a.h
- *
- * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,213 +12,62 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
  *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
  */
-
- /*
-  * Function naming determines intended use:
-  *
-  *     <x>_r(void) : Returns the offset for register <x>.
-  *
-  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
-  *
-  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
-  *
-  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
-  *         and masked to place it at field <y> of register <x>.  This value
-  *         can be |'d with others to produce a full register value for
-  *         register <x>.
-  *
-  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
-  *         value can be ~'d and then &'d to clear the value of field <y> for
-  *         register <x>.
-  *
-  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
-  *         to place it at field <y> of register <x>.  This value can be |'d
-  *         with others to produce a full register value for <x>.
-  *
-  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
-  *         <x> value 'r' after being shifted to place its LSB at bit 0.
-  *         This value is suitable for direct comparison with other unshifted
-  *         values appropriate for use in field <y> of register <x>.
-  *
-  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
-  *         field <y> of register <x>.  This value is suitable for direct
-  *         comparison with unshifted values appropriate for use in field <y>
-  *         of register <x>.
-  */
-
-#ifndef __hw_pri_ringstation_gpc_gk20a_h__
-#define __hw_pri_ringstation_gpc_gk20a_h__
-/*This file is autogenerated.  Do not edit. */
+#ifndef _hw_pri_ringstation_gpc_gk20a_h_
+#define _hw_pri_ringstation_gpc_gk20a_h_
 
 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {
-        return 0x00128300+((i)*4);
-}
-static inline u32 pri_ringstation_gpc_master_config__size_1_v(void)
-{
-        return 64;
-}
-static inline u32 pri_ringstation_gpc_master_config_timeout_s(void)
-{
-        return 18;
-}
-static inline u32 pri_ringstation_gpc_master_config_timeout_f(u32 v)
-{
-        return (v & 0x3ffff) << 0;
-}
-static inline u32 pri_ringstation_gpc_master_config_timeout_m(void)
-{
-        return 0x3ffff << 0;
-}
-static inline u32 pri_ringstation_gpc_master_config_timeout_v(u32 r)
-{
-        return (r >> 0) & 0x3ffff;
-}
-static inline u32 pri_ringstation_gpc_master_config_timeout_i_v(void)
-{
-        return 0x00000064;
-}
-static inline u32 pri_ringstation_gpc_master_config_timeout_i_f(void)
-{
-        return 0x64;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_s(void)
-{
-        return 1;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_f(u32 v)
-{
-        return (v & 0x1) << 30;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_m(void)
-{
-        return 0x1 << 30;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_v(u32 r)
-{
-        return (r >> 30) & 0x1;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_error_v(void)
-{
-        return 0x00000000;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_error_f(void)
-{
-        return 0x0;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_soldier_on_v(void)
-{
-        return 0x00000001;
-}
-static inline u32 pri_ringstation_gpc_master_config_fs_action_soldier_on_f(void)
-{
-        return 0x40000000;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_s(void)
-{
-        return 1;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_f(u32 v)
-{
-        return (v & 0x1) << 31;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_m(void)
-{
-        return 0x1 << 31;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_v(u32 r)
-{
-        return (r >> 31) & 0x1;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_error_v(void)
-{
-        return 0x00000000;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_error_f(void)
-{
-        return 0x0;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_soldier_on_v(void)
-{
-        return 0x00000001;
-}
-static inline u32 pri_ringstation_gpc_master_config_reset_action_soldier_on_f(void)
-{
-        return 0x80000000;
-}
-static inline u32 pri_ringstation_gpc_master_config_setup_clocks_s(void)
-{
-        return 3;
-}
-static inline u32 pri_ringstation_gpc_master_config_setup_clocks_f(u32 v)
-{
-        return (v & 0x7) << 20;
-}
-static inline u32 pri_ringstation_gpc_master_config_setup_clocks_m(void)
-{
-        return 0x7 << 20;
-}
-static inline u32 pri_ringstation_gpc_master_config_setup_clocks_v(u32 r)
-{
-        return (r >> 20) & 0x7;
-}
-static inline u32 pri_ringstation_gpc_master_config_setup_clocks_i_v(void)
-{
-        return 0x00000000;
-}
-static inline u32 pri_ringstation_gpc_master_config_setup_clocks_i_f(void)
-{
-        return 0x0;
-}
-static inline u32 pri_ringstation_gpc_master_config_wait_clocks_s(void)
-{
-        return 3;
-}
-static inline u32 pri_ringstation_gpc_master_config_wait_clocks_f(u32 v)
-{
-        return (v & 0x7) << 24;
-}
-static inline u32 pri_ringstation_gpc_master_config_wait_clocks_m(void)
-{
-        return 0x7 << 24;
+        return 0x00128300 + i*4;
 }
-static inline u32 pri_ringstation_gpc_master_config_wait_clocks_v(u32 r)
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
 {
-        return (r >> 24) & 0x7;
+        return 0x00128120;
 }
-static inline u32 pri_ringstation_gpc_master_config_wait_clocks_i_v(void)
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
 {
-        return 0x00000000;
+        return 0x00128124;
 }
-static inline u32 pri_ringstation_gpc_master_config_wait_clocks_i_f(void)
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
 {
-        return 0x0;
+        return 0x00128128;
 }
-static inline u32 pri_ringstation_gpc_master_config_hold_clocks_s(void)
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
 {
-        return 3;
+        return 0x0012812c;
 }
-static inline u32 pri_ringstation_gpc_master_config_hold_clocks_f(u32 v)
-{
-        return (v & 0x7) << 27;
-}
-static inline u32 pri_ringstation_gpc_master_config_hold_clocks_m(void)
-{
-        return 0x7 << 27;
-}
-static inline u32 pri_ringstation_gpc_master_config_hold_clocks_v(u32 r)
-{
-        return (r >> 27) & 0x7;
-}
-static inline u32 pri_ringstation_gpc_master_config_hold_clocks_i_v(void)
-{
-        return 0x00000000;
-}
-static inline u32 pri_ringstation_gpc_master_config_hold_clocks_i_f(void)
-{
-        return 0x0;
-}
-
-#endif /* __hw_pri_ringstation_gpc_gk20a_h__ */
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
index c281dd54..5ef300e7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
 {
         return 0x1;
 }
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212c;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
index 930592db..9c0f781f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void)
 {
         return 0x00120058;
 }
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
 static inline u32 pri_ringmaster_intr_status1_r(void)
 {
         return 0x0012005c;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
new file mode 100644
index 00000000..d9da79bd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gm20b_h_
+#define _hw_pri_ringstation_gpc_gm20b_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300 + i*4;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812c;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
index 7170a287..66b32604 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
 {
         return 0x1;
 }
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212c;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
new file mode 100644
index 00000000..ec2f8af6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gp106_h_
+#define _hw_pri_ringstation_gpc_gp106_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300 + i*4;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812c;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
index a22d6a05..565ea8e9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
 {
         return 0x1;
 }
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212c;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
index 7a458858..6528a1c3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void)
 {
         return 0x00120058;
 }
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
 static inline u32 pri_ringmaster_intr_status1_r(void)
 {
         return 0x0012005c;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
new file mode 100644
index 00000000..5194ad83
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gp10b_h_
+#define _hw_pri_ringstation_gpc_gp10b_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300 + i*4;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812c;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
index eb711452..7e1d5be7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
 {
         return 0x1;
 }
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212c;
+}
 #endif