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authorSeema Khowala <seemaj@nvidia.com>2017-03-28 17:36:02 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-08 14:35:48 -0400
commitd9ee7aff0455ad79caf395cedd53c3e092d2538c (patch)
treea111c77e352d9726f142dbd005e091f88ee5914c /drivers
parent2f6d321390a98ace1e52f21c6a399e06b3fe71e7 (diff)
gpu: nvgpu: gv11b: fifo recovery for nonreplay fault
Host will no longer receive replayable or non-replayable fault requests. MMU will handle both types of fault reporting. This means that Host will no longer automatically disable scheduling or preempt a PBDMA when an engine page faults. After fault happens, engine will stall on its own fault and will not context switch until the fault is serviced JIRA GPUT19X-7 Change-Id: I8039e6f50d87f43e101d1372faa5ca6fb739036e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493417 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fb_gv11b.c23
1 files changed, 18 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index 6d1fbca9..f9532d66 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -966,6 +966,9 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
966static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, 966static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
967 struct mmu_fault_info *mmfault) 967 struct mmu_fault_info *mmfault)
968{ 968{
969 unsigned int id_type;
970 u32 act_eng_bitmask = 0;
971
969 if (!mmfault->valid) 972 if (!mmfault->valid)
970 return; 973 return;
971 974
@@ -977,13 +980,23 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
977 * instance block, the fault cannot be isolated to a 980 * instance block, the fault cannot be isolated to a
978 * single context so we need to reset the entire runlist 981 * single context so we need to reset the entire runlist
979 */ 982 */
980 nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST"); 983 id_type = ID_TYPE_UNKNOWN;
984 nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST BLOCK MMU FAULT");
985
986 } else if (mmfault->refch) {
987 if (gk20a_is_channel_marked_as_tsg(mmfault->refch))
988 id_type = ID_TYPE_TSG;
989 else
990 id_type = ID_TYPE_CHANNEL;
991 } else {
992 id_type = ID_TYPE_UNKNOWN;
981 } 993 }
982 994
983 if (mmfault->refch) { 995 if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID)
984 gk20a_channel_put(mmfault->refch); 996 act_eng_bitmask = BIT(mmfault->faulted_engine);
985 mmfault->refch = NULL; 997
986 } 998 g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, mmfault->chid,
999 id_type, RC_TYPE_MMU_FAULT, mmfault);
987} 1000}
988 1001
989static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, 1002static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g,