diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-22 16:43:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 15:04:43 -0400 |
commit | d8c0144f8b45ef8a94fc696efaa0c782c4c787af (patch) | |
tree | 07c7463570e0451731dcd29091e1a254b96cd409 /drivers | |
parent | 0852c9f1aba1654e380ccdd13cd0540fbb5a8ab0 (diff) |
gpu: nvgpu: add clear_sm_hww gr ops
Required for multiple SM support and t19x SM
register address changes
JIRA GPUT19X-75
Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 |
5 files changed, 21 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 483cdd6e..95b93496 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -300,6 +300,8 @@ struct gpu_ops { | |||
300 | u32 global_esr_mask, bool check_errors); | 300 | u32 global_esr_mask, bool check_errors); |
301 | int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc, | 301 | int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc, |
302 | u32 sm, u32 global_esr_mask, bool check_errors); | 302 | u32 sm, u32 global_esr_mask, bool check_errors); |
303 | void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
304 | u32 global_esr); | ||
303 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, | 305 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, |
304 | u32 *esr_sm_sel); | 306 | u32 *esr_sm_sel); |
305 | int (*handle_sm_exception)(struct gk20a *g, | 307 | int (*handle_sm_exception)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d2c77c93..4bedcc9a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5501,21 +5501,6 @@ bool gk20a_gr_sm_debugger_attached(struct gk20a *g) | |||
5501 | return false; | 5501 | return false; |
5502 | } | 5502 | } |
5503 | 5503 | ||
5504 | void gk20a_gr_clear_sm_hww(struct gk20a *g, | ||
5505 | u32 gpc, u32 tpc, u32 global_esr) | ||
5506 | { | ||
5507 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
5508 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
5509 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
5510 | |||
5511 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | ||
5512 | global_esr); | ||
5513 | |||
5514 | /* clear the warp hww */ | ||
5515 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, | ||
5516 | gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f()); | ||
5517 | } | ||
5518 | |||
5519 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 5504 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
5520 | bool *post_event, struct channel_gk20a *fault_ch, | 5505 | bool *post_event, struct channel_gk20a *fault_ch, |
5521 | u32 *hww_global_esr) | 5506 | u32 *hww_global_esr) |
@@ -5678,7 +5663,8 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
5678 | /* clear the hwws, also causes tpc and gpc | 5663 | /* clear the hwws, also causes tpc and gpc |
5679 | * exceptions to be cleared | 5664 | * exceptions to be cleared |
5680 | */ | 5665 | */ |
5681 | gk20a_gr_clear_sm_hww(g, gpc, tpc, *hww_global_esr); | 5666 | g->ops.gr.clear_sm_hww(g, |
5667 | gpc, tpc, sm, *hww_global_esr); | ||
5682 | 5668 | ||
5683 | } | 5669 | } |
5684 | 5670 | ||
@@ -8439,7 +8425,8 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g) | |||
8439 | /* clearing hwws, also causes tpc and gpc | 8425 | /* clearing hwws, also causes tpc and gpc |
8440 | * exceptions to be cleared | 8426 | * exceptions to be cleared |
8441 | */ | 8427 | */ |
8442 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr); | 8428 | g->ops.gr.clear_sm_hww(g, |
8429 | gpc, tpc, sm, global_esr); | ||
8443 | } | 8430 | } |
8444 | } | 8431 | } |
8445 | } | 8432 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 77db5cf6..436377bd 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -539,8 +539,6 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config); | |||
539 | 539 | ||
540 | /* sm */ | 540 | /* sm */ |
541 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); | 541 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); |
542 | void gk20a_gr_clear_sm_hww(struct gk20a *g, | ||
543 | u32 gpc, u32 tpc, u32 global_esr); | ||
544 | u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); | 542 | u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); |
545 | 543 | ||
546 | #define gr_gk20a_elpg_protected_call(g, func) \ | 544 | #define gr_gk20a_elpg_protected_call(g, func) \ |
@@ -683,8 +681,6 @@ int gk20a_gr_lock_down_sm(struct gk20a *g, | |||
683 | bool check_errors); | 681 | bool check_errors); |
684 | int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 682 | int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
685 | u32 global_esr_mask, bool check_errors); | 683 | u32 global_esr_mask, bool check_errors); |
686 | void gk20a_gr_clear_sm_hww(struct gk20a *g, | ||
687 | u32 gpc, u32 tpc, u32 global_esr); | ||
688 | int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, | 684 | int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, |
689 | u32 *mailbox_ret, u32 opc_success, | 685 | u32 *mailbox_ret, u32 opc_success, |
690 | u32 mailbox_ok, u32 opc_fail, | 686 | u32 mailbox_ok, u32 opc_fail, |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 333f0340..90046232 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1530,6 +1530,18 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, | |||
1530 | priv_addr_table, priv_addr_table_index); | 1530 | priv_addr_table, priv_addr_table_index); |
1531 | } | 1531 | } |
1532 | 1532 | ||
1533 | static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
1534 | u32 global_esr) | ||
1535 | { | ||
1536 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | ||
1537 | |||
1538 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | ||
1539 | global_esr); | ||
1540 | |||
1541 | /* clear the warp hww */ | ||
1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); | ||
1543 | } | ||
1544 | |||
1533 | void gm20b_init_gr(struct gpu_ops *gops) | 1545 | void gm20b_init_gr(struct gpu_ops *gops) |
1534 | { | 1546 | { |
1535 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1547 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
@@ -1640,4 +1652,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1640 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; | 1652 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; |
1641 | gops->gr.lock_down_sm = gk20a_gr_lock_down_sm; | 1653 | gops->gr.lock_down_sm = gk20a_gr_lock_down_sm; |
1642 | gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down; | 1654 | gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down; |
1655 | gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww; | ||
1643 | } | 1656 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 27d609d1..4ff306e0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1835,7 +1835,8 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1835 | /* reset the HWW errors after locking down */ | 1835 | /* reset the HWW errors after locking down */ |
1836 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, | 1836 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, |
1837 | gpc, tpc, sm); | 1837 | gpc, tpc, sm); |
1838 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1838 | g->ops.gr.clear_sm_hww(g, |
1839 | gpc, tpc, sm, global_esr_copy); | ||
1839 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1840 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1840 | "CILP: HWWs cleared for gpc %d tpc %d\n", | 1841 | "CILP: HWWs cleared for gpc %d tpc %d\n", |
1841 | gpc, tpc); | 1842 | gpc, tpc); |