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authorKonsta Holtta <kholtta@nvidia.com>2016-06-17 08:45:31 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:18 -0500
commitd6730d5214a941451a298a22a037e5bcc4fb9ea4 (patch)
treefa6041955814129c110318a0fe74c01f6beeca10 /drivers
parent81756640cb2c7cadb1b30c0233088268bd57ee6c (diff)
gpu: nvgpu: gp10x: add support for vidmem in page tables
Modify page table updates to take an aperture flag (up until gk20a_locked_gmmu_map()), don't hard-assume sysmem and propagate it to hardware. Jira DNVGPU-76 Change-Id: I797fdaaf5f42a84fa0446577359147fb6908a720 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169295 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h8
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c48
2 files changed, 35 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
index 86870aea..d231ee44 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
@@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void)
242{ 242{
243 return 0; 243 return 0;
244} 244}
245static inline u32 gmmu_new_pte_address_vid_f(u32 v)
246{
247 return (v & 0xffffff) << 8;
248}
249static inline u32 gmmu_new_pte_address_vid_w(void)
250{
251 return 0;
252}
245static inline u32 gmmu_new_pte_vol_w(void) 253static inline u32 gmmu_new_pte_vol_w(void)
246{ 254{
247 return 0; 255 return 0;
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index a183154e..7778883e 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -170,7 +170,8 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
170 u64 *iova, 170 u64 *iova,
171 u32 kind_v, u64 *ctag, 171 u32 kind_v, u64 *ctag,
172 bool cacheable, bool unmapped_pte, 172 bool cacheable, bool unmapped_pte,
173 int rw_flag, bool sparse, bool priv) 173 int rw_flag, bool sparse, bool priv,
174 enum gk20a_aperture aperture)
174{ 175{
175 struct gk20a *g = gk20a_from_vm(vm); 176 struct gk20a *g = gk20a_from_vm(vm);
176 u64 pte_addr = 0; 177 u64 pte_addr = 0;
@@ -184,9 +185,9 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
184 pte_addr = entry_addr(g, pte) >> gmmu_new_pde_address_shift_v(); 185 pte_addr = entry_addr(g, pte) >> gmmu_new_pde_address_shift_v();
185 pde_addr = entry_addr(g, parent); 186 pde_addr = entry_addr(g, parent);
186 187
187 pde_v[0] |= g->mm.vidmem_is_vidmem ? 188 pde_v[0] |= gk20a_aperture_mask(g, &pte->mem,
188 gmmu_new_pde_aperture_sys_mem_ncoh_f() : 189 gmmu_new_pde_aperture_sys_mem_ncoh_f(),
189 gmmu_new_pde_aperture_video_memory_f(); 190 gmmu_new_pde_aperture_video_memory_f());
190 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); 191 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
191 pde_v[0] |= gmmu_new_pde_vol_true_f(); 192 pde_v[0] |= gmmu_new_pde_vol_true_f();
192 pde_v[1] |= pte_addr >> 24; 193 pde_v[1] |= pte_addr >> 24;
@@ -214,7 +215,8 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
214 u64 *iova, 215 u64 *iova,
215 u32 kind_v, u64 *ctag, 216 u32 kind_v, u64 *ctag,
216 bool cacheable, bool unmapped_pte, 217 bool cacheable, bool unmapped_pte,
217 int rw_flag, bool sparse, bool priv) 218 int rw_flag, bool sparse, bool priv,
219 enum gk20a_aperture aperture)
218{ 220{
219 struct gk20a *g = gk20a_from_vm(vm); 221 struct gk20a *g = gk20a_from_vm(vm);
220 bool small_valid, big_valid; 222 bool small_valid, big_valid;
@@ -239,9 +241,9 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
239 241
240 if (small_valid) { 242 if (small_valid) {
241 pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); 243 pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small);
242 pde_v[2] |= g->mm.vidmem_is_vidmem ? 244 pde_v[2] |= gk20a_aperture_mask(g, &pte->mem,
243 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() : 245 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(),
244 gmmu_new_dual_pde_aperture_small_video_memory_f(); 246 gmmu_new_dual_pde_aperture_small_video_memory_f());
245 pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); 247 pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f();
246 pde_v[3] |= pte_addr_small >> 24; 248 pde_v[3] |= pte_addr_small >> 24;
247 } 249 }
@@ -249,9 +251,9 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
249 if (big_valid) { 251 if (big_valid) {
250 pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); 252 pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big);
251 pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); 253 pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f();
252 pde_v[0] |= g->mm.vidmem_is_vidmem ? 254 pde_v[0] |= gk20a_aperture_mask(g, &pte->mem,
253 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() : 255 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(),
254 gmmu_new_dual_pde_aperture_big_video_memory_f(); 256 gmmu_new_dual_pde_aperture_big_video_memory_f());
255 pde_v[1] |= pte_addr_big >> 28; 257 pde_v[1] |= pte_addr_big >> 28;
256 } 258 }
257 259
@@ -276,7 +278,8 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
276 u64 *iova, 278 u64 *iova,
277 u32 kind_v, u64 *ctag, 279 u32 kind_v, u64 *ctag,
278 bool cacheable, bool unmapped_pte, 280 bool cacheable, bool unmapped_pte,
279 int rw_flag, bool sparse, bool priv) 281 int rw_flag, bool sparse, bool priv,
282 enum gk20a_aperture aperture)
280{ 283{
281 struct gk20a *g = vm->mm->g; 284 struct gk20a *g = vm->mm->g;
282 u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; 285 u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx];
@@ -284,15 +287,18 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
284 u32 pte_w[2] = {0, 0}; /* invalid pte */ 287 u32 pte_w[2] = {0, 0}; /* invalid pte */
285 288
286 if (*iova) { 289 if (*iova) {
287 if (unmapped_pte) 290 u32 pte_valid = unmapped_pte ?
288 pte_w[0] = gmmu_new_pte_valid_false_f(); 291 gmmu_new_pte_valid_false_f() :
289 else 292 gmmu_new_pte_valid_true_f();
290 pte_w[0] = gmmu_new_pte_valid_true_f(); 293 u32 iova_v = *iova >> gmmu_new_pte_address_shift_v();
291 pte_w[0] |= g->mm.vidmem_is_vidmem ? 294 u32 pte_addr = aperture == APERTURE_SYSMEM ?
292 gmmu_new_pte_aperture_sys_mem_ncoh_f() : 295 gmmu_new_pte_address_sys_f(iova_v) :
293 gmmu_new_pte_aperture_video_memory_f(); 296 gmmu_new_pte_address_vid_f(iova_v);
294 pte_w[0] |= gmmu_new_pte_address_sys_f(*iova 297 u32 pte_tgt = __gk20a_aperture_mask(g, aperture,
295 >> gmmu_new_pte_address_shift_v()); 298 gmmu_new_pte_aperture_sys_mem_ncoh_f(),
299 gmmu_new_pte_aperture_video_memory_f());
300
301 pte_w[0] = pte_valid | pte_addr | pte_tgt;
296 302
297 if (priv) 303 if (priv)
298 pte_w[0] |= gmmu_new_pte_privilege_true_f(); 304 pte_w[0] |= gmmu_new_pte_privilege_true_f();