drivers: gk20a: Add gr.ops NULL-ptr check

This fix add NULL-ptr checks for some of the user-accessible
ioctl.

Bug 3240771
Bug 200696704

Change-Id: Ibe7f75b31b2521a530883253a93ba832f010dc80
Signed-off-by: Thomas Steinle <tsteinle@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483635
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

2 files changed, 40 insertions, 15 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 7bcf5281..abb53e66 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics
  *
- * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -8851,6 +8851,10 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
         u32 gpc, tpc, sm, sm_id;
         u32 global_mask;
 
+        if (!g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask ||
+            !g->ops.gr.lock_down_sm || !g->ops.gr.bpt_reg_info)
+                return -EINVAL;
+
         /* Wait for the SMs to reach full stop. This condition is:
          * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE)
          * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp
@@ -8908,6 +8912,9 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
         u32 global_esr;
         u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
 
+        if (!g->ops.gr.get_sm_hww_global_esr || !g->ops.gr.clear_sm_hww)
+                return -EINVAL;
+
         for (gpc = 0; gpc < gr->gpc_count; gpc++) {
 
                 /* check if any tpc has an exception */
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index ee141ff8..94162b4f 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2020, NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2011-2021, NVIDIA Corporation.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -692,12 +692,15 @@ static int nvgpu_gpu_ioctl_trigger_suspend(struct gk20a *g)
 
         err = gk20a_busy(g);
         if (err)
-            return err;
+                return err;
 
-        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
-        err = gr_gk20a_elpg_protected_call(g,
+        if (g->ops.gr.trigger_suspend) {
+                nvgpu_mutex_acquire(&g->dbg_sessions_lock);
+                err = gr_gk20a_elpg_protected_call(g,
                         g->ops.gr.trigger_suspend(g));
-        nvgpu_mutex_release(&g->dbg_sessions_lock);
+                nvgpu_mutex_release(&g->dbg_sessions_lock);
+        } else
+                err = -EINVAL;
 
         gk20a_idle(g);
 
@@ -731,8 +734,13 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
                 goto out_free;
 
         nvgpu_mutex_acquire(&g->dbg_sessions_lock);
-        (void)gr_gk20a_elpg_protected_call(g,
+        if (g->ops.gr.wait_for_pause) {
+                (void)gr_gk20a_elpg_protected_call(g,
                         g->ops.gr.wait_for_pause(g, w_state));
+        } else {
+                err = -EINVAL;
+                goto out_idle;
+        }
 
         for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) {
                 ioctl_w_state[sm_id].valid_warps[0] =
@@ -755,6 +763,7 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
                 err = -EFAULT;
         }
 
+out_idle:
         nvgpu_mutex_release(&g->dbg_sessions_lock);
 
         gk20a_idle(g);
@@ -772,12 +781,15 @@ static int nvgpu_gpu_ioctl_resume_from_pause(struct gk20a *g)
 
         err = gk20a_busy(g);
         if (err)
-            return err;
+                return err;
 
-        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
-        err = gr_gk20a_elpg_protected_call(g,
+        if (g->ops.gr.resume_from_pause) {
+                nvgpu_mutex_acquire(&g->dbg_sessions_lock);
+                err = gr_gk20a_elpg_protected_call(g,
                         g->ops.gr.resume_from_pause(g));
-        nvgpu_mutex_release(&g->dbg_sessions_lock);
+                nvgpu_mutex_release(&g->dbg_sessions_lock);
+        } else
+                err = -EINVAL;
 
         gk20a_idle(g);
 
@@ -792,8 +804,11 @@ static int nvgpu_gpu_ioctl_clear_sm_errors(struct gk20a *g)
         if (err)
                 return err;
 
-        err = gr_gk20a_elpg_protected_call(g,
+        if (g->ops.gr.clear_sm_errors) {
+                err = gr_gk20a_elpg_protected_call(g,
                         g->ops.gr.clear_sm_errors(g));
+        } else
+                err = -EINVAL;
 
         gk20a_idle(g);
 
@@ -806,9 +821,12 @@ static int nvgpu_gpu_ioctl_has_any_exception(
 {
         u32 tpc_exception_en;
 
-        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
-        tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g);
-        nvgpu_mutex_release(&g->dbg_sessions_lock);
+        if (g->ops.gr.tpc_enabled_exceptions) {
+                nvgpu_mutex_acquire(&g->dbg_sessions_lock);
+                tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g);
+                nvgpu_mutex_release(&g->dbg_sessions_lock);
+        } else
+                return -EINVAL;
 
         args->tpc_exception_en_sm_mask = tpc_exception_en;