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authorDeepak Nibade <dnibade@nvidia.com>2016-04-27 08:55:57 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-09 16:18:13 -0400
commitc8b6a331d1e30595c5798fc3121575c1ab21e2ae (patch)
tree40a298307254459e83b88d5b0b1645db8a61bd5a /drivers
parente19ee13cc77c4770fabc6917b421f24cdaefec8c (diff)
gpu: nvgpu: use preemption modes defined in nvgpu-t18x.h
Below definitions of preemption modes are deleted: NVGPU_GR_PREEMPTION_MODE_GFXP NVGPU_GR_PREEMPTION_MODE_CILP Use new definitions defined in nvgpu-t18x.h NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP NVGPU_COMPUTE_PREEMPTION_MODE_CILP Bug 1646259 Change-Id: Ieff51e41ef34eb61357f95778c400c8a3fa330c8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1133597 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index f0736e19..5dee0921 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -320,7 +320,7 @@ static int gr_gv11b_commit_global_cb_manager(struct gk20a *g,
320 320
321 gk20a_dbg_fn(""); 321 gk20a_dbg_fn("");
322 322
323 if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { 323 if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) {
324 attrib_size_in_chunk = gr->attrib_cb_default_size + 324 attrib_size_in_chunk = gr->attrib_cb_default_size +
325 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - 325 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
326 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); 326 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
@@ -869,14 +869,14 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g,
869 goto fail_free_betacb; 869 goto fail_free_betacb;
870 } 870 }
871 871
872 (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; 872 (*gr_ctx)->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
873 } 873 }
874 874
875 if (class == PASCAL_COMPUTE_A) { 875 if (class == PASCAL_COMPUTE_A) {
876 if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) 876 if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP)
877 (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; 877 (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
878 else 878 else
879 (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; 879 (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CTA;
880 } 880 }
881 881
882 gk20a_dbg_fn("done"); 882 gk20a_dbg_fn("done");
@@ -978,13 +978,13 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
978 978
979 gk20a_dbg_fn(""); 979 gk20a_dbg_fn("");
980 980
981 if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { 981 if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) {
982 gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); 982 gk20a_dbg_info("GfxP: %x", gfxp_preempt_option);
983 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, 983 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0,
984 gfxp_preempt_option); 984 gfxp_preempt_option);
985 } 985 }
986 986
987 if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) { 987 if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) {
988 gk20a_dbg_info("CILP: %x", cilp_preempt_option); 988 gk20a_dbg_info("CILP: %x", cilp_preempt_option);
989 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0, 989 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0,
990 cilp_preempt_option); 990 cilp_preempt_option);
@@ -1542,8 +1542,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
1542 bool *early_exit, bool *ignore_debugger) 1542 bool *early_exit, bool *ignore_debugger)
1543{ 1543{
1544 int ret; 1544 int ret;
1545 bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode == 1545 bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode ==
1546 NVGPU_GR_PREEMPTION_MODE_CILP) ; 1546 NVGPU_COMPUTE_PREEMPTION_MODE_CILP) ;
1547 u32 global_mask = 0, dbgr_control0, global_esr_copy; 1547 u32 global_mask = 0, dbgr_control0, global_esr_copy;
1548 u32 offset = proj_gpc_stride_v() * gpc + 1548 u32 offset = proj_gpc_stride_v() * gpc +
1549 proj_tpc_in_gpc_stride_v() * tpc; 1549 proj_tpc_in_gpc_stride_v() * tpc;