diff options
author | Martin Radev <mradev@nvidia.com> | 2018-03-15 13:36:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-26 12:13:05 -0400 |
commit | c392a7270fd13fa0eb1e26ef0ef9f8f4479630a1 (patch) | |
tree | ab4713d743a277cc098ca017c603a5416a5cacd2 /drivers | |
parent | b1ac66d41855a9fa6bc6a29ff2259c93cae36532 (diff) |
gpu: nvgpu: Reset streaming on perfbuf_enable and perfbuf_disable
Similarly to css_hw_(enable|disable)_snapshot the HWPM
state should be reset on perfbuf_enable and perfbuf_disable
to avoid leaking snapshot data into a freshly mapped buffer.
Bug 1960846
Change-Id: I94826b209ef4b8cb6ad44d3b8667745270c6a7e1
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676009
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | 25 |
2 files changed, 50 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index fd31ab89..5d428afa 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -36,6 +36,27 @@ | |||
36 | #include <nvgpu/hw/gk20a/hw_therm_gk20a.h> | 36 | #include <nvgpu/hw/gk20a/hw_therm_gk20a.h> |
37 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 37 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
38 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> | 38 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> |
39 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
40 | |||
41 | static void gk20a_perfbuf_reset_streaming(struct gk20a *g) | ||
42 | { | ||
43 | u32 engine_status; | ||
44 | u32 num_unread_bytes; | ||
45 | |||
46 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | ||
47 | |||
48 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); | ||
49 | WARN_ON(0u == | ||
50 | (engine_status & perf_pmasys_enginestatus_rbufempty_empty_f())); | ||
51 | |||
52 | gk20a_writel(g, perf_pmasys_control_r(), | ||
53 | perf_pmasys_control_membuf_clear_status_doit_f()); | ||
54 | |||
55 | num_unread_bytes = gk20a_readl(g, perf_pmasys_mem_bytes_r()); | ||
56 | if (num_unread_bytes != 0u) { | ||
57 | gk20a_writel(g, perf_pmasys_mem_bump_r(), num_unread_bytes); | ||
58 | } | ||
59 | } | ||
39 | 60 | ||
40 | /* | 61 | /* |
41 | * API to get first channel from the list of all channels | 62 | * API to get first channel from the list of all channels |
@@ -316,6 +337,8 @@ int gk20a_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) | |||
316 | 337 | ||
317 | g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0); | 338 | g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0); |
318 | 339 | ||
340 | gk20a_perfbuf_reset_streaming(g); | ||
341 | |||
319 | virt_addr_lo = u64_lo32(offset); | 342 | virt_addr_lo = u64_lo32(offset); |
320 | virt_addr_hi = u64_hi32(offset); | 343 | virt_addr_hi = u64_hi32(offset); |
321 | 344 | ||
@@ -349,6 +372,8 @@ int gk20a_perfbuf_disable_locked(struct gk20a *g) | |||
349 | return err; | 372 | return err; |
350 | } | 373 | } |
351 | 374 | ||
375 | gk20a_perfbuf_reset_streaming(g); | ||
376 | |||
352 | gk20a_writel(g, perf_pmasys_outbase_r(), 0); | 377 | gk20a_writel(g, perf_pmasys_outbase_r(), 0); |
353 | gk20a_writel(g, perf_pmasys_outbaseupper_r(), | 378 | gk20a_writel(g, perf_pmasys_outbaseupper_r(), |
354 | perf_pmasys_outbaseupper_ptr_f(0)); | 379 | perf_pmasys_outbaseupper_ptr_f(0)); |
diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c index 562476ca..0dad7c2d 100644 --- a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | |||
@@ -25,6 +25,27 @@ | |||
25 | #include <nvgpu/log.h> | 25 | #include <nvgpu/log.h> |
26 | #include "gk20a/gk20a.h" | 26 | #include "gk20a/gk20a.h" |
27 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> | 27 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> |
28 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
29 | |||
30 | static void gv11b_perfbuf_reset_streaming(struct gk20a *g) | ||
31 | { | ||
32 | u32 engine_status; | ||
33 | u32 num_unread_bytes; | ||
34 | |||
35 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | ||
36 | |||
37 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); | ||
38 | WARN_ON(0u == | ||
39 | (engine_status & perf_pmasys_enginestatus_rbufempty_empty_f())); | ||
40 | |||
41 | gk20a_writel(g, perf_pmasys_control_r(), | ||
42 | perf_pmasys_control_membuf_clear_status_doit_f()); | ||
43 | |||
44 | num_unread_bytes = gk20a_readl(g, perf_pmasys_mem_bytes_r()); | ||
45 | if (num_unread_bytes != 0u) { | ||
46 | gk20a_writel(g, perf_pmasys_mem_bump_r(), num_unread_bytes); | ||
47 | } | ||
48 | } | ||
28 | 49 | ||
29 | int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) | 50 | int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) |
30 | { | 51 | { |
@@ -47,6 +68,8 @@ int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) | |||
47 | 68 | ||
48 | g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0); | 69 | g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0); |
49 | 70 | ||
71 | gv11b_perfbuf_reset_streaming(g); | ||
72 | |||
50 | virt_addr_lo = u64_lo32(offset); | 73 | virt_addr_lo = u64_lo32(offset); |
51 | virt_addr_hi = u64_hi32(offset); | 74 | virt_addr_hi = u64_hi32(offset); |
52 | 75 | ||
@@ -82,6 +105,8 @@ int gv11b_perfbuf_disable_locked(struct gk20a *g) | |||
82 | return err; | 105 | return err; |
83 | } | 106 | } |
84 | 107 | ||
108 | gv11b_perfbuf_reset_streaming(g); | ||
109 | |||
85 | gk20a_writel(g, perf_pmasys_outbase_r(), 0); | 110 | gk20a_writel(g, perf_pmasys_outbase_r(), 0); |
86 | gk20a_writel(g, perf_pmasys_outbaseupper_r(), | 111 | gk20a_writel(g, perf_pmasys_outbaseupper_r(), |
87 | perf_pmasys_outbaseupper_ptr_f(0)); | 112 | perf_pmasys_outbaseupper_ptr_f(0)); |